An equivalent inductance circuit synthesized based on metal-oxide-semiconductor field-effect transistors

Abstract

An equivalent inductor circuit synthesized based on a metal-oxide-semiconductor field-effect transistor, which relates to the field of radio frequency integrated circuits, includes: a first transconductance unit (1), a second transconductance unit (2), a first bias unit (3), a second bias unit (4), a first feedback resistor unit (5), a third transconductance unit (6), a fourth transconductance unit (7), a third bias unit (8), a fourth bias unit (9), and a second feedback resistor unit (10). The first transconductance unit, the first feedback resistor unit, and the second transconductance unit form a first loop, the third transconductance unit, the second feedback resistor unit, and the fourth transconductance unit form a second loop, and the first loop and the second loop have a common input terminal Z in , a power supply terminal V DD and a ground terminal GND, which form a parallel relationship. Finally, the equivalent inductor circuit realizes comprehensive performances of high Q value, large inductance value, high linearity of the L value, and low noise.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency integrated circuits, and particularly to an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor (MOS) field effect transistor (FET). Background Art

[0002] In radio frequency integrated circuits (RFICs), on-chip passive inductors are one of the commonly used components, usually formed by thin metal lines in a spiral shape. It not only has the disadvantage of large area, but also due to the existence of parasitic resistance, capacitance and substrate loss, it also results in low operating frequency and low quality factor value (Q) at high frequencies. In addition, since its geometric size is fixed, its performance parameter indicators are not tunable. These deficiencies severely limit its application in small-area, tunable, high-frequency, and high-performance RFICs. The equivalent inductance circuit synthesized by MOSFET (i.e., active inductor, AI) provides an attractive solution for replacing on-chip passive spiral inductors.

[0003] Currently, for the active inductor (AI) synthesized based on MOSFET, in order to improve one of the performance parameter indicators such as inductance value (L), Q value, L value linearity, and noise, one or more additional circuit units have to be introduced. If different performance parameter indicators need to be improved simultaneously, more additional circuits are required. This not only increases the complexity of the AI circuit, but also when improving one performance parameter indicator of the AI, it often inevitably degrades another performance parameter indicator. Therefore, the currently reported AI circuits are difficult to achieve high Q value, large inductance value, high L value linearity, and low noise in one AI circuit. Therefore, it is urgently necessary to optimize different transconductor circuit structures in the AI circuit simultaneously, and also to optimize the structures of different additional circuit units used to improve the Q value, L value, and L value linearity and their interconnections, so as to strengthen the versatility of the adopted additional circuit units to replace the single functionality and strengthen the tightness of the connections between different circuit units, achieving the purpose of reducing the number of circuit units, complementing each other, and forming a synergistic effect, so that a synthesized equivalent inductance circuit can take into account multiple performance parameters and finally achieve excellent comprehensive performance. Summary of the Invention

[0004] To address the above-mentioned deficiencies of current active inductors, the present invention innovatively proposes an equivalent inductance circuit synthesized based on metal-oxide-semiconductor field-effect transistors. A first loop is constructed by a first transconductance unit (1), a second transconductance unit (2), and a first feedback resistance unit (5), and a first bias unit (3) and a second bias unit (4) respectively provide DC biases for the first transconductance unit (1) and the second transconductance unit (2); a second loop is constructed by a third transconductance unit (6), a fourth transconductance unit (7), and a second feedback resistance unit (10), and a third bias unit (8) and a fourth bias unit (9) respectively provide DC biases for the third transconductance unit (6) and the fourth transconductance unit (7). Moreover, two MOS field-effect transistors in the third bias unit (8) and the fourth transconductance unit (7) are cross-coupled to generate a negative resistance, which, together with the first feedback resistance unit (5), the second feedback resistance unit (10), the second transconductance unit (2) configured as a cascode structure for modulation, and the fourth transconductance unit (7) configured as a cascode structure, jointly improve the Q value; further, the first loop and the second loop are connected in parallel between a common input terminal Z in , a power supply terminal V DD and a ground terminal GND, such that the positive feedback effect generated by the cross-coupling connection of two MOS field-effect transistors in the third bias unit (8) and the fourth transconductance unit (7) can simultaneously suppress the compression of the transconductance of the first transconductance unit (1) and the third transconductance unit (6), thereby improving the linearity of the L value of the active inductor. Ultimately, the present invention can simultaneously have a high Q value, a large inductance value, a high L value linearity, and low noise.

[0005] The present invention adopts the following technical solutions:

[0006] An equivalent inductance circuit synthesized based on metal-oxide-semiconductor field-effect transistors, the circuit topology is as Figure 1 shown, and it is characterized in that it is composed of a first transconductance unit (1), a second transconductance unit (2), a first bias unit (3), a second bias unit (4), a first feedback resistance unit (5), a third transconductance unit (6), a fourth transconductance unit (7), a third bias unit (8), a fourth bias unit (9), and a second feedback resistance unit (10). For the sake of convenient description, hereinafter, metal-oxide-semiconductor field-effect transistors will be abbreviated as MOS transistors.

[0007] The first transconductance unit (1) of the described equivalent inductance circuit synthesized based on metal-oxide-semiconductor field-effect transistors includes a first N-type MOS transistor (M1); the second transconductance unit (2) includes a second N-type MOS transistor (M2), a third N-type MOS transistor (M3), and has a first voltage bias terminal (V bias1) the fourth N-type MOS transistor (M4) and the fifth N-type MOS transistor (M5); the first bias unit (3) includes a sixth N-type MOS transistor (M6) having a second voltage bias terminal (V bias2 ) the second bias unit (4) includes a first passive resistor (R1), a seventh P-type MOS transistor (M7) and an eighth P-type MOS transistor (M8); the first feedback resistor unit (5) includes a second passive resistor (R2) and a ninth N-type MOS transistor (M9) having a third voltage bias terminal (V bias3 ) the third transconductance unit (6) includes a tenth N-type MOS transistor (M 10 ) the fourth transconductance unit (7) includes an eleventh N-type MOS transistor (M bias4 ) having a fourth voltage bias terminal (V 11 ) and a twelfth N-type MOS transistor (M 12 ) the third bias unit (8) includes a thirteenth N-type MOS transistor (M 13 ) the fourth bias unit (9) includes a fourteenth P-type MOS transistor (M bias5 ) having a fifth voltage bias terminal (V 14 ) the second feedback resistor unit (10) includes a third passive resistor (R3) and a fifteenth N-type MOS transistor (M bias6 ) having a sixth voltage bias terminal (V 15 ).

[0008] The input end Z of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field effect transistor in is simultaneously connected to the source of the first N-type MOS transistor (M1), the gate of the third N-type MOS transistor (M3), the drain of the sixth N-type MOS transistor (M6), the source of the tenth N-type MOS transistor (M 10 ), the gate of the twelfth N-type MOS transistor (M 12 ), and the drain of the thirteenth N-type MOS transistor (M 13 ); the drain of the first N-type MOS transistor (M1) is connected to the power supply terminal V DDare connected. The gate of the first N-type MOS transistor (M1) is simultaneously connected to the first end of the second passive resistor (R2) and the source of the ninth N-type MOS transistor (M9). The drain of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the eighth P-type MOS transistor (M8), the second end of the second passive resistor (R2), and the drain of the ninth N-type MOS transistor (M9). The gate of the second N-type MOS transistor (M2) is simultaneously connected to the source of the fourth N-type MOS transistor (M4) and the drain of the fifth N-type MOS transistor (M5). The source of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the third N-type MOS transistor (M3) and the gate of the fifth N-type MOS transistor (M5). The source of the third N-type MOS transistor (M3) is connected to the ground terminal GND. The drain of the fourth N-type MOS transistor (M4) is connected to the power supply terminal V DD is connected. The gate of the fourth N-type MOS transistor (M4) is connected to the first voltage bias terminal (V bias1 ). The source of the fifth N-type MOS transistor (M5) is connected to the ground terminal GND. The gate of the sixth N-type MOS transistor (M6) is connected to the second voltage bias terminal (V bias2 ). The source of the sixth N-type MOS transistor (M6) is connected to the ground terminal GND. The source of the seventh P-type MOS transistor (M7) is connected to the power supply terminal V DD . The gate of the seventh P-type MOS transistor (M7) is simultaneously connected to the gate of the eighth P-type MOS transistor (M8) and the first end of the first passive resistor (R1). The drain of the seventh P-type MOS transistor (M7) is connected to the first end of the first passive resistor (R1). The source of the eighth P-type MOS transistor (M8) is connected to the power supply terminal V DD . The second end of the first passive resistor (R1) is connected to the ground terminal GND. The gate of the ninth N-type MOS transistor (M9) is connected to the third voltage bias terminal (V bias3 ). The drain of the tenth N-type MOS transistor (M 10 ) is connected to the power supply terminal V DD . The gate of the tenth N-type MOS transistor (M 10 ) is simultaneously connected to the second end of the third passive resistor (R3) and the source of the fifteenth N-type MOS transistor (M 15 ). The drain of the eleventh N-type MOS transistor (M 11 ) is simultaneously connected to the first end of the third passive resistor (R3), the drain of the fifteenth N-type MOS transistor (M 15 ), and the drain of the fourteenth P-type MOS transistor (M 14 ). The gate of the eleventh N-type MOS transistor (M 11 ) is connected to the fourth voltage bias terminal (V bias4 ). The eleventh N-type MOS transistor (M11 )'s source electrode is simultaneously connected to the drain electrode of the twelfth N-type MOS transistor (M 12 ) and the gate electrode of the thirteenth N-type MOS transistor (M 13 ); the source electrode of the twelfth N-type MOS transistor (M 12 ) is connected to the ground terminal GND; the source electrode of the thirteenth N-type MOS transistor (M 13 ) is connected to the ground terminal GND; the gate electrode of the fourteenth P-type MOS transistor (M 14 ) is connected to the fifth voltage bias terminal (V bias5 ); the source electrode of the fourteenth P-type MOS transistor (M 14 ) is connected to the power supply terminal V DD ; the gate electrode of the fifteenth N-type MOS transistor (M 15 ) is connected to the sixth voltage bias terminal (V bias6 ).

[0009] The first transconductance unit (1) of the equivalent inductance circuit synthesized based on metal-oxide-semiconductor field effect transistors constitutes a positive transconductance device, and the second transconductance unit (2) constitutes a negative transconductance device. The first transconductance unit (1), the second transconductance unit (2), and the first feedback resistance unit (5) form a first loop through a negative feedback connection method, such that the impedance characteristic of the equivalent inductance circuit at the input terminal Z in exhibits an inductive characteristic. Further, the second N-type MOS transistor (M2), the third N-type MOS transistor (M3), the fourth N-type MOS transistor (M4) with the first voltage bias terminal (V bias1 ), and the fifth N-type MOS transistor (M5) of the second transconductance unit (2) together form a modulated cascode structure, reducing the equivalent series resistance of the equivalent inductance circuit, and thus increasing its Q value. The first feedback resistance unit (5) is composed of the second passive resistor (R2) and the ninth N-type MOS transistor (M9) with the third voltage bias terminal (V bias3 ), where the ninth N-type MOS transistor (M9) operates in the linear region and can be equivalent to a linear resistor. The resistance value of the linear resistor is regulated by the voltage magnitude of the third voltage bias terminal (V bias3 ). This linear resistor is connected in parallel with the second passive resistor (R2) to form an active-passive combined feedback resistor, reducing the equivalent series resistance of the equivalent inductance circuit and further increasing its Q value.

[0010] The third transconductance unit (6) of the equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field effect transistor forms a positive transconductor, and the fourth transconductance unit (7) forms a negative transconductor. The third transconductance unit (6), the fourth transconductance unit (7), and the second feedback resistor unit (10) form a second loop through a negative feedback connection method, so that the impedance characteristic of the equivalent inductance circuit at the input end Z in exhibits an inductive characteristic. Further, the eleventh N-type MOS transistor (M bias4 ) with the fourth voltage bias terminal (V 11 ) and the twelfth N-type MOS transistor (M 12 ) in the fourth transconductance unit (7) together form a cascode structure with two transistors, reducing the equivalent series resistance of the equivalent inductance circuit and thus increasing its Q value. The second feedback resistor unit (10) is composed of a third passive resistor (R3) and a fifteenth N-type MOS transistor (M bias6 ) with a sixth voltage bias terminal (V 15 ). Among them, the fifteenth N-type MOS transistor (M 15 ) operates in the linear region and can be equivalent to a linear resistor. The resistance value of the linear resistor is regulated by the voltage of the sixth voltage bias terminal (V bias6 ). This linear resistor is connected in parallel with the third passive resistor (R3) to form an active-passive combined feedback resistor, reducing the equivalent series resistance of the equivalent inductance circuit and further increasing its Q value.

[0011] Further, the thirteenth N-type MOS transistor (M 13 ) of the equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field effect transistor and the twelfth N-type MOS transistor (M 12 ) in the fourth transconductance unit (7) are connected in a cross-coupled manner to generate a positive feedback effect and generate a negative resistance. When the voltage V in at the input end Z in increases, that is, the drain voltage of the thirteenth N-type MOS transistor (M 13 ) increases, causing the gate voltage of the twelfth N-type MOS transistor (M 12 ) to increase and the drain voltage to decrease. Further, the gate voltage of the thirteenth N-type MOS transistor (M 13 ) decreases and the drain voltage continues to increase, causing the voltage V in at the input end Z in to further increase, forming a positive feedback loop. The generated negative resistance reduces the equivalent series resistance of the equivalent inductance circuit and further increases its Q value.

[0012] Further, the first loop and the second loop share a common input end Z in and the power supply end VDD in parallel with the ground terminal GND. As the voltage V in at the input terminal Z in increases, the drain current of the first transconductance unit (1), i.e., the first N-type MOS transistor (M1), will generate a second-order non-linear current I EX1 , and at the same time, the drain current of the third transconductance unit (6), i.e., the tenth N-type MOS transistor (M 10 ) will also generate a second-order non-linear current I EX10 , resulting in the compression of the transconductance g m1 of the first N-type MOS transistor (M1) and the transconductance g 10 of the tenth N-type MOS transistor (M m10 ), thereby causing non-linearity in the inductance value L of this equivalent inductance circuit. The sixth N-type MOS transistor (M6) provides the bias current for the first N-type MOS transistor (M1), and the thirteenth N-type MOS transistor (M 10 ) provides the bias current for the tenth N-type MOS transistor (M 13 ). Since the thirteenth N-type MOS transistor (M 13 ) and the twelfth N-type MOS transistor (M 12 ) in the fourth transconductance unit (7) are connected in a cross-coupled manner, the resulting positive feedback effect can suppress the second-order non-linear current I EX6 generated by the sixth N-type MOS transistor (M6) and the second-order non-linear current I 13 generated by the thirteenth N-type MOS transistor (M EX13 ), and further suppress the second-order non-linear currents I EX1 and I EX10 of the first transconductance unit (1) and the third transconductance unit (6), thereby improving the linearity of the inductance value L of this equivalent inductance circuit. In order to characterize the variation of the inductance value with the input signal, the -1dB compression point can be used to measure the linearity of the L value. The larger the L value linearity L -1dB , the more it indicates that the L value of the active inductor can remain constant within a wider dynamic range of the input signal, and the better the linearity.

[0013] Furthermore, for the equivalent inductance circuit obtained by paralleling the first loop and the second loop, as the frequency increases, the thermal noise at high frequencies continuously decreases. Therefore, this equivalent inductance circuit has good noise performance.

[0014] Further, the sixth N-type MOS transistor (M6) of the first bias unit (3) provides a DC bias for the first transconductance unit (1); the first passive resistor (R1), the seventh P-type MOS transistor (M7), and the eighth P-type MOS transistor (M8) of the second bias unit (4) form a current mirror structure to provide a DC bias for the second transconductance unit (2); the thirteenth N-type MOS transistor (M 13 ) of the third bias unit (8) provides a DC bias for the third transconductance unit (6); the fourteenth P-type MOS transistor (M 14 ) of the fourth bias unit (9) provides a DC bias for the fourth transconductance unit (7).

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] The present invention is composed of a first transconductance unit (1), a second transconductance unit (2), a first bias unit (3), a second bias unit (4), a first feedback resistor unit (5), a third transconductance unit (6), a fourth transconductance unit (7), a third bias unit (8), a fourth bias unit (9), and a second feedback resistor unit (10). Further, the first transconductance unit (1) constitutes a positive transconductor, the second transconductance unit (2) constitutes a negative transconductor, and in this negative transconductor, four transistors, namely the second N-type MOS transistor (M2), the third N-type MOS transistor (M3), the fourth N-type MOS transistor (M4), and the fifth N-type MOS transistor (M5), together form a modulated cascode structure. The first feedback resistor unit (has the ninth N-type MOS transistor (M9) and the second passive resistor (R2), and further they form an active-passive combined feedback resistor through a parallel connection. Moreover, the first transconductance unit (1), the first feedback resistor unit (5), and the second transconductance unit (2) are connected end to end to form a first loop, which exhibits inductive characteristics at the input terminal Z in and has a wide operating frequency band and a high Q value. The first bias unit (3) provides a DC bias for the first transconductance unit (1), and the second bias unit (4) provides a DC bias for the second transconductance unit (2); the third transconductance unit (6) constitutes a positive transconductor, the fourth transconductance unit (7) constitutes a negative transconductor, and in this negative transconductor, the eleventh N-type MOS transistor (M 11 ) and the twelfth N-type MOS transistor (M 12 ) together form a cascode structure. The second feedback resistor unit (10) is composed of the fifteenth N-type MOS transistor (M 15 ) and the third passive resistor (R3), and further they form an active-passive combined feedback resistor through a parallel connection. The thirteenth N-type MOS transistor (M 13 ) of the third bias unit (8) and the twelfth N-type MOS transistor (M 12)They are connected in a cross-coupled manner to produce a positive feedback effect and generate negative resistance. The third transconductance unit (6), the second feedback resistor unit (10), and the fourth transconductance unit (7) are connected end to end to form a second loop, at the input terminal Z in exhibits inductive characteristics and has a wide operating frequency band and a high Q value. The third bias unit (8) provides a DC bias for the third transconductance unit (6), and the fourth bias unit (9) provides a DC bias for the fourth transconductance unit (7). Further, the first loop and the second loop are connected in parallel between the common input terminal Z in , the power supply terminal V DD and the ground terminal GND. The positive feedback effect generated by the cross-coupling of the thirteenth N-type MOS transistor (M 13 ) and the twelfth N-type MOS transistor (M 12 ) can simultaneously suppress the transconductance g m1 of the first N-type MOS transistor (M1) and the transconductance g 10 of the tenth N-type MOS transistor (M m10 ) compression, thereby improving the linearity of the L value of the equivalent inductor circuit. Therefore, in the present invention, by configuring the negative transconductors in the first loop and the second loop into a modulated cascode structure and a basic cascode structure respectively, and cross-coupling the two MOS transistors in the third bias unit (8) and the fourth transconductance unit (7) to generate negative resistance, together with the first feedback resistor unit (5) and the second feedback resistor unit (10), the Q value of the active inductor is improved; at the same time, by utilizing the characteristic that the cross-coupling connection of the two MOS transistors in the third bias unit (8) and the fourth transconductance unit (7) in the second loop can also generate a positive feedback effect again, on the one hand, the linearity of the second loop is improved, and on the other hand, the first loop and the second loop are connected in parallel, and through the input terminal Z in , the positive feedback effect is fed into the first loop, and the linearity of the first loop is also improved. Finally, by simultaneously optimizing the circuit structures of different transconductors in the equivalent inductor circuit, the multifunctionality of the circuit unit is strengthened to replace the single functionality, the tightness of the connection between different circuit units is strengthened, and a synergistic effect is formed between different units, so that the equivalent inductor circuit of the present invention can simultaneously have a high Q value, a large inductance value, a high linearity of the L value, and low noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a topological diagram of an equivalent inductor circuit synthesized based on a metal-oxide-semiconductor field effect transistor according to the present invention. Among them, 1 - the first transconductance unit; 2 - the second transconductance unit; 3 - the first bias unit; 4 - the second bias unit; 5 - the first feedback resistor unit; 6 - the third transconductance unit; 7 - the fourth transconductance unit; 8 - the third bias unit; 9 - the fourth bias unit; 10 - the second feedback resistor unit.

[0018] Figure 2 It is a graph showing the relationship between the quality factor value Q and the frequency f of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor.

[0019] Figure 3 It is a graph showing the relationship between the inductance value L and the frequency f of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor.

[0020] Figure 4 It is a graph showing the relationship between the inductance value L of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor and the input signal voltage V in of.

[0021] Figure 5 It is a graph showing the relationship between the noise and the frequency f of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor. Detailed implementation manner

[0022] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings.

[0023] Figure 1 It is a topological diagram of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor according to the present invention. In the figure, it is composed of a first transconductance unit (1), a second transconductance unit (2), a first bias unit (3), a second bias unit (4), a first feedback resistance unit (5), a third transconductance unit (6), a fourth transconductance unit (7), a third bias unit (8), a fourth bias unit (9), and a second feedback resistance unit (10).

[0024] The first transconductance unit (1) of the equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor described above includes a first N-type MOS transistor (M1); the second transconductance unit (2) includes a second N-type MOS transistor (M2), a third N-type MOS transistor (M3), a fourth N-type MOS transistor (M4) having a first voltage bias terminal (V bias1 ) and a fifth N-type MOS transistor (M5); the first bias unit (3) includes a sixth N-type MOS transistor (M6) having a second voltage bias terminal (V bias2 ); the second bias unit (4) includes a first passive resistor (R1), a seventh P-type MOS transistor (M7), and an eighth P-type MOS transistor (M8); the first feedback resistance unit (5) includes a second passive resistor (R2) and a third voltage bias terminal (V bias3) the ninth N-type MOS transistor (M9); the third transconductance unit (6) includes a tenth N-type MOS transistor (M 10 ); the fourth transconductance unit (7) includes an eleventh N-type MOS transistor (M with a fourth voltage bias terminal (V bias4 )); the fourth transconductance unit (7) includes an eleventh N-type MOS transistor (M with a fourth voltage bias terminal (V 11 )) and a twelfth N-type MOS transistor (M 12 ); the third bias unit (8) includes a thirteenth N-type MOS transistor (M 13 ); the fourth bias unit (9) includes a fourteenth P-type MOS transistor (M with a fifth voltage bias terminal (V bias5 )) and a fourteenth P-type MOS transistor (M with a fifth voltage bias terminal (V 14 )); the second feedback resistor unit (10) includes a third passive resistor (R3) and a fifteenth N-type MOS transistor (M with a sixth voltage bias terminal (V bias6 )) and a fifteenth N-type MOS transistor (M with a sixth voltage bias terminal (V 15 ).

[0025] Specific embodiments of the present invention:

[0026] The input end Z of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field effect transistor as described in is simultaneously connected to the source of the first N-type MOS transistor (M1), the gate of the third N-type MOS transistor (M3), the drain of the sixth N-type MOS transistor (M6), the source of the tenth N-type MOS transistor (M 10 ), the gate of the twelfth N-type MOS transistor (M 12 ), and the drain of the thirteenth N-type MOS transistor (M 13 ); the drain of the first N-type MOS transistor (M1) is connected to the power supply terminal V DD , and the gate of the first N-type MOS transistor (M1) is simultaneously connected to the first end of the second passive resistor (R2) and the source of the ninth N-type MOS transistor (M9); the drain of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the eighth P-type MOS transistor (M8), the second end of the second passive resistor (R2), and the drain of the ninth N-type MOS transistor (M9), the gate of the second N-type MOS transistor (M2) is simultaneously connected to the source of the fourth N-type MOS transistor (M4) and the drain of the fifth N-type MOS transistor (M5), and the source of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the third N-type MOS transistor (M3) and the gate of the fifth N-type MOS transistor (M5); the source of the third N-type MOS transistor (M3) is connected to the ground terminal GND; the drain of the fourth N-type MOS transistor (M4) is connected to the power supply terminal V DD , and the gate of the fourth N-type MOS transistor (M4) is connected to the first voltage bias terminal (V bias1) are connected; the source of the fifth N-type MOS transistor (M5) is connected to the ground terminal GND; the gate of the sixth N-type MOS transistor (M6) is connected to the second voltage bias terminal (V bias2 ), and the source of the sixth N-type MOS transistor (M6) is connected to the ground terminal GND; the source of the seventh P-type MOS transistor (M7) is connected to the power supply terminal V DD , the gate of the seventh P-type MOS transistor (M7) is simultaneously connected to the gate of the eighth P-type MOS transistor (M8) and the first end of the first passive resistor (R1), and the drain of the seventh P-type MOS transistor (M7) is connected to the first end of the first passive resistor (R1); the source of the eighth P-type MOS transistor (M8) is connected to the power supply terminal V DD ; the second end of the first passive resistor (R1) is connected to the ground terminal GND; the gate of the ninth N-type MOS transistor (M9) is connected to the third voltage bias terminal (V bias3 ); the drain of the tenth N-type MOS transistor (M 10 ) is connected to the power supply terminal V DD , the gate of the tenth N-type MOS transistor (M 10 ) is simultaneously connected to the second end of the third passive resistor (R3) and the source of the fifteenth N-type MOS transistor (M 15 ); the drain of the eleventh N-type MOS transistor (M 11 ) is simultaneously connected to the first end of the third passive resistor (R3), the drain of the fifteenth N-type MOS transistor (M 15 ) and the drain of the fourteenth P-type MOS transistor (M 14 ), the gate of the eleventh N-type MOS transistor (M 11 ) is connected to the fourth voltage bias terminal (V bias4 ), the source of the eleventh N-type MOS transistor (M 11 ) is simultaneously connected to the drain of the twelfth N-type MOS transistor (M 12 ) and the gate of the thirteenth N-type MOS transistor (M 13 ); the source of the twelfth N-type MOS transistor (M 12 ) is connected to the ground terminal GND; the source of the thirteenth N-type MOS transistor (M 13 ) is connected to the ground terminal GND; the gate of the fourteenth P-type MOS transistor (M 14 ) is connected to the fifth voltage bias terminal (V bias5 ), the source of the fourteenth P-type MOS transistor (M 14 ) is connected to the power supply terminal V DD ; the gate of the fifteenth N-type MOS transistor (M 15 ) is connected to the sixth voltage bias terminal (V bias6 ).

[0027] Figure 2 It is a graph showing the relationship between the quality factor value Q and the frequency f of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor. It can be seen that the frequency band range where Q is greater than 1 is 0.53 GHz to 6.2 GHz (i.e., the bandwidth is 5.67 GHz), the frequency band range where Q is greater than 10 is 2.53 GHz to 5.32 GHz (i.e., the bandwidth is 2.79 GHz), the frequency band range where Q is greater than 100 is 3.71 GHz to 4.62 GHz (i.e., the bandwidth is 0.91 GHz), and at 4.2 GHz, the quality factor value Q reaches the maximum value (i.e., the peak value) of 122778. Therefore, this equivalent inductance circuit has achieved a very high Q value.

[0028] Figure 3 It is a graph showing the relationship between the inductance value L and the frequency f of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor. It can be seen that it exhibits inductance characteristics within a wide frequency band of 0 to 6.55 GHz, and at 6.11 GHz, the inductance value L reaches the maximum value (i.e., the peak value) of 14.798 nH. Therefore, this equivalent inductance circuit has achieved a wide operating frequency band and a large inductance value.

[0029] Figure 4 It is a graph showing the relationship between the inductance value L of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor and the input signal voltage V in . It can be seen that the linearity L -1dB of the inductance value L is -16.7 dBV. Therefore, this equivalent inductance circuit has achieved a high linearity of the L value.

[0030] Figure 5 It is a graph showing the relationship between the noise of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor field-effect transistor and the frequency f. It can be seen that the input-referred noise voltages at 1 GHz, 4.2 GHz, and 6.11 GHz are respectively and Therefore, this equivalent inductance circuit has achieved a lower noise.

[0031] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An equivalent inductance circuit synthesized based on a metal-oxide-semiconductor (MOS) field-effect transistor, characterized in that, It is composed of a first transconductance unit (1), a second transconductance unit (2), a first bias unit (3), a second bias unit (4), a first feedback resistor unit (5), a third transconductance unit (6), a fourth transconductance unit (7), a third bias unit (8), a fourth bias unit (9), and a second feedback resistor unit (10); Among them, the first transconductance unit (1) includes a first N-type MOS transistor (M1); the second transconductance unit (2) includes a second N-type MOS transistor (M2), a third N-type MOS transistor (M3), a fourth N-type MOS transistor (M4) with a first voltage bias terminal (V bias1 ) and a fifth N-type MOS transistor (M5); the first bias unit (3) includes a sixth N-type MOS transistor (M6) with a second voltage bias terminal (V bias2 ); the second bias unit (4) includes a first passive resistor (R1), a seventh P-type MOS transistor (M7) and an eighth P-type MOS transistor (M8); the first feedback resistor unit (5) includes a second passive resistor (R2) and a ninth N-type MOS transistor (M9) with a third voltage bias terminal (V bias3 ); the third transconductance unit (6) includes a tenth N-type MOS transistor (M 10 ); the fourth transconductance unit (7) includes an eleventh N-type MOS transistor (M bias4 ) with a fourth voltage bias terminal (V 11 ) and a twelfth N-type MOS transistor (M 12 ); the third bias unit (8) includes a thirteenth N-type MOS transistor (M 13 ); the fourth bias unit (9) includes a fourteenth P-type MOS transistor (M bias5 ) with a fifth voltage bias terminal (V 14 ); the second feedback resistor unit (10) includes a third passive resistor (R3) and a fifteenth N-type MOS transistor (M bias6 ) with a sixth voltage bias terminal (V 15 ); The input terminal Z of an equivalent inductance circuit synthesized based on a metal-oxide-semiconductor (MOS) field-effect transistor in is simultaneously connected to the source of the first N-type MOS transistor (M1), the gate of the third N-type MOS transistor (M3), the drain of the sixth N-type MOS transistor (M6), the source of the tenth N-type MOS transistor (M 10 ), the gate of the twelfth N-type MOS transistor (M 12 ), and the drain of the thirteenth N-type MOS transistor (M 13 ); the drain of the first N-type MOS transistor (M1) is connected to the power supply terminal V DD , and the gate of the first N-type MOS transistor (M1) is simultaneously connected to the first end of the second passive resistor (R2) and the source of the ninth N-type MOS transistor (M9); the drain of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the eighth P-type MOS transistor (M8), the second end of the second passive resistor (R2), and the drain of the ninth N-type MOS transistor (M9). The gate of the second N-type MOS transistor (M2) is simultaneously connected to the source of the fourth N-type MOS transistor (M4) and the drain of the fifth N-type MOS transistor (M5). The source of the second N-type MOS transistor (M2) is simultaneously connected to the drain of the third N-type MOS transistor (M3) and the gate of the fifth N-type MOS transistor (M5); the source of the third N-type MOS transistor (M3) is connected to the ground terminal GND; the drain of the fourth N-type MOS transistor (M4) is connected to the power supply terminal V DD , and the gate of the fourth N-type MOS transistor (M4) is connected to the first voltage bias terminal (V bias1 ); the source of the fifth N-type MOS transistor (M5) is connected to the ground terminal GND; the gate of the sixth N-type MOS transistor (M6) is connected to the second voltage bias terminal (V bias2 ), and the source of the sixth N-type MOS transistor (M6) is connected to the ground terminal GND; the source of the seventh P-type MOS transistor (M7) is connected to the power supply terminal V DD , the gate of the seventh P-type MOS transistor (M7) is simultaneously connected to the gate of the eighth P-type MOS transistor (M8) and the first end of the first passive resistor (R1), and the drain of the seventh P-type MOS transistor (M7) is connected to the first end of the first passive resistor (R1); the source of the eighth P-type MOS transistor (M8) is connected to the power supply terminal V DD ; the second end of the first passive resistor (R1) is connected to the ground terminal GND; the gate of the ninth N-type MOS transistor (M9) is connected to the third voltage bias terminal (V bias3 ); the drain of the tenth N-type MOS transistor (M 10 ) is connected to the power supply terminal V DD , and the tenth N-type MOS transistor (M 10 ) The gate of which is connected to the second terminal of the third passive resistor (R3) and the source of the fifteenth N-type MOS transistor (M 15 ) at the same time; The drain of the eleventh N-type MOS transistor (M 11 ) is connected to the first terminal of the third passive resistor (R3), the drain of the fifteenth N-type MOS transistor (M 15 ) and the drain of the fourteenth P-type MOS transistor (M 14 ) at the same time. The gate of the eleventh N-type MOS transistor (M 11 ) is connected to the fourth voltage bias terminal (V bias4 ). The source of the eleventh N-type MOS transistor (M 11 ) is connected to the drain of the twelfth N-type MOS transistor (M 12 ) and the gate of the thirteenth N-type MOS transistor (M 13 ) at the same time; The source of the twelfth N-type MOS transistor (M 12 ) is connected to the ground terminal GND; The source of the thirteenth N-type MOS transistor (M 13 ) is connected to the ground terminal GND; The gate of the fourteenth P-type MOS transistor (M 14 ) is connected to the fifth voltage bias terminal (V[[ID=2�]] bias5 ). The source of the fourteenth P-type MOS transistor (M 14 ) is connected to the power supply terminal V DD ; The gate of the fifteenth N-type MOS transistor (M 15 ) is connected to the sixth voltage bias terminal (V bias6 ).

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