Scheduling method and device

Abstract

This specification provides a scheduling method and apparatus, the method comprising: obtaining a memory access request initiated for a target memory; obtaining a thread unlocking quantity threshold for the target memory; wherein the thread unlocking quantity threshold is data determined based on a target description parameter corresponding to the memory access request, the target description parameter including a request description parameter for characterizing processing resources required for the memory access request and a device description parameter for characterizing processing resources provided by an electronic device where the target memory is located; scheduling an access thread that initiates the memory access request based on the thread unlocking quantity threshold so that the number of access threads in an unlocked state does not exceed the thread unlocking quantity threshold.

Description

Technical Field

[0001] This specification relates to the field of computer storage technology, and in particular to a scheduling method and device. Background Art

[0002] With the continuous advancement of computer storage technology, people have begun to use multiple types of memory simultaneously in the same electronic device to meet the functional requirements of complex storage scenarios. However, due to the differences in the physical structure of various memory types, the concurrent processing performance of different memories varies. This in turn may cause memory contention in the electronic device under partial load conditions, ultimately compromising the overall memory performance of the electronic device. Summary of the Invention

[0003] In view of this, this specification provides a scheduling method and device to solve the deficiencies in the related art.

[0004] Specifically, this specification is implemented through the following technical solutions:

[0005] According to a first aspect of an embodiment of this specification, a scheduling method is provided, the method comprising:

[0006] Get the memory access request initiated for the target memory;

[0007] Obtaining a thread unlock quantity threshold for the target memory; wherein the thread unlock quantity threshold is data determined based on target description parameters corresponding to the memory access request, the target description parameters including request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located;

[0008] The access thread that initiates the memory access request is scheduled according to the thread unlock quantity threshold, so that the number of access threads in the unlock state does not exceed the thread unlock quantity threshold.

[0009] According to a second aspect of the embodiments of this specification, a scheduling method is provided, the method comprising:

[0010] In response to a memory access request initiated for a target memory, obtaining corresponding target description parameters; wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located;

[0011] A thread unlocking number threshold for the target memory is determined based on the target description parameters, and the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0012] According to a third aspect of the embodiments of this specification, a scheduling device is provided, the device comprising:

[0013] A request acquisition unit, configured to acquire a memory access request initiated for a target memory;

[0014] a threshold acquisition unit, configured to acquire a thread unlocking quantity threshold for the target memory; wherein the thread unlocking quantity threshold is data determined based on target description parameters corresponding to the memory access request, the target description parameters including request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by the electronic device where the target memory is located;

[0015] The thread scheduling unit is used to schedule the access thread that initiates the memory access request according to the thread unlocking number threshold so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0016] According to a fourth aspect of the embodiments of this specification, a scheduling device is provided, the device comprising:

[0017] a parameter acquisition unit, configured to acquire corresponding target description parameters in response to a memory access request initiated for a target memory; wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located;

[0018] A threshold determination unit is used to determine a thread unlocking number threshold for the target memory based on the target description parameters, and the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0019] According to a fifth aspect of the embodiments of this specification, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the steps of the method described in the first and second aspects are implemented.

[0020] According to the sixth aspect of the embodiments of this specification, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method described in the first and second aspects are implemented.

[0021] The technical solution provided in this specification uses target description parameters to understand the current usage of the target memory, thereby dynamically and strategically limiting the number of concurrent memory access requests to the target memory. This avoids scheduling failures caused by changes in load characteristics, effectively mitigates memory contention under different load environments, and improves the overall performance of the electronic device.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0024] Figure 1 This is a schematic diagram of the architecture of a scheduling system shown in an exemplary embodiment of this specification;

[0025] Figure 2 is a flowchart of a scheduling method shown in an exemplary embodiment of this specification;

[0026] Figure 3 is a flowchart illustrating a method for determining a thread unlock quantity threshold according to an exemplary embodiment of this specification;

[0027] Figure 4 is a flowchart of another scheduling method shown in an exemplary embodiment of this specification;

[0028] Figure 5 is a schematic diagram of a scheduling method shown in an exemplary embodiment of this specification;

[0029] Figure 6 is a flowchart illustrating a process of processing a memory access request according to an exemplary embodiment of this specification;

[0030] Figure 7 is a schematic structural diagram of an electronic device shown in an exemplary embodiment of this specification;

[0031] Figure 8is a structural diagram of a scheduling device shown in an exemplary embodiment of this specification;

[0032] Figure 9 It is a structural diagram of another scheduling device shown in an exemplary embodiment of this specification. DETAILED DESCRIPTION

[0033] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of this specification.

[0034] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a," "the," and "the" used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0035] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information without departing from the scope of this specification. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0036] Dynamic Random Access Memory (DRAM), a type of volatile memory, has become a staple of modern memory architectures thanks to its low cost, low access latency, and high processing performance. However, due to limitations in its physical structure and storage principles, DRAM cannot provide persistent data storage, and is therefore increasingly unable to meet the needs of users in complex storage scenarios.

[0037] On this basis, with the continuous development of non-volatile memory (NVM) technology, some types of non-volatile memory have evolved the above-mentioned modern memory architecture from a single memory architecture to a heterogeneous memory architecture through their access latency close to DRAM, support for byte-addressable interfaces, and the ability to use memory interfaces and memory channels like DRAM while supporting persistent data storage functions.

[0038] Below Figure 1 For specific instructions, Figure 1 This is a schematic diagram of the architecture of a scheduling system shown in an exemplary embodiment of this specification. Figure 1 As shown, it may include a memory group 11 and a memory scheduler 12.

[0039] Memory group 11 includes multiple types of memory installed in the same electronic device, each with different concurrent processing capabilities. During system operation, these multiple types of memory handle corresponding concurrent memory access requests based on the memory scheduling policy of memory scheduler 12. The efficiency of processing concurrent memory access requests is positively correlated with the concurrent processing capabilities of the corresponding memory.

[0040] The memory scheduler 12 can be a software programming framework for optimizing memory access control in the above-mentioned electronic device, or a hardware device solidified based on the above-mentioned software programming framework and set in the above-mentioned electronic device. At the same time, the memory scheduler 12 can be used to receive memory access requests from applications carried by the above-mentioned electronic device and control the execution of the memory access requests. Furthermore, during the operation of the system, the above-mentioned memory access request is initiated by the access thread corresponding to the above-mentioned application. After receiving the above-mentioned memory access request, the memory scheduler 12 can change the execution state of the access thread according to the preset memory scheduling policy to control the execution of the corresponding memory access request.

[0041] Among them, the above-mentioned electronic devices can be mobile phones, tablet devices, laptops, PDAs (Personal Digital Assistants), wearable devices (such as smart glasses, smart watches, etc.), and other hardware devices that support the simultaneous assembly and use of multiple memories. One or more embodiments of this specification are not limited to this.

[0042] It will be understood by those skilled in the art that the correlation between the above-mentioned heterogeneous memory architecture and the architecture implemented by the memory group 11 is not necessary: on the one hand, the concurrent processing capabilities of memories of different architectures in the related art (such as DRAM and Optane non-volatile memory) are usually completely different. Therefore, in this application, all memories in the above-mentioned heterogeneous memory architecture will be assumed to have different concurrent processing capabilities, that is, the memory group 11 can be implemented based on the above-mentioned heterogeneous memory architecture; on the other hand, even memories of the same architecture may be further divided into multiple subtypes of memory according to different physical structures. Taking non-volatile memory as an example: it can be subdivided into AEP (Apache pass) memory (such as the above-mentioned Optane non-volatile memory), PCM (Phase-Change Memory), MRAM (Magnetoresistive RandomAccess Memory) and other subtypes of memory. Among them, the above-mentioned subtypes of memory may also have different concurrent processing capabilities, so that the memory group 11 can also be implemented based on a homogeneous memory architecture rather than a heterogeneous memory architecture. The above-mentioned homogeneous memory architecture is opposite to the heterogeneous memory architecture, which can be represented as the above-mentioned electronic device being equipped with and using multiple memories corresponding to the same architecture at the same time.

[0043] As mentioned above, since the above-mentioned various memories can all use corresponding memory interfaces and memory channels, people can deploy and use them simultaneously in the same electronic device to achieve functional complementarity. Taking the existence of non-volatile memory and DRAM in memory group 11 as an example, DRAM can ensure high-performance data processing, and non-volatile memory can achieve fast data persistence, thereby achieving the above-mentioned functional complementarity. However:

[0044] Because the above-mentioned multiple memories can all use corresponding memory interfaces and memory channels, there is a situation where the above-mentioned multiple memories occupy the memory bandwidth of the same memory controller. Among them, when at least one memory processes memory access requests under intensive and high-concurrency loads, the throughput performance of other memories may be seriously affected, thereby causing the performance of applications that need to use the above-mentioned other memories to decline. At the same time, since the concurrent requests that the memory that processes the above-mentioned access requests can only handle are limited, the processing performance of the overall memory is difficult to be further improved. The above phenomenon is called "memory contention phenomenon", in which memory load characteristics can be used as a technical means to quantify and determine various memory load conditions, and the content and method of obtaining the above-mentioned memory load characteristics have been basically disclosed in the relevant technology, and this specification will not elaborate on them here.

[0045] In order to avoid or reduce the occurrence of the above-mentioned memory contention phenomenon, it is usually necessary to simply reduce the number of access threads set for one or more memories in the application to reduce the load pressure on the targeted memory, and finally control the load of all memories within a preset stable range to handle concurrent memory access requests, thereby ensuring the overall memory throughput performance. However, the above-mentioned application is unable to understand the current load of the memory from a global perspective of the system, and thus sets the number of access threads unreasonably, which leads to a decline in the performance of the overall memory in the above-mentioned electronic device. Taking the case of non-volatile memory as an example, the performance of non-volatile memory may decline due to an insufficient number of access threads set in the application, or memory contention may occur due to an excessive number of access threads, affecting the access performance of other memories and reducing the performance of other applications running in other memories.

[0046] Therefore, this specification proposes the following technical solutions to solve the above problems.

[0047] The following combination Figure 2 The illustrated embodiments illustrate the technical solutions of this specification. Figure 2 This is a flowchart of a scheduling method shown in an exemplary embodiment of this specification. Figure 2 As shown, the method may include the following steps:

[0048] S201, in response to a memory access request initiated for a target memory, obtain corresponding target description parameters; wherein the target description parameters include request description parameters for characterizing the processing resources required for the memory access request, and device description parameters for characterizing the processing resources provided by the electronic device where the target memory is located.

[0049] When any application needs to access data stored in the target memory, it can initiate a memory access request to the target memory through the access thread described below. The electronic device can obtain the corresponding target description parameters for the memory access request, which are then used to determine the thread unlock quantity threshold described below. The multiple types of memory described above can include volatile memory and non-volatile memory. At the same time, the target memory can be the non-volatile memory described above, which is not limited in this specification.

[0050] The above-mentioned memory access request may be one or more, and each memory access request corresponds to a set of request description parameters, which can be used to describe the processing resources required for the corresponding memory access request, such as the request length and / or request type of the memory access request. Among them, the request length can be the overall content of the memory access request, or the byte length of part of the content (such as key information, payload part), and the request type can be divided into read type and write type. In the case where there are multiple memory access requests, the request description parameter can be the average request length and read-write type ratio of the memory access request, wherein the average request length is the average value of the request length of each memory access request in the multiple memory access requests, and the read-write type ratio is the ratio of read-type and write-type memory access requests in the multiple memory access requests. Of course, the above-mentioned average value or read-write type ratio can be determined as a decimal or a positive integer after rounding according to actual usage requirements, and this is not limited in the present application.

[0051] Furthermore, the device description parameters can be used to describe the deployment of various devices within an electronic device, such as the number of memory devices deployed within the electronic device. This number can be further broken down into the total number of all memory devices or the sub-numbers corresponding to each type of memory. Furthermore, the device description parameters are typically fixed and can be obtained from user-preset information or system information, and this specification does not impose any restrictions on this.

[0052] It will be understood by those skilled in the art that, on the one hand, the request length of the above-mentioned memory access request is generally positively correlated with the load pressure of the corresponding memory. In other words, the longer the request length, the greater the processing resources required for the corresponding memory access request, the greater the processing resources that the electronic device needs to provide, and the more likely the corresponding memory is to be in an overloaded state. As for the request type, in fact, whether it is a read type or a write type has little impact on the processing resources required for a single memory access request, but for determining the processing resources required for a large number of concurrent memory access requests, the above-mentioned read-write type ratio has a certain influence, and the actual effect of its influence can be changed according to actual use requirements and hardware deployment, and this specification does not limit this. On the other hand, the number of memory devices is negatively correlated with the load pressure of the corresponding memory. For example, the more memory devices of a certain type there are, the more concurrent memory access requests it can process at the same time, and the more likely the corresponding memory is to be in a normal load state.

[0053] S202, determining a thread unlocking number threshold for the target memory according to the target description parameters, wherein the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0054] The above thread unlock quantity threshold can be set in different determination methods according to different usage requirements.

[0055] In one embodiment, the target description parameters can be input into a predefined threshold calculation formula, and the calculation result output by the threshold calculation formula is determined as the thread unlocking threshold. Since the threshold calculation formula is relatively fixed and simple, it takes less time to determine the thread unlocking threshold and uses less system resources. For example:

[0056] TS=k*Um*Wr / S

[0057] The above TS is the thread unlocking threshold, the above k is the adjustment parameter, the above Um is the expected maximum throughput of the target memory, the above Wr is the read-write type ratio, and the above S is the normalized single-thread processing capability corresponding to the memory access request size.

[0058] Correspondingly, the calculation formula for the number of unlocked threads can also be obtained based on the above threshold calculation formula:

[0059] T=k*Uc*Wr / S

[0060] The above T is the number of access threads currently in the unlocked state, and the above Uc is the current actual throughput capacity of the target memory.

[0061] Among them, the above-mentioned adjustment parameter k can be an empirical value determined based on experience, an experimental value determined based on experiments, or a value automatically determined based on an algorithm. At the same time, the above-mentioned adjustment parameter k can be used to participate in the calculation of the thread unlocking number threshold and adjust the size of the calculation result finally output by the threshold calculation formula to reduce the error value between the calculation result and the actual result. As for the expected maximum throughput capacity Um of the target memory, the current actual throughput capacity Uc and the normalized single-thread processing capacity S of the corresponding memory access request size, the three can be determined based on the above-mentioned target description parameters such as the average request length and / or the number of memory devices. At the same time, the specific calculation method for the three also varies according to different actual conditions, and this manual does not limit this.

[0062] In another embodiment, the target description parameters can be input into a pre-trained threshold prediction model, and the calculation result output by the threshold prediction model can be determined as the thread unlock quantity threshold. The threshold prediction model can be a model obtained by training a constructed calculation model based on a sample set to be trained. The calculation model can be a neural network model, which is not limited in this application. In particular, when the neural network model belongs to supervised learning, the sample set to be trained can include sample target description parameters corresponding to sample memory access requests, and each sample target description parameter is added with a training label, wherein the training label can be used to characterize the thread unlock quantity threshold of the access thread corresponding to the sample memory access request.

[0063] The process of determining the thread unlocking threshold based on the threshold prediction model can be referred to Figure 3 The method shown, Figure 3 FIG. 1 is a flow chart showing a method for determining a thread unlocking threshold according to an exemplary embodiment of the present specification. Figure 3 As shown, taking determining the thread unlocking quantity threshold corresponding to the non-volatile memory as an example, the method may include the following steps:

[0064] S301: Count the request lengths of all memory access requests.

[0065] S302, calculating the average request length S.

[0066] In one embodiment, the non-volatile memory requests may be continuously monitored by the electronic device. In other words, the electronic device may obtain all non-volatile memory requests within a preset time period and determine an average request length S based on the request length of each non-volatile memory request.

[0067] S303: Count the read and write modes of all non-volatile memory requests.

[0068] S304: Calculate the read-write type ratio Wr.

[0069] In one embodiment, similar to the average request length S, the above-mentioned electronic device can also obtain all non-volatile memory requests within a preset time period, and determine the ratio Wr of the read and write types of all non-volatile memory requests within the preset time period by a numerical type such as "20%:80%", "3:2", etc. according to the request type of each non-volatile memory request.

[0070] S305: Obtain the number N of non-volatile memory devices.

[0071] In one embodiment, the electronic device may directly obtain the number N of corresponding non-volatile memory devices by querying system information.

[0072] S306, obtaining the user-defined impact factor Tmc.

[0073] In one embodiment, the above-mentioned influencing factor Tmc can be an empirical value determined based on experience, an experimental value determined based on experiments, or a value automatically determined based on an algorithm. The above-mentioned influencing factor is similar to the above-mentioned adjustment parameter, and can be used to participate in the calculation of the thread unlocking quantity threshold and adjust the size of the calculation result finally output by the threshold prediction model to reduce the error value between the calculation result and the actual result.

[0074] S307, input S, Wr, N, and Tmc into the threshold prediction model.

[0075] S308, the threshold prediction model outputs the calculation result Ts.

[0076] In one embodiment, the threshold prediction model outputs a calculation result Ts based on the input parameters such as S, Wr, N, Tmc, etc., wherein the calculation result can be a positive integer.

[0077] S309: Determine the thread unlocking number threshold TS as Ts.

[0078] In one embodiment, when the thread unlocking number threshold TS does not exist, the calculation result Ts is directly determined as the thread unlocking number threshold TS; otherwise, the calculation result Ts is updated to a new thread unlocking number threshold TS.

[0079] S310, waiting for a fixed time period.

[0080] In one embodiment, considering the need for the electronic device to run for a long time and the differences in concurrent memory access requests in different time periods, a fixed time period can be designed to repeatedly execute S301 to S309 to ensure timely adjustment of the scheduling strategy so that the thread unlocking number threshold matches the actual situation.

[0081] After determining the thread unlock quantity threshold, the electronic device may schedule the memory access request, wherein the scheduling operation will be described in the following Figure 5 The corresponding embodiments are described in detail and will not be described in detail in this specification.

[0082] The following combination Figure 4 The illustrated embodiments illustrate the technical solutions of this specification. Figure 4 This is a flowchart of another scheduling method shown in an exemplary embodiment of this specification. Figure 4 As shown, the method may include the following steps:

[0083] S401: Obtain a memory access request initiated for a target memory.

[0084] When any application needs to access data stored in the target memory, it can initiate a memory access request to the target memory through the access thread described below. The multiple types of memory described above may include volatile memory and non-volatile memory. At the same time, the target memory may be the non-volatile memory described above, which is not limited in this specification.

[0085] S402, obtaining a thread unlocking number threshold for the target memory; wherein the thread unlocking number threshold is data determined based on a target description parameter corresponding to the memory access request, the target description parameter including a request description parameter for characterizing processing resources required for the memory access request, and a device description parameter for characterizing processing resources provided by the electronic device where the target memory is located.

[0086] The electronic device may obtain corresponding target description parameters for the memory access request, and then use them to determine the thread unlocking quantity threshold. The thread unlocking quantity threshold may be set in different determination methods according to different usage requirements.

[0087] In one embodiment, the target description parameters can be input into a predefined threshold calculation formula, and the result of the threshold calculation formula is used as the thread unlock threshold. The threshold calculation formula is relatively fixed and simple, so determining the thread unlock threshold takes less time and consumes less system resources.

[0088] In another embodiment, the target description parameters can be input into a pre-trained threshold prediction model, and the calculation result output by the threshold prediction model can be determined as the thread unlock quantity threshold. The threshold prediction model can be a model obtained by training a constructed calculation model based on a sample set to be trained. The calculation model can be a neural network model, which is not limited in this application. In particular, when the neural network model belongs to supervised learning, the sample set to be trained can include sample target description parameters corresponding to sample memory access requests, and each sample target description parameter is added with a training label, wherein the training label can be used to characterize the thread unlock quantity threshold of the access thread corresponding to the sample memory access request.

[0089] The process of determining the thread unlock quantity threshold based on the threshold prediction model can be referred to above. Figure 3 The method shown in this specification will not be described in detail here.

[0090] The above-mentioned memory access request may be one or more, and each memory access request corresponds to a set of request description parameters, which can be used to describe the processing resources required for the corresponding memory access request, such as the request length and / or request type of the memory access request. Among them, the request length can be the overall content of the memory access request, or the byte length of part of the content (such as key information, payload part), and the request type can be divided into read type and write type. In the case where there are multiple memory access requests, the request description parameter can be the average request length and read-write type ratio of the memory access request, wherein the average request length is the average value of the request length of each memory access request in the multiple memory access requests, and the read-write type ratio is the ratio of read-type and write-type memory access requests in the multiple memory access requests. Of course, the above-mentioned average value or read-write type ratio can be determined as a decimal or a positive integer after rounding according to actual usage requirements, and this is not limited in the present application.

[0091] Furthermore, the device description parameters can be used to describe the deployment of various devices within an electronic device, such as the number of memory devices deployed within the electronic device. This number can be further broken down into the total number of all memory devices or the sub-numbers corresponding to each type of memory. Furthermore, the device description parameters are typically fixed and can be obtained from user-preset information or system information, and this specification does not impose any restrictions on this.

[0092] It will be understood by those skilled in the art that, on the one hand, the request length of the above-mentioned memory access request is generally positively correlated with the load pressure of the corresponding memory. In other words, the longer the request length, the greater the processing resources required for the corresponding memory access request, the greater the processing resources that the electronic device needs to provide, and the more likely the corresponding memory is to be in an overloaded state. As for the request type, in fact, whether it is a read type or a write type has little impact on the processing resources required for a single memory access request, but for determining the processing resources required for a large number of concurrent memory access requests, the above-mentioned read-write type ratio has a certain influence, and the actual effect of its influence can be changed according to actual use requirements and hardware deployment, and this specification does not limit this. On the other hand, the number of memory devices is negatively correlated with the load pressure of the corresponding memory. For example, the more memory devices of a certain type there are, the more concurrent memory access requests it can process at the same time, and the more likely the corresponding memory is to be in a normal load state.

[0093] S403: Scheduling the access thread that initiates the memory access request according to the thread unlocking number threshold, so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0094] The above scheduling operation actually controls and manages the execution status of the above memory access request by utilizing the thread lock mechanism of the access thread.

[0095] In one embodiment, the electronic device may determine the number of access threads in the unlocked state as an initial number, and compare the initial number with the acquired thread unlocking number threshold: if the initial number is greater than or equal to the thread unlocking number threshold, the access thread is set to the locked state; if the initial number is less than the thread unlocking number threshold, the access thread is set to the unlocked state. Because the thread lock mechanism stipulates that the electronic device can process access threads in the unlocked state while not allowing the electronic device to perform any operations on access threads in the locked state, the number of concurrent memory access requests that can be processed simultaneously by the target memory is limited to a reasonable range to avoid the occurrence of the memory contention phenomenon.

[0096] The process of scheduling concurrent memory access requests can be referred to Figure 5 , Figure 5 This is a schematic diagram of a scheduling method shown in an exemplary embodiment of this specification. Figure 5 As shown, taking determining the access thread corresponding to the non-volatile memory as an example, the method may include the following contents:

[0097] Assume that there is a memory scheduler in an electronic device that can receive non-volatile memory access requests initiated by all access threads for non-volatile memory (i.e., non-volatile memory access threads). Each non-volatile memory access thread can correspond to a memory access request, and each memory access request includes a memory access request message. Assume that there are four non-volatile memory access threads 1 to 4, and each access thread initiates memory access requests 1, 2, 3, and 4, respectively.

[0098] The memory scheduler can obtain the corresponding target description parameters by counting each memory access request information, and then calculate the corresponding thread unlock quantity threshold. Taking the non-volatile memory access threads 1-4 as an example, their request lengths are a1, a2, a3, and a4, respectively. Access threads 1 and 2 are read-type access requests, and access threads 3 and 4 are write-type access requests. Then, it can be determined that the average request length of the non-volatile memory access threads 1-4 is (a1+a2+a3+a4) / 4, and the read-write type ratio is "1:1". At the same time, the electronic device is equipped with only one non-volatile memory device. Then, the electronic device can input the above parameters and the preset influencing factors into the threshold prediction model to obtain a calculation result of "2", which is then determined as the thread unlock quantity threshold.

[0099] The above-mentioned memory scheduler can compare the above-mentioned thread unlocking number threshold with the initial number of access threads currently in the unlocked state to determine the control operation of the thread lock for each non-volatile memory access thread. Assume that by counting the thread lock status, it is found that there is currently only one access thread in the unlocked state. Obviously, since the above-mentioned initial number is less than the above-mentioned thread unlocking number threshold, one access thread can be selected from the remaining three and set to the unlocked state. Correspondingly, if there are currently three access threads in the unlocked state, since the above-mentioned initial number is greater than or equal to the above-mentioned thread unlocking number threshold, no substantial operation can be performed on the thread lock of any access thread. Among them, the above-mentioned operation of selecting a part of the access threads to be set to the unlocked state from multiple access threads can be based on a preset selection rule or a random algorithm to determine the access threads that need / do not need to be unlocked, and this specification does not limit this.

[0100] When the access thread is in the unlocked state, the memory access request initiated by it can be executed normally.

[0101] The following analyzes the process of a single access thread initiating a memory access request from the perspective of the access thread. Figure 6 FIG. 1 is a flow chart of processing a memory access request according to an exemplary embodiment of this specification. Figure 6 As shown, still taking the access thread of non-volatile memory as an example, the method may include the following steps:

[0102] S601: Determine whether a non-volatile memory thread issues a memory access request.

[0103] In one embodiment, the electronic device determines whether the non-volatile memory thread initiates a memory access request for the non-volatile memory. If so, step S602 is executed; otherwise, step S601 is repeatedly executed.

[0104] Those skilled in the art will appreciate that, to prevent the non-volatile memory thread from frequently executing S601 when no memory access request is initiated, a minimum operation interval or a maximum number of executions within a preset time period may be set between the two operations.

[0105] S602: Determine whether the access thread is in unlocked state.

[0106] In one embodiment, it is determined whether the access thread of the non-volatile memory thread is in unlocked state. If so, S603 is executed, otherwise S602 is repeatedly executed. The process of repeatedly executing S602 is basically the same as S601 and will not be repeated here.

[0107] S603: Request access to non-volatile memory.

[0108] In one embodiment, since the access thread is in an unlocked state, the memory access request can be executed normally.

[0109] S604, request return.

[0110] In one embodiment, the non-volatile memory returns a corresponding execution result to the access thread in response to the memory access request.

[0111] S605: Change the access thread to a locked state.

[0112] In one embodiment, assuming that the access thread is locked by default, when the memory access request is processed, the access thread is restored to the locked state. Correspondingly, assuming that the access thread is unlocked by default, when the memory access request is processed, no processing is performed on the thread lock state of the access thread.

[0113] It can be seen from the above embodiments that this specification dynamically and strategically limits the number of concurrent memory access requests by obtaining target description parameters, thereby avoiding the failure of the original scheduling strategy due to changes in the load of the target memory, and effectively alleviating memory contention under different load environments, thereby improving the overall performance of the entire memory system.

[0114] Figure 7 This is a schematic structural diagram of an electronic device in an exemplary embodiment. Figure 7 At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include other required hardware. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a scheduling device for concurrent memory access requests at the logical level. Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0115] Corresponding to the aforementioned embodiment of the method for scheduling concurrent memory access requests, this specification also provides an embodiment of an apparatus for scheduling concurrent memory access requests.

[0116] Please refer to Figure 8 , Figure 8 FIG. 1 is a schematic diagram showing the structure of a scheduling device according to an exemplary embodiment. Figure 8 As shown, in a software implementation, the device may include:

[0117] A parameter acquisition unit 801 is configured to acquire corresponding target description parameters in response to a memory access request initiated for a target memory; wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located;

[0118] A threshold determination unit 802 is used to determine a thread unlocking number threshold for the target memory based on the target description parameters, and the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0119] Optionally, the threshold determination unit 802 is specifically configured to:

[0120] Inputting the target description parameter into a predefined threshold calculation formula, and determining the calculation result output by the threshold calculation formula as the thread unlocking quantity threshold; or,

[0121] The target description parameters are input into a threshold prediction model generated by pre-training, and the calculation result output by the threshold prediction model is determined as the thread unlock quantity threshold; wherein, the threshold prediction model is a model obtained by training a constructed calculation model based on a sample set to be trained, and the sample set to be trained includes sample target description parameters corresponding to sample memory access requests, and each sample target description parameter is added with a training label, and the training label is used to characterize the thread unlock quantity threshold of the access thread corresponding to the sample memory access request.

[0122] Optionally, the request description parameter includes at least one of the following: an average request length and a read-write type ratio of the memory access request;

[0123] The device description parameters include: the number of memory devices deployed in the electronic device.

[0124] Optionally, the memory in the electronic device where the target memory is located includes a volatile memory and a non-volatile memory, and the target memory is the non-volatile memory.

[0125] Please refer to Figure 9 , Figure 9 FIG. 1 is a schematic diagram showing the structure of another scheduling device according to an exemplary embodiment. Figure 9 As shown, in a software implementation, the device may include:

[0126] A request obtaining unit 901 is configured to obtain a memory access request initiated for a target memory;

[0127] A threshold acquisition unit 902 is configured to acquire a thread unlocking quantity threshold for the target memory; wherein the thread unlocking quantity threshold is data determined based on target description parameters corresponding to the memory access request, wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by the electronic device where the target memory is located;

[0128] The thread scheduling unit 903 is configured to schedule the access thread that initiates the memory access request according to the thread unlocking number threshold, so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

[0129] Optionally, the process of determining the thread unlock quantity threshold is as follows:

[0130] Inputting the target description parameter into a predefined threshold calculation formula, and determining the calculation result output by the threshold calculation formula as the thread unlocking quantity threshold; or,

[0131] The target description parameters are input into a threshold prediction model generated by pre-training, and the calculation result output by the threshold prediction model is determined as the thread unlock quantity threshold; wherein, the threshold prediction model is a model obtained by training a constructed calculation model based on a sample set to be trained, and the sample set to be trained includes sample target description parameters corresponding to sample memory access requests, and each sample target description parameter is added with a training label, and the training label is used to characterize the thread unlock quantity threshold of the access thread corresponding to the sample memory access request.

[0132] Optionally, the request description parameter includes at least one of the following: an average request length and a read-write type ratio of the memory access request;

[0133] The device description parameters include: the number of memory devices deployed in the electronic device.

[0134] Optionally, the thread scheduling unit 903 is specifically configured to:

[0135] Determine the number of access threads in an unlocked state as an initial number, and compare the initial number with the thread unlocking number threshold;

[0136] When the initial number is greater than or equal to the thread unlocking number threshold, setting the access thread to a locked state;

[0137] When the initial number is smaller than the thread unlocking number threshold, the access thread is set to an unlocked state.

[0138] Optionally, the device further includes:

[0139] The state recovery unit 904 is configured to restore the access thread to the locked state when the access thread is in the locked state by default and the memory access request processing is completed.

[0140] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0141] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0142] Embodiments of the subject matter and functional operations described in this specification may be implemented in the following: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information and transmit it to a suitable receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0143] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform the corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0144] Computers suitable for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or the computer will be operably coupled to such mass storage devices to receive data from them or to transmit data to them, or both. However, a computer does not necessarily have such devices. In addition, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0145] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0146] Although this specification includes many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of specific embodiments of specific inventions. Certain features described in multiple embodiments within this specification may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may work in certain combinations as described above and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may point to a sub-combination or a variation of the sub-combination.

[0147] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these operations be performed in the particular order shown or performed sequentially, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0148] Thus, specific embodiments of the subject matter have been described. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0149] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A scheduling method, comprising: Get the memory access request initiated for the target memory; Obtaining a thread unlock quantity threshold for the target memory; wherein the thread unlock quantity threshold is data determined based on target description parameters corresponding to the memory access request, the target description parameters including request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located; The access thread that initiates the memory access request is scheduled according to the thread unlock quantity threshold, so that the number of access threads in the unlock state does not exceed the thread unlock quantity threshold.

2. According to the method of claim 1, the process of determining the thread unlock quantity threshold is as follows: Inputting the target description parameter into a predefined threshold calculation formula, and determining the calculation result output by the threshold calculation formula as the thread unlocking quantity threshold; or, The target description parameters are input into a threshold prediction model generated by pre-training, and the calculation result output by the threshold prediction model is determined as the thread unlocking quantity threshold; wherein, The threshold prediction model is a model obtained by training the constructed computing model based on the sample set to be trained. The sample set to be trained includes sample target description parameters corresponding to the sample memory access request, and each sample target description parameter is added with a training label. The training label is used to characterize the thread unlocking quantity threshold of the access thread corresponding to the sample memory access request.

3. The method according to claim 1, The request description parameter includes at least one of the following: an average request length and a read-write type ratio of the memory access request; The device description parameters include: the number of memory devices deployed in the electronic device.

4. The method according to claim 1, wherein scheduling the access thread that initiates the memory access request according to the thread unlock quantity threshold comprises: Determine the number of access threads in an unlocked state as an initial number, and compare the initial number with the thread unlocking number threshold; When the initial number is greater than or equal to the thread unlocking number threshold, setting the access thread to a locked state; When the initial number is smaller than the thread unlocking number threshold, the access thread is set to an unlocked state.

5. The method according to claim 4, further comprising: When the access thread is in a locked state by default and the memory access request processing is completed, the access thread is restored to the locked state. 6 . The method according to claim 1 , wherein the memory in the electronic device where the target memory is located includes a volatile memory and a non-volatile memory, and the target memory is the non-volatile memory.

7. A scheduling method, comprising: In response to a memory access request initiated for a target memory, obtaining corresponding target description parameters; wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located; A thread unlocking number threshold for the target memory is determined based on the target description parameters, and the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

8. The method according to claim 7, wherein determining the thread unlocking quantity threshold of the target memory according to the target description parameter comprises: Inputting the target description parameter into a predefined threshold calculation formula, and determining a calculation result output by the threshold calculation formula as the thread unlocking quantity threshold; or, The target description parameters are input into a threshold prediction model generated by pre-training, and the calculation result output by the threshold prediction model is determined as the thread unlock quantity threshold; wherein, the threshold prediction model is a model obtained by training a constructed calculation model based on a sample set to be trained, and the sample set to be trained includes sample target description parameters corresponding to sample memory access requests, and each sample target description parameter is added with a training label, and the training label is used to characterize the thread unlock quantity threshold of the access thread corresponding to the sample memory access request.

9. The method according to claim 7, The request description parameter includes at least one of the following: an average request length and a read-write type ratio of the memory access request; The device description parameters include: the number of memory devices deployed in the electronic device.

10. The method according to claim 7, wherein the memory in the electronic device where the target memory is located includes a volatile memory and a non-volatile memory, and the target memory is the non-volatile memory.

11. A scheduling device, comprising: A request acquisition unit, configured to acquire a memory access request initiated for a target memory; a threshold acquisition unit, configured to acquire a thread unlocking quantity threshold for the target memory; wherein the thread unlocking quantity threshold is data determined based on target description parameters corresponding to the memory access request, the target description parameters including request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by the electronic device where the target memory is located; The thread scheduling unit is used to schedule the access thread that initiates the memory access request according to the thread unlocking number threshold so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

12. A scheduling device, comprising: a parameter acquisition unit, configured to acquire corresponding target description parameters in response to a memory access request initiated for a target memory; wherein the target description parameters include request description parameters for characterizing processing resources required for the memory access request and device description parameters for characterizing processing resources provided by an electronic device where the target memory is located; A threshold determination unit is used to determine a thread unlocking number threshold for the target memory based on the target description parameters, and the thread unlocking number threshold is used to schedule the access thread that initiates the memory access request so that the number of access threads in the unlocked state does not exceed the thread unlocking number threshold.

13. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 10 when executing the program.

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