A BMS slave address allocation method, a BMS master module and a BMS slave module

Abstract

The application belongs to the technical field of battery management system, and particularly relates to a BMS slave control address allocation method, a BMS master control module and a BMS slave control module. The BMS slave control address allocation method comprises the following steps: the BMS master control module simultaneously sends a periodic signal and a self-defined address signal to a first BMS slave control module; when the first BMS slave control module receives the first level mutation moment of the periodic signal, the first BMS slave control module continuously reads the values of the self-defined address signal at the set number of periodic signal level mutation moments as the addresses of the corresponding slave control modules; after the address of the first BMS slave control module is set, the self-defined address signal is processed to obtain the address of the next slave control module, and the periodic signal and the processed self-defined address signal are sent to the next BMS slave control module. Through the above address allocation method, the error of the sent and received signals when only the address signal is sent is avoided, and the accuracy of setting the slave control address is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of battery management system, and particularly relates to a BMS slave control address allocation method, a BMS master control module and a BMS slave control module. BACKGROUND

[0002] From the topology architecture of a battery management system (BMS), the BMS is divided into centralized and distributed types according to different project requirements. The centralized BMS collects all battery cells with one BMS hardware, which is suitable for the scene with few battery cells, and is commonly used in the scene with low capacity, low total voltage and small battery system volume. With the continuous development of the power battery system of a passenger vehicle towards high capacity, high total voltage and large volume, the distributed BMS architecture is mainly used in plug-in hybrid and pure electric vehicles. The distributed BMS architecture is composed of one master control and multiple slave controls to manage the battery pack. In order to realize the communication between the master and slave modules, different addresses need to be set for each slave control.

[0003] There are three common address setting schemes for the slave control module of the BMS: 1. The slave control module fixes the address through burning software, and each module matches the address before being installed on a vehicle; 2. The address is fixed in the hardware design stage, and the software automatically identifies the address through the peripheral circuit of a single-chip microcomputer, and each address corresponds to one kind of hardware design; and 3. The slave control module allocates the address through CAN network and specific information. The defect of the first scheme is that the module address is fixed, and the module is not universal. The defect of the second scheme is that there are many hardware versions, and the management and control are complex. The defect of the third scheme is that the allocated address cannot be corresponded to the actual physical connection through address allocation. Therefore, the three address setting schemes for the slave control module of the BMS have the problems of complex circuit, low universality, complicated work engineering and low efficiency.

[0004] The prior art sets a scheme of automatically allocating the address of the BMS slave module to solve the above problems, for example, the Chinese invention patent with publication number CN112193125A discloses a method and system for automatically allocating the address of a BMS, a PWM output line and a PWM input line are added between adjacent BMS slaves to automatically allocate the address of the BMS from the first BMS slave to the third BMS slave, meanwhile, each BMS slave processes the input first PWM signal to generate a second PWM signal for output, and each BMS slave is written with the slave board number in series to realize the integration of the battery pack system. However, the allocation is inaccurate due to the influence of PWM sending and receiving errors, and the allocated address is allocated based on different proportions of PWM modulation, so the duty cycle resolution is limited, and the number of slave settings is also limited. Based on the above analysis, the prior art still has the problems of inaccurate slave address allocation and low universality. SUMMARY

[0005] The purpose of the present application is to provide a BMS slave address allocation method and a BMS master module and a BMS slave module to solve the problem of inaccurate slave address allocation in the prior art.

[0006] To solve the above technical problems, the present application provides a BMS slave address allocation method, which comprises the following steps:

[0007] 1) When the conditions for allocating the address of the BMS slave are met, the BMS master module simultaneously sends a periodic signal and a custom address signal to the first BMS slave module;

[0008] 2) After the first BMS slave module receives the periodic signal and the custom address signal, the first BMS slave module sets the address; the first BMS slave module sets the address specifically by continuously reading the value of the custom address signal at the moment of the level mutation of the set number of periodic signals as the address of the corresponding slave module;

[0009] 3) After the first BMS slave module sets the address, the first BMS slave module processes the custom address signal to obtain the address of the next slave module, and the first BMS slave module sends the periodic signal and the processed custom address signal to the next BMS slave module.

[0010] The beneficial effects are: by setting the periodic signal and the custom address signal respectively, and obtaining the value of the custom address signal as the address of the slave according to the periodic signal, the influence of the error of the sent and received signals on the setting of the address is avoided when only the address signal is sent, and the accuracy of setting the address of the slave is improved.

[0011] Further, the custom address signal is a PWM signal; the low level of the PWM signal represents an address bit with a value of 0, and the high level of the PWM signal represents an address bit with a value of 1. By setting the custom address signal to be a PWM signal and using the high and low levels of the PWM signal to represent the values of the address bits, the address setting of the slave control address is performed in a digital transmission manner, and is not a process of slave control address allocation based on the duty cycle. Thus, the resolution of the duty cycle is limited, and the use of the duty cycle to allocate the slave control address can only identify accurate data under the condition of meeting the resolution of the duty cycle, thereby causing the address allocation to limit the number of slave controls. However, the address allocation method of the present application uses a digital transmission manner, and thus is not affected by the resolution, and the number of slave controls is not limited, thereby improving the versatility of the address allocation.

[0012] Further, the periodic signal is a square wave signal, and the signal representing an address bit in the PWM signal corresponds to one period of the square wave signal.

[0013] Further, in step 2), if the BMS slave module detects that the first level transition time of the periodic signal is a rising edge transition, then from the first falling edge transition time of the square wave signal, the values of the PWM at the falling edge transition times of a set number of square wave signals are continuously read as the addresses of the corresponding slave modules; if the BMS slave module detects that the first level transition time of the periodic signal is a falling edge transition, then from the first rising edge transition time of the square wave signal, the values of the PWM at the rising edge transition times of a set number of square wave signals are continuously read as the addresses of the corresponding slave modules.

[0014] Further, in step 2), if the address setting fails, the BMS slave module sends the setting failure information to the BMS master module through the CAN message, and the BMS master module stops the address allocation; the address setting failure is that when the address setting error times of the same BMS slave module exceed the set times, the address setting of the BMS slave module fails; the address setting error of the BMS slave module includes that the address set by the BMS slave module is unreasonable. In the address allocation process, the BMS slave module sends the setting failure information to the BMS master module, so that the BMS master module can accurately determine the slave serial number of the address setting failure, and stop the address allocation in time, thereby avoiding the problem that after a BMS slave address setting fails, the address allocation is continued, resulting in low accuracy of the subsequent allocated address, and further reducing the error rate of the entire BMS slave. By setting the error opportunity times of each slave by the master, the address setting error caused by accidental factors is avoided, the success rate of address allocation of each slave is improved, and the success rate of address allocation of the entire slave is improved. The address data has corresponding rules, for example, if the range of the address data is 0000-0111, but the set address is 1000, then the set address is unreasonable.

[0015] Further, before the BMS master module stops the address allocation, the address setting error times of the BMS slave module are judged, and when the address setting error times of the BMS slave module exceed the set times, the BMS master module stops the address allocation; otherwise, the periodic signal and the custom address signal are sent to the BMS slave module again.

[0016] Further, before the periodic signal and the custom address signal are sent to the BMS slave module again, a waiting preset time interval is included. By setting the idle time interval, the data interlacing caused by continuous data transmission is avoided, the data stability is enhanced, the inaccurate data acquisition is avoided, the data transmission is ensured to be unaffected, the data correctness is improved, and the accuracy of address allocation is ensured.

[0017] Further, after the address of the last BMS slave module is set, the set address of the BMS slave module is sent to the BMS master module, and the BMS master module judges whether the received address is correct according to the number of BMS slave modules. If correct, the address setting of all BMS slaves is successful, and a normal working mode is entered. By the final judgment of the master module, it is ensured that when the normal working mode is entered, the address setting of the BMS slave is correct.

[0018] Further, in the step 1), the condition of the BMS slave address allocation includes that the number of the BMS slave is not consistent with the number of the BMS slave stored by the BMS master or the BMS slave address is not unique. By performing the address allocation when the condition is met, the process of address allocation to the system which has completed the address allocation is avoided, thereby reducing the time for the system which has completed the address allocation to enter the normal work, and avoiding the problems of energy waste and time waste caused by the re-allocation error when the address allocation is performed again.

[0019] To solve the above technical problems, the application further provides a BMS master module, which simultaneously sends a periodic signal and a self-defined address signal to a first BMS slave module when the condition of the BMS slave address allocation is met; the periodic signal and the self-defined address signal are used to set the address of the first BMS slave module after being received by the first BMS slave module; the value of the self-defined address signal at the time of the level mutation of a set number of periodic signals is continuously read as the address of the corresponding slave module.

[0020] The BMS master module sends the periodic signal and the self-defined address signal to the BMS slave module, and the BMS master module sets the address according to the two signals, thereby avoiding the influence of the error of the sent and received signals on the address setting when only the address signal is sent, and improving the accuracy of the slave address setting.

[0021] Further, the self-defined signal is a PWM signal; the low level of the PWM signal represents an address bit with a value of 0, and the high level of the PWM signal represents an address bit with a value of 1. By setting the self-defined address signal as the PWM signal and using the high and low levels of the PWM signal to represent the value of the address bit, the address setting of the slave is performed in the digital transmission mode, and the address allocation process is not based on the duty cycle, thereby avoiding the condition that the address allocation is limited by the number of slaves due to the limitation of the resolution of the duty cycle, the accurate data can be recognized only when the condition of the resolution of the duty cycle is met, thereby leading to the limitation of the number of slaves, and the address allocation method of the application adopts the digital transmission mode, and is not affected by the resolution, thereby the number of slaves is not limited, and the universality of the address allocation is improved.

[0022] Further, the periodic signal is a square wave signal, and the time interval occupied by one address bit data in the PWM signal corresponds to one period of the square wave signal.

[0023] Further, if the BMS slave module address setting fails, the BMS slave module sends a setting failure information through a CAN message, and stops address allocation; the address setting failure is that when the same BMS slave module address setting error times exceed the set times, the BMS slave module address setting fails; the BMS slave module address setting error includes that the address set by the BMS slave module is unreasonable. When the address setting fails, the process of stopping address allocation is controlled by the BMS master module, which avoids the problem that after a BMS slave address setting fails, address allocation continues, resulting in low accuracy of the subsequently allocated address, thereby reducing the error rate of the entire BMS slave, and by setting the number of error opportunities for each slave by the master, the situation of address setting error caused by accidental factors is avoided, the success rate of address allocation of each slave is improved, and the success rate of address allocation of the entire slave is improved, and the address data has corresponding rules, for example, if the address data range is 0000-0111, but if the set address is 1000, the set address is unreasonable.

[0024] Further, before the BMS master module stops address allocation, the number of BMS slave module address setting errors is judged, and when the number of BMS slave module address setting errors exceeds the set number, address allocation is stopped; otherwise, the periodic signal and the custom address signal are sent to the BMS slave module again.

[0025] Further, before the BMS slave module is sent the periodic signal and the custom address signal again, it includes waiting for a preset time interval. By setting the idle time interval, the data interlacing caused by continuous data transmission is avoided, the data stability is enhanced, the inaccurate data acquisition situation is avoided, the data transmission is ensured to be unaffected, the data correctness is improved, and the address allocation accuracy is ensured.

[0026] Further, after the address of the last BMS slave module is set, the address set by the BMS slave module is received, and whether the received address data is correct is judged according to the number of BMS slave modules, if correct, the address setting of all BMS slave modules is successful, and a normal working mode is entered. By the final judgment of the master module, it is ensured that when the normal working mode is entered, the BMS slave address setting is correct.

[0027] Furthermore, the conditions for BMS slave address allocation include: the number of BMS slaves is inconsistent with the number of BMS slaves stored in the BMS master control, or the BMS slave addresses are not unique. By only initiating the address allocation process when these conditions are met, the BMS master control module avoids re-allocating addresses to the system after address allocation is complete. This reduces the time required for the system to enter normal operation after address allocation is completed, and avoids energy waste and time waste caused by incorrect re-allocation.

[0028] To address the aforementioned technical problems, this invention also provides a BMS slave control module, which sets the address based on received periodic signals and a custom address signal; specifically, setting the address includes continuously reading the values ​​of the custom address signal at the moments of a predetermined number of periodic signal level changes as the address of the corresponding slave control module;

[0029] After the address is set, the custom address signal is processed to obtain the address of the next slave module; and the periodic signal and the processed custom address signal are sent to the next BMS slave module.

[0030] Its beneficial effect is that by receiving periodic signals and custom address signals through the BMS slave module, and obtaining the value of the custom address signal based on the periodic signal as the slave address, it avoids the error between sending and receiving signals affecting the address setting when only the address signal is sent, thus improving the accuracy of setting the slave address.

[0031] Furthermore, the custom signal is a PWM signal; a low level of the PWM signal represents an address bit with a value of 0, and a high level of the PWM signal represents an address bit with a value of 1. By setting the custom address signal to PWM and using the high and low levels of the PWM signal to represent the address bit values, the slave address is set using digital transmission, rather than based on duty cycle. This avoids the situation where duty cycle resolution limits the number of slave addresses that can be allocated, which would otherwise require meeting certain duty cycle resolution requirements to accurately identify data. The address allocation method of this invention uses digital transmission and is therefore not affected by resolution, thus the number of slave addresses is also unlimited, improving the versatility of address allocation.

[0032] Furthermore, the periodic signal is a square wave signal, and the signal representing one address bit in the PWM signal corresponds to one cycle of the square wave signal.

[0033] Furthermore, if the first level change of the periodic signal is detected as a rising edge change, then the PWM values ​​at the falling edge change times of the square wave signal are continuously read from the first falling edge change time of the square wave signal as the address of the corresponding slave control module; if the first level change of the periodic signal is detected as a falling edge change, then the PWM values ​​at the rising edge change times of the square wave signal are continuously read from the first rising edge change time of the square wave signal as the address of the corresponding slave control module.

[0034] Furthermore, if address setting fails, a setting failure message is sent to the BMS master control module via a CAN message, and the BMS master control module stops address allocation. Address setting failure is defined as when the number of incorrect address settings for the same BMS slave control module exceeds a set limit; this includes situations where the address set by the BMS slave control module is unreasonable. By controlling the cessation of address allocation through the BMS master control module when address setting fails, the problem of continuing address allocation after one slave control module's address setting fails, leading to low accuracy in subsequent address allocations, is avoided. This reduces the overall error rate of the BMS slave control modules. By allowing each slave control module a set number of error attempts, the system avoids address setting errors due to accidental factors, improving the success rate of address allocation for each slave control module and thus the overall success rate of slave control address allocation. Address data follows certain rules; for example, if the address data range is 0000 to 0111, but the set address is 1000, then the set address is unreasonable.

[0035] Furthermore, the address set by the last BMS slave module is sent to the BMS master module. The master module then determines the correctness of the received address data based on the number of slave modules. If correct, all slave addresses are successfully set, and the system enters normal operating mode. The last slave module also sends a periodic signal along with its corresponding custom address signal to the master module. This allows the master module to verify the accuracy of the address data. In other words, the master module makes the final determination to ensure that the slave addresses are correctly set when entering normal operating mode. Attached Figure Description

[0036] Figure 1 This is a block diagram of the BMS slave address allocation method and the allocation system of the BMS master control module and the BMS slave control module of the present invention.

[0037] Figure 2 This invention relates to a BMS slave control address allocation method and a timing diagram of BMS address allocation data for the BMS master control module and the BMS slave control module.

[0038] Figure 3 is the power-on flowchart of the BMS slave address allocation method, the BMS master module and the BMS slave module of the application;

[0039] Figure 4 is the address allocation flowchart of the BMS slave address allocation method, the BMS master module and the BMS slave module of the application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the application more clear and obvious, the application is further described in detail in combination with the drawings and examples.

[0041] BMS slave address allocation method embodiment:

[0042] The distributed BMS architecture is composed of one master and multiple slaves to manage the battery pack. In order to realize the communication between the master and slave modules, different addresses need to be set for each slave. In order to realize the automatic allocation of the BMS slave module address and improve the allocation accuracy, the following process of the BMS slave address allocation method is designed:

[0043] As Figure 1 , there is one BMS master module and n BMS slave modules, wherein the connection mode of the BMS master and the BMS slave is that the DO1 port of the BMS master is connected with the DI1 port of the BMS slave 1, which is used to transmit the PWM1 signal (i.e. periodic signal) sent by the BMS master to the BMS slave 1, the DO2 port of the BMS master is connected with the DI2 port of the BMS slave 1, which is used to transmit the PWM2 signal (i.e. custom address signal) sent by the BMS master to the BMS slave 1; the DO1 port of the BMS slave 1 is connected with the DI1 port of the BMS slave 2, which is used to transmit the PWM1 signal sent by the BMS slave 1 to the BMS slave 2, the DO2 port of the BMS slave 1 is connected with the DI2 port of the BMS slave 2, which is used to transmit the PWM2 signal sent by the BMS slave 1 to the BMS slave 1; the connection mode of the BMS slave 1 and the BMS slave 2 is the same, and the BMS slave 1, the BMS slave 2, the BMS slave 3, …, the BMS slave n are connected in turn; the DO1 port of the BMS slave n is connected with the DI1 port of the BMS master, which is used to transmit the PWM1 signal sent by the BMS slave n to the BMS master, the DO2 port of the BMS slave n is connected with the DI2 port of the BMS master, which is used to transmit the PWM2 signal sent by the BMS slave n to the BMS master; in addition, each BMS slave is connected with the BMS master through the CAN bus, which is used for the BMS slave to send the CAN message to the BMS master. Based on the above line connection, the BMS slave address allocation method comprises the following steps:

[0044] 1, asFigure 3 After power on, the BMS master calls all BMS slave data through CAN message, and the BMS master determines whether the BMS slave address is unique through the slave address, and determines whether the number of BMS slaves is consistent with the system set number of slaves. When the slave address is unique and the number is consistent, it enters the normal working mode. Otherwise, the BMS master sends PWM1 and PWM2 signals to BMS slave 1, and enters the slave address allocation mode. Through the process of whether the slave address allocation is needed after power on (i.e. whether the condition of BMS slave address allocation is met), and only when it is needed, the BMS slave address allocation is performed. By performing the address allocation when the condition is met, the process of re-addressing the system that has completed address allocation is avoided, thereby reducing the time for the system that has completed address allocation to enter the normal working mode, and avoiding the problems of energy waste caused by re-allocation after allocation, and time waste caused by re-allocation error. As other embodiments, the slave address re-allocation can be directly performed after power on.

[0045] 2. When the condition of BMS slave address allocation is met, enter the address allocation process, such as Figure 4 , the BMS master DO1 outputs 1kHz PWM1 signal, DO2 outputs 8-bit data PWM2 signal representing the set address (the transmission data bit is not limited to 8 bits, which can be extended according to the actual application), and the time interval of PWM2 sending 1-bit address bit data corresponds to one cycle of PWM1 signal (i.e. if PWM2 address sending is binary sending, the time used by PWM2 to send 1-bit information is 0.001s), for example, as shown in Figure 2 , PWM1 and PWM2 are in high level state when not set, when starting to set the address, PWM1 first changes from high level to low level, and at the same time PWM2 starts to output address data (as other embodiments, PWM1 and PWM2 can also be in low level state when not set, when starting to set the address, PWM1 first changes from low level to high level, and at the same time PWM2 starts to output address data; again, PWM1 is in low level state (or high level state), PWM2 is in high level state (or low level state) when not set, when starting to set the address, PWM1 first changes from low level to high level (or first changes from high level to low level), and at the same time PWM2 starts to output address data).

[0046] 3、BMS slave 1 receives PWM1 signal and PWM2 signal from DI1 port and DI2 port respectively, and performs address acquisition. The address acquisition method is as follows: BMS slave 1 starts to acquire address data after receiving the first level mutation moment of PWM1 signal. If the first level mutation is rising edge mutation, the value of PWM2 at the first falling edge mutation moment of PWM1 is read, and the values of PWM2 at a set number of falling edge mutation moments of PWM1 are continuously read as the address of BMS slave 1. If the first level mutation is falling edge mutation, the value of PWM2 at the first rising edge mutation moment of PWM1 is read, and the values of PWM2 at a set number of rising edge mutation moments of PWM1 are continuously read as the address of BMS slave 1. For example, if the signal received by BMS slave 1 is as shown in the figure, the data of PWM2 at the rising edge mutation moment of PWM1 is read, and 8 data are read in turn as the address of BMS slave 1. That is, the values of 8 continuous PWM2 read by BMS slave 1 at the rising edge mutation moment of PWM1 are 0101000, and the address of BMS slave 1 is set as 0x50, that is, 80 in decimal. Figure 2

[0047] 4、After address acquisition, address setting is performed, and whether the address is set successfully is judged. If BMS slave 1 is set successfully, BMS slave 1 continues to process the signal and transmits the new signal to BMS slave 2. The process of processing the signal is as follows: the acquired address data is increased by a set value x to form new address data, and the new address data is set as the corresponding PWM1 signal and PWM2 signal. In this embodiment, in order to consider the generality of address allocation, x is set as 1, that is, the minimum increase value. Therefore, the address quantity set by this method is more, and the generality is stronger. As other real-time methods, x can also be set as any value that can meet the number of BMS slaves.

[0048] ​If the address setting of BMS slave controller 1 fails, it outputs a failure message to the BMS master controller via CAN. The BMS master controller then stops address allocation and enters an error state. During address allocation, the slave controller module sends the failure message to the master controller module, allowing the master controller module to accurately determine the slave controller number where the address setting failed and promptly stop address allocation. This avoids the problem of continuing address allocation after one slave controller has failed, leading to low accuracy in subsequent address allocations, and thus reduces the overall error rate of the BMS slave controllers. This embodiment also considers the randomness of address setting errors. Specifically, BMS slave controller 1's address setting fails only after the number of incorrect address settings exceeds a set limit. After an incorrect address setting, it checks if the number of incorrect settings exceeds the set limit (e.g., 3 times). If the number of errors does not exceed 3, the BMS master controller continues to send PWM1 and PWM2 signals to BMS slave controller 1, and BMS slave controller 1 continues the address acquisition process. When the number of address setting failures for BMS slave controller 1 reaches 4, the address setting for BMS slave controller 1 fails, and the BMS master controller stops address allocation and enters an error state. By giving each slave controller 3 chances to fail (i.e., giving each slave controller 4 chances to allocate an address), the success rate of address allocation for each slave controller is improved, thereby improving the overall success rate of slave controller address allocation. To ensure the success rate of BMS slave address allocation, this embodiment also allows the BMS slave to continue sending PWM1 and PWM2 signals after a set idle time interval T (e.g., at least one cycle of PWM1, i.e., 0.001ms, while also considering the utilization rate of the communication channel, the idle time period is set to any value from one cycle of PWM1 to a set number (i.e., 8) cycles) when transmitting signals to the same BMS slave multiple times.

[0049] 5. BMS slave controller 2 receives PWM1 and PWM2 signals from ports DI1 and DI2, and performs the same address acquisition as BMS slave controller 1 (if the signals received by BMS slave controller 1 are...). Figure 2 As shown in the signal, after BMS slave controller 2 successfully obtains the address (address is 0x51, which is 81 in decimal), it checks whether the address is set successfully. If the address is set successfully, it processes the signal and sends the processed signal to BMS slave controller 3. Each BMS slave controller sequentially receives the signal, obtains the address, checks whether the address is set successfully, processes the signal if the address is set successfully, and sends the processed signal, until BMS slave controller n processes the signal and transmits the processed PWM1 and PWM2 to the BMS master controller.

[0050] To ensure the correctness of the BMS slave address setting, the BMS master controller performs a final check. After receiving the PWM2 and PWM1 signals, the BMS master controller module acquires the address and checks whether the difference between the acquired address and the sent address is equal to n×x. If they are equal, the BMS slave address setting is successful; otherwise, the BMS slave address setting fails. For example, if the PWM1 and PWM2 signals sent by the BMS master controller are... Figure 2 As shown, with the set value x = 1 and the number of BMS slave controllers n = 5, the addresses of BMS slave controller 1 to BMS slave controller 5 are 80, 81, 82, 83, and 84 respectively. The data received by the BMS master controller is 85. 85 - 80 = 1 × 5. Therefore, when the data received by the BMS master controller is 85, the BMS slave controller address allocation is completed, the master controller and slave controllers stop outputting addresses, and the system enters normal working mode.

[0051] By using PWM1 and PWM2 signals for BMS slave address allocation, the error in sending and receiving signals when only sending address signals is avoided, thus improving the accuracy of address setting. Setting addresses via I / O port data transmission enhances address allocation stability. Slave addresses are automatically allocated according to wiring sequence (physical location) without manual intervention. Furthermore, by increasing the set value of the address signal PWM2 without changing its duty cycle, the limitation imposed by duty cycle resolution on the number of slaves allocated is avoided, thereby improving the versatility of address allocation. In other words, through this BMS slave address allocation method, automatic slave address allocation is achieved until the nth BMS slave module completes the setting process (i.e., the first BMS slave module completes address allocation), with high accuracy and strong versatility.

[0052] Example of BMS main control module:

[0053] like Figure 1As shown, the BMS slave module of the application comprises a DO1 port, a DO2 port, a DI1 port and a DI2 port, the DO1 port of the BMS master is connected with the DI1 port of the BMS slave 1, for transmitting the PWM1 signal sent by the BMS master to the BMS slave 1, the DO2 port of the BMS master is connected with the DI2 port of the BMS slave 1, for transmitting the PWM2 signal sent by the BMS master to the BMS slave 1; the DO1 port of the BMS slave n is connected with the DI1 port of the BMS master, for transmitting the PWM1 signal sent by the BMS slave n to the BMS master, the DO2 port of the BMS slave n is connected with the DI2 port of the BMS master, for transmitting the PWM2 signal sent by the BMS slave n to the BMS master; the BMS slave module further comprises a signal processor, in addition, each BMS slave is connected with the BMS master through a CAN bus, for the BMS slave to send CAN messages to the BMS master, the BMS master module based on the above setting is used to realize the process of the BMS slave address allocation method, the process of the BMS slave address allocation method has been introduced in the BMS slave address allocation method embodiment clearly enough, and details are not repeated here.

[0054] BMS slave module embodiment:

[0055] As Figure 1As shown, the BMS slave module of the application comprises a DO1 port, a DO2 port, a DI1 port and a DI2 port, and the DO1 port of the BMS master is connected with the DI1 port of the BMS slave 1, for transmitting the PWM1 signal sent by the BMS master to the BMS slave 1, the DO2 port of the BMS master is connected with the DI2 port of the BMS slave 1, for transmitting the PWM2 signal sent by the BMS master to the BMS slave 1; the DO1 port of the BMS slave 1 is connected with the DI1 port of the BMS slave 2, for transmitting the PWM1 signal sent by the BMS slave 1 to the BMS slave 2, the DO2 port of the BMS slave 1 is connected with the DI2 port of the BMS slave 2, for transmitting the PWM2 signal sent by the BMS slave 1 to the BMS slave 1; the BMS slave 1, the BMS slave 2, the BMS slave 3, …, the BMS slave n are connected in turn in the same way as the connection of the BMS slave 1 and the BMS slave 2; the DO1 port of the BMS slave n is connected with the DI1 port of the BMS master, for transmitting the PWM1 signal sent by the BMS slave n to the BMS master, the DO2 port of the BMS slave n is connected with the DI2 port of the BMS master, for transmitting the PWM2 signal sent by the BMS slave n to the BMS master; in addition, each BMS slave is connected with the BMS master through a CAN bus, for transmitting the CAN message by the BMS slave to the BMS master, the BMS slave module further comprises a signal processor, the BMS slave address allocation method based on the above-mentioned BMS slave module is used to realize the process of the BMS slave address allocation method, the process of the BMS slave address allocation method has been introduced in the BMS slave address allocation method embodiment, which is clear enough, and will not be repeated here.

[0056] The above is only the preferred embodiment of the application, and is not used to limit the application, the patent protection scope of the application is subject to the claims, any equivalent structural changes made by using the content of the specification and drawings of the application should be included in the protection scope of the application.

Claims

1. A BMS slave address allocation method, characterized by, The method comprises the following steps: 1) when the condition of BMS slave address allocation is met, the BMS master module simultaneously sends a periodic signal and a custom address signal to the first BMS slave module; the custom address signal and the periodic signal are both PWM signals; 2) after the first BMS slave module receives the periodic signal and the custom address signal, the first BMS slave module sets the address; the first BMS slave module sets the address specifically as follows: if the first level mutation time of the periodic signal is a rising edge mutation, the first BMS slave module reads the values of the custom address signal at the set number of falling edge mutation times of the periodic signal from the first falling edge mutation time of the periodic signal as the address of the corresponding slave module; if the first level mutation time of the periodic signal is a falling edge mutation, the first BMS slave module reads the values of the custom address signal at the set number of rising edge mutation times of the periodic signal from the first rising edge mutation time of the periodic signal as the address of the corresponding slave module; 3) after the first BMS slave module sets the address, the first BMS slave module processes the custom address signal to obtain the address of the next slave module, and the first BMS slave module sends the periodic signal and the processed custom address signal to the next BMS slave module.

2. The BMS slave address allocation method of claim 1, wherein, The low level of the custom address signal represents an address bit with a value of 0, and the high level represents an address bit with a value of 1.

3. The BMS slave address allocation method of claim 2, wherein, The signal representing an address bit in the custom address signal corresponds to one period of the periodic signal.

4. The BMS slave address allocation method of claim 1, wherein, In step 2), if the address setting fails, the BMS slave module sends a setting failure message to the BMS master module through a CAN message, and the BMS master module stops address allocation; the address setting failure is that when the number of address setting errors of the same BMS slave module exceeds the set number of times, the address setting of the BMS slave module fails; the address setting error of the BMS slave module includes that the address set by the BMS slave module is unreasonable.

5. The BMS slave address allocation method of claim 4, wherein, Before the BMS master module stops address allocation, the number of address setting errors of the BMS slave module is determined; when the number of address setting errors of the BMS slave module exceeds the set number of times, the BMS master module stops address allocation; otherwise, the periodic signal and the custom address signal are sent to the BMS slave module again.

6. The BMS slave address allocation method of claim 5, wherein, Before the periodic signal and the custom address signal are sent to the BMS slave module again, a preset time interval is waited.

7. The BMS slave address allocation method of claim 1, wherein, After the address of the last BMS slave module is set, the address is sent to the BMS master module; the BMS master module determines whether the received address is correct according to the number of BMS slave modules; if the address is correct, the address setting of all BMS slave modules is successful, and the BMS slave modules enter a normal working mode.

8. The BMS slave address allocation method of claim 1, wherein, In step 1), the conditions of BMS slave address allocation include that the number of BMS slaves is inconsistent with the number of BMS slaves stored by the BMS master or the BMS slave addresses are not unique.

9. A BMS master module, characterized in that, When the condition of the BMS slave address allocation is met, a periodic signal and a custom address signal are simultaneously sent to the first BMS slave module; the custom address signal and the periodic signal are both PWM signals, and the periodic signal and the custom address signal are used to set the address of the BMS slave module after being received by the first BMS slave module; if the first level mutation time of the periodic signal detected by the BMS slave module is a rising edge mutation, the values of the custom address signal at the set number of falling edge mutation times of the periodic signal are continuously read as the address of the corresponding slave module from the first falling edge mutation time of the periodic signal; if the first level mutation time of the periodic signal detected by the BMS slave module is a falling edge mutation, the values of the custom address signal at the set number of rising edge mutation times of the periodic signal are continuously read as the address of the corresponding slave module from the first rising edge mutation time of the periodic signal.

10. The BMS master module of claim 9, wherein, The low level of the custom address signal represents an address bit with a value of 0, and the high level represents an address bit with a value of 1.

11. The BMS master module of claim 10, wherein, The signal representing an address bit in the custom address signal corresponds to one period of the periodic signal.

12. The BMS master module of claim 9, wherein, If the address setting of the BMS slave module fails, the BMS slave module sends a setting failure message through a CAN message, and the address allocation is stopped; the address setting failure is that when the number of address setting errors of the same BMS slave module exceeds the set number of times, the address setting of this BMS slave module fails; the address setting error of the BMS slave module includes an unreasonable address set by the BMS slave module.

13. The BMS host module of claim 12, wherein, Before the BMS master module stops address allocation, the number of address setting errors of the BMS slave module is determined, and when the number of address setting errors of the BMS slave module exceeds the set number of times, the address allocation is stopped; otherwise, the periodic signal and the custom address signal are sent to the BMS slave module again.

14. The BMS host module of claim 13, wherein, Before the periodic signal and the custom address signal are sent to the BMS slave module again, a preset time interval is waited.

15. The BMS host module of claim 9, wherein, After the address of the last BMS slave module is set, the set address of the BMS slave module is received, and whether the received address is correct is determined according to the number of BMS slave modules; if correct, the address setting of all BMS slave modules is successful, and a normal working mode is entered.

16. The BMS host module of claim 9, wherein, The condition of the BMS slave address allocation includes that the number of BMS slaves is inconsistent with the number of BMS slaves stored by the BMS master or the BMS slave address is not unique.

17. A BMS slave module, comprising: According to the received periodic signal and the self-defined address signal, address setting is performed; the self-defined address signal and the periodic signal are PWM signals, and the address setting specifically includes: if the BMS slave module detects that the first level mutation time of the periodic signal is a rising edge mutation, then from the first falling edge mutation time of the periodic signal, a set number of values of the self-defined address signal at falling edge mutation times of the periodic signal are continuously read as addresses of the corresponding slave modules; if the BMS slave module detects that the first level mutation time of the periodic signal is a falling edge mutation, then from the first rising edge mutation time of the periodic signal, a set number of values of the self-defined address signal at rising edge mutation times of the periodic signal are continuously read as addresses of the corresponding slave modules; After the address setting is completed, the self-defined address signal is processed to obtain an address of a next slave module, and the periodic signal and the processed self-defined address signal are sent to the next BMS slave module.

18. The BMS slave module of claim 17, wherein, The low level of the self-defined address signal represents an address bit with a value of 0, and the high level represents an address bit with a value of 1.

19. The BMS slave module of claim 18, wherein, The signal representing an address bit in the self-defined address signal corresponds to one period of the periodic signal.

20. The BMS slave module of claim 17, wherein, If the address setting fails, a setting failure message is sent to the BMS master module through a CAN message, and the BMS master module stops address allocation; the address setting failure is that when the number of address setting errors of the same BMS slave module exceeds a set number of times, the address setting of the BMS slave module fails; the address setting error of the BMS slave module includes that the address set by the BMS slave module is unreasonable.

21. The BMS slave module of claim 17, wherein, The address set by the last BMS slave module is sent to the BMS master module, so that the BMS master module judges whether the received address is correct according to the number of BMS slave modules, and if correct, the address setting of all BMS slave modules is successful, and a normal working mode is entered.

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