Switch mode (TM) encoding using circuit-boundary array memory

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform a toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from the location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data and send the decoded data to the host device.

Description

BACKGROUND TECHNICAL FIELD

[0002] Embodiments of the present disclosure generally relate to data storage devices such as solid state drives (SSDs), and migrating data within data storage devices.

[0003] Description of the Related Art

[0004] In data storage devices, data is transferred between a host device having a host controller and a memory device having a memory controller and a memory array. That is, the memory device has its own controller (typically a CMOS chip) coupled to the memory array. Further, the memory device can have a circuit boundary array (CbA) architecture. In a CbA architecture, in addition to the memory controller chip, a separate control die (referred to as a CbA die) is bonded to each of the dies that make up the memory array, such as NAND dies, so that each NAND die has its own dedicated control logic for operating data stored and retrieved from that particular NAND die.

[0005] Toggle mode (TM) data rate and power consumption characteristics of the memory controller interacting with the memory array impact the performance of the data storage device. TM data rate is associated with input / output (IO) performance and throughput of the transfers between the memory controller and the memory array. However, high TM rates are challenging due to signal strength and power consumption. Thus, limits on power consumption and thermal capacity impact data storage device performance.

[0006] In communication systems, data can be shaped in order to reduce the number of toggles between 0 and 1 (and vice versa). For example, double data rate (DDR) data bus inversion can utilize data shaping. However, data shaping is not used in SSDs between the memory controller and the memory die because the data is scrambled and randomized before programming to the memory die. A long string of 0s and Is is not a preferred data pattern for program performance and data retention.

[0007] Accordingly, there is a need in the art for improved data shaping for use with data transferred between a memory controller and a memory die. SUMMARY

[0008] The present disclosure generally relates to migrating data within a data storage device having a controller and a memory device. The controller is configured to receive a command to write data to the memory device, perform toggle mode encoding on the data, and send the toggle mode encoded data to the memory device. The memory device is configured to receive the toggle mode encoded data, decode the toggle mode encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, perform toggle mode encoding on the data, and send the toggle mode encoded data to the controller. The controller is configured to receive the toggle mode encoded data, decode the toggle mode encoded data, and send the decoded data to a host device.

[0009] In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command to write data to the memory device, perform toggle mode (TM) encoding on the write data, and send the TM encoded write data to the memory device. The memory device is configured to receive the TM encoded write data, decode the TM encoded write data, and write the decoded data to a location within the memory device.

[0010] In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The memory device is configured to receive a read command to read data from a location within the memory device, read the data, perform toggle mode (TM) encoding on the data, and transmit the TM encoded read data. The controller is configured to receive the transmitted TM encoded read data, decode the TM encoded read data, and send the decoded data to a host device.

[0011] In another embodiment, a data storage device includes a memory device including means for TM decoding received data and means for TM encoding read data. The data storage device includes a controller means coupled to the memory device. The controller means is configured to decode TM encoded data received from the memory device and TM encode write data to be sent to the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0012] Therefore, by reference to the embodiments, a detailed understanding of the above-mentioned features of the present disclosure, a more particular description of the application, briefly summarized above, can be had by reference to the embodiments which are illustrated in the drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments.

[0013] Figure 1 is a schematic block diagram illustrating a data storage device in communication with a host device, in accordance with certain embodiments.

[0014] Figure 2 is a schematic diagram of a circuit boundary array (CbA) architecture, in accordance with certain embodiments.

[0015] Figure 3A is a functional diagram illustrating a CbA architecture, in accordance with certain embodiments.

[0016] Figure 3B is a schematic diagram of a circuit array on array (CAA) architecture, in accordance with certain embodiments.

[0017] Figure 3C is a schematic diagram of a CAA architecture, in accordance with certain embodiments.

[0018] Figure 4 is a schematic block diagram illustrating a data storage device coupled to a host system, in accordance with certain embodiments, wherein the data storage device includes a circuit boundary array architecture.

[0019] Figure 5 is a schematic diagram of a memory controller and a CbA memory device each including TM encoder logic and TM decoder logic, in accordance with certain embodiments.

[0020] Figure 6 is a flow diagram illustrating a method of switch mode encoding, in accordance with certain embodiments.

[0021] Figure 7 is a flow diagram illustrating a method of transferring data between a memory controller and a respective memory die, in accordance with certain embodiments.

[0022] To facilitate an understanding of this description, like reference characters are used to identify like elements throughout the description and the drawings. It should be appreciated that, in some embodiments, elements disclosed in one embodiment can be advantageously used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0023] In the following, reference is made to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Furthermore, although the embodiments of the disclosure can achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not a limitation of the disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims, unless specifically recited therein. Likewise, reference to "the disclosure" should not be interpreted as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims, unless specifically recited in such a claim.

[0024] The present disclosure generally relates to data storage devices having a controller and a memory device. In one embodiment, the memory device includes one or more memory dies and one or more control circuits, where each of the one or more memory dies is bonded with a respective one of the one or more control circuits. The controller is configured to receive a command to write data to the memory device, perform toggle mode encoding on the data, and send the toggle mode encoded data to the memory device. The memory device is configured to receive the toggle mode encoded data, decode the toggle mode encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from the location within the memory device, read the data, toggle mode encode the data, and send the toggle mode encoded data to the controller. The controller is configured to receive the toggle mode encoded data, decode the toggle mode encoded data, and send the decoded data to a host device.

[0025] Figure 1 A schematic block diagram of a storage system 100 is shown in accordance with certain embodiments, in which a host device 104 is in communication with a data storage device 106. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, which can operate as a storage array. For example, the storage system 100 can include multiple data storage devices 106 configured to collectively function as a redundant array of inexpensive / independent disks (RAID) for the host device 104.

[0026] The host device 104 can store data to and / or retrieve data from one or more storage devices, such as the data storage device 106. As Figure 1As shown, the host device 104 can communicate with the data storage device 106 via the interface 114. The host device 104 can comprise any of a variety of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called “smart” phone, a so-called “smart” tablet, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, or other device capable of sending or receiving data from the data storage device.

[0027] The data storage device 106 includes a controller 108, NVM 110, a power source 111, volatile memory 112, an interface 114, and a write buffer 116. In some examples, for the sake of clarity, the data storage device 106 can include additional components not shown in FIG. 1. For example, the data storage device 106 can include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and which includes conductive traces to electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 can conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, peripheral component interconnect (PCI), PCI extended (PCI-X), PCI Express (PCIe) (e.g., PCIe xl, x4, x8, x16, PCIe Mini card, MiniPCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device 104. Figure 1

[0028] ​The interface 114 can include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 can operate according to any suitable protocol. For example, the interface 114 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to the controller 108, providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 can also allow the data storage device 106 to receive power from the host device 104. For example, as shown in FIG. 1, the power supply 111 can receive power from the host device 104 via the interface 114. Figure 1

[0029] The NVM 110 can include a plurality of storage devices or storage units. The NVM 110 can be configured to store and / or retrieve data. For example, a storage unit of the NVM 110 can receive data and receive a message from the controller 108 instructing the storage unit to store the data. Similarly, the storage unit can receive a message from the controller 108 instructing the storage unit to retrieve data. In some examples, each of the storage units can be referred to as a die. In some examples, the NVM 110 can include a plurality of dies (e.g., a plurality of storage units). In some examples, each storage unit can be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0030] In some examples, each storage unit can include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0031] ​The NVM 110 can include a plurality of flash memory devices or storage units. The NVM flash memory devices can include NAND or NOR based flash memory devices and can store data based on charge contained in a floating gate of a transistor for each flash memory unit. In NVM flash memory devices, the flash memory devices can be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of blocks, which can be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device can include a plurality of NVM cells. Rows of NVM cells can be electrically connected using word lines to define a page of the plurality of pages. Respective cells in each page of the plurality of pages can be electrically connected to a respective bit line. Further, the NVM flash memory devices can be 2D or 3D devices and can be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 can write data to and read data from the NVM flash memory devices at a page level and erase data from the NVM flash memory devices at a block level.

[0032] The power supply 111 can provide power to one or more components of the data storage device 106. When operating in a standard mode, the power supply 111 can use power provided by an external device, such as the host device 104, to power the one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power the one or more components. In some examples, the power supply 111 can include one or more power storage components configured to power the one or more components when operating in an off mode, such as in the event that power is stopped being received from the external device. In this way, the power supply 111 can act as an on-board backup power supply. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by the one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0033] The volatile memory 112 can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As Figure 1As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.).

[0034] Controller 108 can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to the NVM. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data to NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operational characteristic of storage system 100 and store the at least one operational characteristic to NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores data associated with the write command in an internal memory or write buffer 116 prior to sending the data to NVM 110.

[0035] Figure 2 A schematic diagram of a circuit boundary array (CbA) architecture 200 is shown, in accordance with one embodiment. CbA architecture 200 includes one or more complementary metal-oxide-semiconductor (CMOS) chips 206 coupled to one or more memory arrays 208 via one or more connection units. In one embodiment, each memory array 208 includes a memory die.

[0036] Figure 3A is a functional diagram of a memory device 300 having a CbA architecture. As shown in FIG. 3, CbA architecture 300 includes a substrate 302, a first memory die 304a mounted on substrate 302, a second memory die 304b stacked on first memory die 304a, a third memory die 304c stacked on second memory die 304b, and a fourth memory die 304d stacked on third memory die 304c. Each of memory dies 304a-304d is coupled to a CMOS chip. Further, each of memory dies 304a-304d is electrically coupled to the substrate, either directly or through a respective one of the CMOS chips. It should be appreciated that the number of arrays and CMOS chips shown are not intended to be limiting, but rather provide an example of a possible embodiment.

[0037] For example, a first memory die 304a is coupled to a first CMOS chip 306a, where the first CMOS chip 306a is also coupled to the substrate 302. A second memory die 304b is coupled to a second CMOS chip 306b, where the second CMOS chip 306b is also coupled to the first CMOS chip 306a. A third memory die 304c is coupled to a third CMOS chip 306c, where the third CMOS chip 306c is also coupled to the second CMOS chip 306b. A fourth memory die 304d is coupled to a fourth CMOS chip 306d, where the fourth CMOS chip 306d is also coupled to the third CMOS chip 306c.

[0038] Bonding wires 308 can be used to couple the first CMOS chip 306a to the substrate, the second CMOS chip 306b to the first CMOS chip 306a, the third CMOS chip 306c to the second CMOS chip 306b, and the third CMOS chip 306c to the fourth CMOS chip 306d. The bonding wires 308 can include one or more bonding wires.

[0039] Figure 3B A schematic diagram of a memory device 330 having a circuit above array (CAA) architecture is shown, in accordance with certain embodiments. Reference numerals of the memory device 300 can be used in the description of similar components of the CAA architecture memory device 330. In the CAA architecture, CMOS chips are bonded over memory dies. It should be understood that the number of memory dies and CMOS chips shown are not intended to be limiting, but rather provide an example of a possible implementation.

[0040] For example, a first memory die 304a is disposed on the substrate 302 and a first CMOS chip 306a is bonded to the first array 304a. As used herein, bonded means that an active surface of the CMOS chip 306a is in direct electrical and mechanical contact with an active surface of the first memory die 304a. A second memory die 304b is partially disposed on an inactive surface of the first CMOS chip 306a and a second CMOS chip 306b is bonded to the second memory die 304b. A third memory die 304c is partially disposed on an inactive surface of the second CMOS chip 306b and a third CMOS chip 306c is bonded to the third memory die 304c. A fourth memory die 304d is partially disposed on an inactive surface of the third CMOS chip 306c and a fourth CMOS chip 306d is bonded to the fourth memory die 304d.

[0041] In the illustrated embodiment, the first CMOS chip 306a includes a first through-silicon via (TSV) 332a. The second CMOS chip 306b includes a second TSV 332b. The third CMOS chip 306c includes a third TSV 332c. The fourth CMOS chip 306d includes a fourth TSV 332d. Each of the TSVs 332a-332d is coupled to a bonding wire 308. Each of the memory dies 304a-304d includes a corresponding TSV 312a-312d. The first memory die 304a includes a first TSV 312a, the second memory die 304b includes a second TSV 312b, the third memory die 304c includes a third TSV 312c, and the fourth memory die 304d includes a fourth TSV 312d. In some embodiments, one or more bonding pads 310 are provided between each memory die / CMOS chip pair.

[0042] Figure 3C A schematic diagram of a memory device 360 ​​having a circuit under array (CUA) architecture according to certain embodiments is shown. Reference numerals of the CbA architecture memory device 300 and the CAA architecture memory device 330 may be used to describe similar components of the CUA architecture memory device 360. In the CUA architecture, CMOS chips 306a-306d are bonded below the memory dies 304a-304d. As Figure 3A and Figure 3B , it should be understood that the number of memory dies and CMOS chips shown is not intended to be limiting, but rather to provide examples of possible implementations.

[0043] exist Figure 3C In the embodiment shown, pairs of memory die 304a-304d and CMOS chips 306a-306d are stacked vertically, with no continuous pair partially overhanging the substrate 302. Additionally, the memory die and CMOS chip pairs are connected via TSVs rather than wire bonds (e.g., Figure 3A ) or through a combination of bond wires and TSVs ( Figure 3B ) are electrically connected. In addition, a first CMOS chip 306a is mounted on the substrate 302 and connected to the substrate with a plurality of solder balls 364. As will be apparent, according to the CbA architecture, whether CAA or CUA, each memory die is coupled to the CMOS die and therefore has its own control logic circuitry so that data to be stored in the memory die can be manipulated by its associated CMOS logic circuitry.

[0044] Figure 4is a schematic block diagram illustrating the storage system 400, in which the host device 402 is coupled to the data storage device 408 through a flash bus 406. The data storage device 408 includes a controller 410 coupled to a memory array 420 through a memory bus 416. The memory array 420 in the illustrated embodiment is a CUA architecture similar to that shown in Figure 3C

[0045] The host device and the data storage device 408 communicate through the flash bus 406. The flash bus 406 can be used to transfer data and commands between the data storage device 408 and the host device 402. The host device 402 includes a data storage device interface 404, which can be configured to manage data into and out of the data storage device 408.

[0046] The controller 410 of the data storage device 408 includes a toggle mode (TM) encoder logic 412 and a TM decoder logic 414. The TM encoder logic 412 can be configured to encode data to be stored in locations of the memory array 420, and the TM decoder logic 414 can be configured to decode encoded data retrieved from the memory array 420. Data is transferred between the controller 410 and the memory array 420 through the memory bus 416.

[0047] Each of the CMOS chips 426a-426c includes its own TM logic circuit 434. The TM logic 434 can be configured to encode data to be transferred from the memory array 420 to the controller 410, and to decode data transferred from the controller 410 to the memory array 420.

[0048] ​During a write process, the TM encoder logic 412 encodes data that is subsequently transferred to the memory array 420 via the memory bus 416, and the TM logic 434 at the associated CMOS chip decodes the encoded data. Similarly, when read data is transferred from the memory array 420 to the controller 410 via the memory bus 416, the data is encoded by the TM logic 434 after being read from the array's memory dies, and then decoded by the TM decoder logic 414 of the controller 410. In one embodiment, the encoding performed by the TM encoder logic 412 and by the TM logic 434 may use the same encoding mapping, making the encoding symmetrical. In another embodiment, the encoding performed by the TM encoder logic 412 and by the TM logic 434 may use different encoding mappings, making the encoding asymmetrical. Similarly, in one embodiment, the decoding performed by the TM decoder logic 414 and by the TM logic 434 may use the same decoding mapping, making the decoding symmetrical. In another embodiment, the decoding performed by the TM decoder logic 414 and by the TM logic 434 may use different decoding mappings, making the decoding asymmetrical.

[0049] TM encoder logic 412 and TM logic 434 can be configured to encode data in such a manner as to reduce the number of toggles from 1 to 0 (and vice versa) applied to the data during data shaping. By reducing or even minimizing the number of bit toggles, terminal power can be reduced. Dedicated TM logic 434 is configured to decode the encoded data and program the decoded data into the appropriate location in the memory array. By including TM logic 434, silicon area can be saved, resulting in less silicon area being used, and the processing power of data storage device 408 with CbA can be more efficiently utilized or more power-efficient.

[0050] The encoding and decoding by the TM encoder logic 412, TM decoder logic 414, and TM logic 434 can be dynamically calibrated according to an analysis of the interface transmission lines and one or more parasitic elements of the interface transmission lines. The one or more parasitic elements include, but are not limited to, TM frequency, the amount of NAND dies in the memory array stack, the type of PCB used, packaging parameters, and the resulting delay and impedance. The dynamic calibration can be based on a short term history, such as a previous transaction amount “x” or time amount “y”. By dynamically calibrating the encoding and decoding logic, the amount of toggling between wires, such as from 1 to 0 (and vice versa), can be reduced, the amount of polarity toggling between adjacent wires can be reduced, which can reduce the amount of power loss due to crosstalk, and the amount of DC power used on the target termination can be reduced by changing the data polarity distribution. For example, in the case of a low voltage swing termination logic (LVSTL) interface, which has endpoints coupled to ground, more number of 0s can be preferred, or in the case of a pseudo open drain (POD) interface, which has endpoints coupled to Vcc, more number of 1s are transmitted. Further, encoding the data transmitted between the controller 410 and the memory array 420 can improve data integrity as the data is encoded and protected.

[0051] The interface encoding, such as the TM encoder logic 412 and TM logic 434, can include additional redundancy logic. The additional redundancy logic can include the use of control data signals such as data bus inversion (DBI), encoding control signals during data transmission, additional data cycles, and additional data signals outside of the 8-bit NAND data bus. Other redundancy logic is contemplated to be applicable to the described embodiments.

[0052] Figure 5 A schematic diagram of a memory controller 502 coupled to a memory device of a memory die 510 through a memory bus 508 is shown, in accordance with certain embodiments, where each of the controller 502 and the memory die 510 includes TM encoder logic 504, 522 and TM decoder logic 506, 514. The controller 502 includes TM encoder logic 504 and TM decoder logic 506. The memory die 510 includes a control circuit chip 512, which can be a Figures 3A to 3C and Figure 4The controller 502 is a CMOS chip for the CbA architecture 300, 330, 360, 420. The control circuit chip 512 includes a TM decoder logic component 514, a TM encoder logic component 522, and a decoded data section 516. The decoded data section 516 includes a plurality of data registers 518a-518n and a plurality of parity data registers 520a-520n, wherein each parity data register is associated with one of the plurality of data registers 518a-518n. Encoded data is transferred between the controller 502 and the memory die 510 via the memory bus 508.

[0053] Figure 6 is a flow chart illustrating a method 600 for switching mode encoding according to certain embodiments. The method 600 may be used by a TM logic component, such as the TM encoder logic component 412, 504, 522, the TM decoder logic component 414, 506, 514, or Figure 4 and Figure 5 TM logic unit 434. At block 602, a data storage device is provided that includes at least one memory die and at least one control circuit chip coupled to one memory die. For example, the data storage device may be Figure 4 The data storage device 408, wherein at least one memory die and at least one control circuit chip may be Figure 4 The memory array 420 or Figure 5 Memory tube core 510 / control circuit chip 512.

[0054] At block 604, a TM encoder logic component and a TM decoder logic component are provided that are configured to encode and decode user data, respectively, to reduce and preferably minimize switching between 0s and 1s (and vice versa) on a memory bus between the controller and at least one memory die. At block 606, the controller's TM encoder encodes the data and transmits the encoded data with a low switching frequency from the controller to the at least one memory die via the memory bus. The controller may be Figure 5 The controller 502 of FIG. At block 606 , the controller may execute a write command received from the host device or write data back to the memory device as part of a data management operation. At block 608 , the TM decoder logic component of at least one control circuit chip bonded to the memory die decodes the received encoded data, and the decoded data is programmed into the target location of the memory die.

[0055] At block 610, when a read command is received or a data management operation such as garbage collection occurs, data is sensed from the relevant location of the memory die and encoded by the TM encoder logic of the at least one control circuit chip bonded to the memory die. The encoding is done prior to transmission of the data to the controller via the memory bus. At block 612, the encoded data is decoded by the TM decoder logic of the controller.

[0056] Figure 7 is a flowchart illustrating a method 700 of transmitting data between a controller 502 of a memory controller (as opposed to a host controller) such as Figure 5 is a flowchart illustrating a method 700 of transmitting data between a controller 502 of a memory controller (as opposed to a host controller) such as Figure 5 is a flowchart illustrating a method 700 of transmitting data between a controller 502 of a memory controller (as opposed to a host controller) such as

[0057] The method 700 applies in reverse as well. For example, at block 704, rather than the TM encoder logic of the controller encoding the data, the TM encoder logic of the circuit chip encodes the relevant data using a second encoding method. At block 706, the relevant data is sent back to the controller, where the TM decoder logic of the controller decodes the data at block 710 using a second decoding method. In one embodiment, the first encoding method and the second encoding method are substantially the same. In another embodiment, the first encoding method and the second encoding method are substantially different. In one embodiment, the first decoding method and the second decoding method are substantially the same. In another embodiment, the first decoding method and the second decoding method are substantially different.

[0058] By implementing the array boundary circuit architecture with TM encoding (encoding and decoding) logic, power consumption of the data storage device during device operation can be reduced, and the bit error rate (BER) can be reduced due to a reduction in communication errors. Further, the CbA architecture with TM encoding logic can improve transmission signal integrity with high TM frequencies.

[0059] In one embodiment, a data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command to write data to the memory device, perform toggle mode (TM) encoding on the write data, and send the TM encoded write data to the memory device. The memory device is configured to receive the TM encoded write data, decode the TM encoded write data, and write the decoded data to a location within the memory device.

[0060] The memory device includes a memory die and a control circuit chip. The control circuit chip and the memory die are both configured in a CbA architecture. The control circuit chip includes logic configured to perform TM decoding on data. The controller is further configured to receive TM encoded data from the memory device and decode the TM encoded data. The memory device is further configured to TM encode data read from the memory die and send the TM encoded data to the controller. The TM encoding performed at the controller and the TM encoding performed at the memory device can be symmetrical or asymmetrical. The data storage device also includes a bus between the memory device and the controller for passing TM encoded read data and write data therebetween.

[0061] In another embodiment, a data storage device includes a memory device. The memory device is configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and transmit the TM encoded data. The data storage device includes a memory controller coupled to the memory device. The memory controller is configured to receive the transmitted TM encoded read data, decode the TM encoded read data, and send the decoded data to a host device.

[0062] The memory device includes a control chip that includes logic to perform TM encoding. The control chip additionally includes logic to perform TM decoding. The controller includes logic to perform TM decoding and logic to perform TM encoding. The TM encoding performed by the controller can be different than the TM encoding performed by the memory device. The memory device is configured to receive TM encoded data, decode the TM encoded data, and write the decoded data to a location in the memory device. The controller is configured to receive a write request for data, TM encode the write data, and send the TM encoded write data to the memory device. The data sent from the controller to the memory device and the data received at the controller from the memory device is TM encoded.

[0063] In another embodiment, a data storage device includes a memory device including means for TM decoding received data and means for TM encoding read data. The data storage device includes a controller device coupled to the memory device. The controller device is configured to decode TM encoded data received from the memory device and TM encode write data to be sent to the memory device.

[0064] The memory device includes a memory die having a control circuit die bonded thereto. The control circuit die is configured to read decoded data from the memory die and write the decoded data to the memory die.

[0065] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the claims that follow.

Claims

1. A data storage device, comprising: Memory devices; and a controller coupled to the memory device, wherein the controller is configured to: receiving a command to write data to the memory device; Perform switching mode encoding, i.e. TM encoding, on the written data; as well as sending the TM-encoded write data to the memory device; Wherein, the memory device is configured as: receiving the TM-encoded write data; decoding the TM-encoded write data; and The decoded data is written to a location within the memory device.

2. The data storage device of claim 1, wherein the memory device comprises a memory die and a control circuit chip.

3. The data storage device of claim 2, wherein the control circuitry is chip-bonded to the memory die. 4 . The data storage device according to claim 2 , wherein the control circuit chip includes a logic component configured to perform TM decoding on the write data.

5. The data storage device of claim 1 , wherein the controller is further configured to: receiving TM-encoded read data from the memory device; and The TM-encoded read data is decoded.

6. The data storage device of claim 5, wherein the memory device is further configured to: TM encoding the data read from the memory device; and The TM-encoded read data is sent to the controller. 7 . The data storage device of claim 6 , wherein the TM encoding performed at the controller and the TM encoding performed at the memory device are asymmetric.

8. The data storage device of claim 6, wherein the TM encoding performed at the controller and the TM encoding performed at the memory device are symmetric.

9. The data storage device of claim 1, further comprising a bus located between the memory device and the controller for communicating the TM-encoded read data and the TM-encoded write data therebetween.

10. A data storage device, comprising: A memory device, wherein the memory device is configured to: receiving a read command to read data from a location within the memory device; reading the data; Perform switching mode encoding on the read data, i.e. TM encoding; as well as Transmitting TM-encoded read data; and a controller coupled to the memory device, wherein the controller is configured to: receiving the transmitted TM-encoded read data; decoding the TM-encoded read data; and The decoded data is sent to the host device.

11. The data storage device of claim 10, wherein the memory device comprises a control chip containing logic components for performing the TM encoding.

12. The data storage device of claim 11, wherein the control chip further comprises logic components for performing TM decoding.

13. The data storage device of claim 10, wherein the controller comprises logic for performing the TM decoding and logic for performing TM encoding.

14. The data storage device of claim 13, wherein the TM encoding performed by the controller is different from the TM encoding performed by the memory device.

15. The data storage device of claim 10, wherein the memory device is configured to receive TM-encoded data, decode the TM-encoded data, and write the decoded data to a location in the memory device. 16 . The data storage device of claim 10 , wherein the controller is configured to receive a write request for data, TM-encode the write data, and send the TM-encoded write data to the memory device.

17. The data storage device of claim 10, wherein data sent from the controller to the memory device and data received at the controller from the memory device are TM encoded.

18. A data storage device, comprising: A memory device, the memory device comprising: means for performing switching mode decoding (TM decoding) on ​​received data; and means for TM encoding read data; and A controller device is coupled to the memory device, wherein the controller device is configured to decode TM-encoded data received from the memory device and to TM-encode write data to be sent to the memory device.

19. The data storage device of claim 18, wherein the memory device comprises a memory die having a control circuit die bonded thereto.

20. The data storage device of claim 19, wherein the control circuit die is configured to read decoded data from the memory die and write decoded data to the memory die.

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