A chip design method based on delivering comprehensive information flow

Abstract

The present application discloses a chip design method based on the transmission of integrated information flow, which relates to the field of chip design technology. After the device group is identified based on the RTL-level description file in the logic synthesis stage, the method not only obtains the logic subnet table of each device group and other logic subnet tables of other circuit structures, but also obtains the physical scene netlist of each device group and transmits it to the binning stage; in the binning stage, the binning results of each device group can be directly obtained according to the box structure and the connection relationship between each other expressed by the physical scene netlist of the device group, without the need to participate in the search binning of the binning algorithm, and because the physical scene netlist is generated based on the functional information and architectural information of the device group, the binning stage can directly obtain the optimal binning result that meets the requirements of the functional information and architectural information of the device group, thereby improving the binning efficiency and quality, thereby improving the efficiency and quality of chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip design method based on the transmission of integrated information flow. Background Art

[0002] Semiconductor technology and processes have evolved over decades, from the initial discrete semiconductor transistors to today's very large-scale integrated circuits. Along with this development, integrated circuit design technology has also evolved from computer-aided design tools to today's complete integrated circuit design automation process (Electronic Design Automation). The invention and application of integrated circuit technology in the 1990s, in particular, made it possible to automate the entire integrated circuit design process, from the description of design ideas to the final physical implementation.

[0003] The design processes of commonly used FPGA chips and ASIC chips are similar. For example, the process of developing FPGA chips using EDA (Electronic Design Automation) development software and programming tools is shown in the following example. Figure 1 As shown in the design flow chart, the EDA development software development process mainly includes the user design input stage, logic synthesis stage, packaging stage, layout stage, routing stage, and design completion stage. The design completion stage mainly includes operations such as timing analysis and bitstream generation. Among them, the logic synthesis stage is used to convert the input user design (RTL-level description file) into a logic netlist (or device netlist). The logic synthesis stage mainly includes four processes: reading, translation, optimization, and mapping. The first step is to read the RTL-level description file. The second step is to convert the RTL-level description file into a general circuit to obtain a general netlist (independent of the specific process). The third step is to optimize the circuit structure of the general circuit according to the design goals. The fourth step is to map the optimized circuit structure to the target process library corresponding to the FPGA chip. The appropriate prototype device in the target process library is selected to implement the optimized circuit structure, thus obtaining a logic netlist suitable for the FPGA chip.

[0004] With the rapid development of semiconductor technology, chip design capacity has also continued to expand accordingly. How to quickly and accurately convert user designs into digital systems and successfully install them on the chip, and improve the processing efficiency and optimization level of ultra-large-capacity FPGA / ASIC designs, has posed a major challenge to the chip's supporting design software. The patent application number 202110545652.3, entitled "A Chip Design Method Based on Intelligent Analysis," reads the RTL-level description file and identifies related or specific description statements to create device groups and add them to the target process library corresponding to the FPGA chip. This approach, from the prototype device level to a higher level of abstraction and promotion, can, to a certain extent, improve the processing power and efficiency of ultra-large-capacity chip designs.

[0005] However, whether it is the conventional chip design method or the chip design method of the modified target process library corresponding to the FPGA chip cited above, as the chip scale increases, the number, type and connection relationship of the prototype devices contained in the logic netlist generated in the logic synthesis stage are huge and complex. After the logic netlist is passed to the binning stage, the binning stage needs to use the binning algorithm to perform a global search and binning of these prototype devices with connection relationships. The difficulty of binning is often greater, and the final binning result may not be ideal. Therefore, the processing efficiency of the chip design process is still not ideal. Summary of the Invention

[0006] In response to the above problems and technical requirements, the inventors have proposed a chip design method based on the transmission of integrated information flow. The technical solution of the present invention is as follows:

[0007] A chip design method based on transmitting integrated information flow, the method comprising:

[0008] Obtaining an RTL-level description file, parsing description statements in the RTL-level description file and identifying and obtaining a plurality of device groups to add to a mapping library containing a plurality of prototype devices;

[0009] Based on the mapping library, logic synthesis is performed on the RTL-level description file to obtain logical subnet tables and physical scenario netlists for several device groups, as well as other logical subnet tables for other circuit structures other than the device groups; wherein each logical subnet table is expressed using prototype devices with connection relationships as basic units; the physical scenario netlist of each device group is expressed using box structures with connection relationships as basic units, and the prototype devices in the logical subnet table of each device group are assigned to the corresponding box structures based on the functional information and architectural information of the device group determined in the logic synthesis stage;

[0010] In the binning stage, the binning results of each device group are directly obtained according to the physical scenario netlist of each device group. According to other logical subnet tables, the prototype devices contained in other logical subnet tables are searched and binned using the binning algorithm to obtain the binning results.

[0011] Placement and routing are performed based on the global binning results, and chip design for the chip to be designed is completed.

[0012] Its further technical solution is that, when determining the box structure to which each prototype device in the device group belongs based on the functional information and architecture information of the device group during the logic synthesis processing stage, the prototype devices contained in the circuit structure in the device group used to realize the predetermined logical function and / or having a predetermined circuit architecture are assigned to the box structure according to the corresponding preset optimal packing method.

[0013] Its further technical solution is that the method further comprises:

[0014] In the logic synthesis processing stage, the layout scenario netlist of each device group is obtained by logic synthesis processing of the RTL level description file. Each layout scenario netlist is expressed as a box structure with layout constraints as a basic unit, and the box structure in the physical scenario netlist of each device group determines the layout constraints based on the functional information and architectural information of the device group determined in the logic synthesis stage.

[0015] When performing layout based on the global binning result, the layout of the global binning result is completed based on the layout constraints of the bin structure indicated by the layout scenario netlist of each device group.

[0016] Its further technical solution is that, when determining the layout constraints of the box structure in the device group based on the functional information and architectural information of the device group during the logic synthesis processing stage, the layout constraints between multiple box structures with functional correlation and / or architectural correlation are determined to be layout of these multiple box structures according to preset optimal relative positions corresponding to the functional correlation and / or architectural correlation.

[0017] Its further technical solution is that when determining the layout constraints of the box structure in the device group based on the functional information and architectural information of the device group during the logic synthesis processing stage, it also includes determining the layout constraints between all box structures in the same device group to compactly layout all box structures in the same device group within the same local area.

[0018] Its further technical solution is that the layout constraints of the box structures in each device group include the relative layout positions of each box structure in a virtual layout area of ​​corresponding size of the device group, each device group corresponds to a different virtual layout area, and the size of the virtual layout area corresponding to each device group corresponds to the total number of box structures included and the preset optimal relative positions between multiple box structures with functional associations and / or architectural associations.

[0019] A further technical solution is to determine the relative layout position of each box structure in the device group within the virtual layout area corresponding to the device group with the purpose of minimizing the layout distance between box structures with direct drive relationships.

[0020] Its further technical solution is that, when performing layout based on global box packing results, global layout is performed with the virtual layout area of ​​the size corresponding to each device group and each box structure obtained by box packing other logical subnet tables as basic units, and each device group directly obtains the relative layout position of each box structure in the corresponding virtual layout area according to the layout constraints of the box structure indicated by the layout scenario netlist of the device group to achieve compact layout. In the obtained layout results, multiple box structures with functional correlation and / or architectural correlation in each device group are directly laid out according to the preset optimal relative positions.

[0021] A further technical solution is that the layout constraints of the box structures in each device group include the layout weights of the box structures. All box structures contained in the same device group have the same layout weight, and box structures contained in different device groups have different layout weights.

[0022] Its further technical solution is that, when performing layout based on the global packing results, each box structure in the obtained packing results is used as a basic unit for global layout, and according to the layout constraints of the box structure indicated by the layout scenario netlist of each device group, the box structures with the same layout weights are compactly laid out in the same local area, and multiple box structures with functional correlation and / or architectural correlation in each device group are directly laid out according to the preset optimal relative positions.

[0023] The beneficial technical effects of the present invention are:

[0024] The present application discloses a chip design method based on the transmission of comprehensive information flow. After identifying the device group in the logic synthesis stage, the method not only generates a logical subnet table for each device group, but also constructs a netlist scenario to generate a physical scenario netlist and transmits it to the subsequent packing stage through the information flow. In this way, the physical scenario netlist of the device group can be used to directly obtain the packing result of the device group in the packing stage, without the need to participate in the search and packing of the packing algorithm, thereby improving the efficiency of the packing.

[0025] Moreover, since the physical scenario netlist is generated based on the functional information and architectural information of the device group, the packing stage can directly obtain the optimal packing result that meets the requirements of the functional information and architectural information of the device group. This makes up for the problem of not being able to obtain ideal packing results in conventional design methods because the packing stage can only obtain the connection relationship of the prototype devices recorded in the logic netlist, but cannot obtain the functional information and architectural information of the device group, thereby improving the quality of packing.

[0026] Furthermore, in the logic synthesis stage, a layout scenario is constructed to generate a layout scenario netlist and pass it to the subsequent boxing stage and layout stage through the information flow, so that the layout stage can quickly obtain the layout result by using the layout constraints recorded in the layout scenario netlist of the device group. Moreover, since the layout scenario netlist is generated based on the functional information and architectural information of the device group, the layout stage can directly obtain the optimal layout result that meets the requirements of the functional information and architectural information of the device group, which makes up for the problem of not being able to obtain the ideal layout result in the conventional design method because the layout stage can only obtain the connection relationship of the prototype device recorded in the logic netlist but cannot obtain the functional information and architectural information of the device group, thereby improving the layout efficiency and layout quality.

[0027] When creating a netlist scenario for each device group, the relative independence between device groups can be exploited to maximize the use of parallel processing computing resources to further improve the efficiency of ultra-large capacity FPGA design. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a design flow diagram of the existing chip design method.

[0029] Figure 2 This is a design flow diagram of a chip design method based on the transmission of integrated information flow provided by an embodiment of the present application.

[0030] Figure 3 The diagram is a schematic diagram of a logic subnet table of a device group generated during the logic synthesis stage in an example.

[0031] Figure 4 yes Figure 3 Schematic diagram of the physical scenario netlist generated during the logic synthesis phase for the device group in the example shown.

[0032] Figure 5 yes Figure 3 Schematic diagram of the placement scenario netlist generated during the logic synthesis phase for the device group in the example shown. DETAILED DESCRIPTION

[0033] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0034] This application discloses a chip design method based on the transmission of comprehensive information flow, please refer to Figure 2 As shown in the flowchart, the method includes the following steps in each link of the chip design process:

[0035] 1. User Design Input Phase

[0036] Obtain an RTL-level description file of the chip to be designed. The RTL-level description file in this application is written in any one of Verilog, SystemVerilog, and VHDL. The chip to be designed is an FPGA chip or an ASIC chip.

[0037] 2. Logic Synthesis Stage

[0038] 1. Parse RTL level description file

[0039] The description statements in the RTL description file are parsed and identified to obtain several device groups, which are then added to a mapping library containing several prototype devices. Each device group is a circuit structure represented by at least two description statements with predetermined associations and / or at least one description statement that meets predetermined statement characteristics.

[0040] A device group determined in the present application includes a circuit structure in the form of a general circuit model and / or a local netlist. The circuit structure in the form of a general circuit model represents a macro unit with a preset architecture. Optionally, the macro unit with a preset architecture includes at least one of an N-bit arithmetic operation unit, an N-bit multiplexer, an N-bit comparator, a storage unit, a digital signal processing unit, a control circuit unit, and a microprocessor unit. It should be noted that the N bits mentioned above are only general and do not mean that the signal bit widths of each device need to be equal. Among them, the arithmetic operation unit includes at least one of an adder, a subtractor, a multiplier, a divider, and an accumulator, the storage unit includes at least one of BRAM, ROM, and RAM, the digital signal processing unit includes at least one of a digital filter and a DSP, the control circuit unit includes an FSM (Finite State Machine), and the microprocessor unit includes at least one of a CPU, a GPU, and an MPU. These macro units with preset architectures are all commonly used high-level modules, which can be recorded as primitive cells. The architecture of each macro unit is pre-configured and set, so it can exist directly in the form of a general circuit model. In addition to the circuit structure that forms the macro unit, the device group also includes some random combinational logics. These random combinational logics do not form any macro units of a preset architecture, and therefore exist in the form of a netlist. Therefore, the circuit structure that exists in the form of a partial netlist represents the circuit structure other than all macro units with a preset architecture.

[0041] Therefore, the device group in this application can include both macro units and random combination logic, and is a more advanced module with higher circuit complexity than conventional macro units. This application does not elaborate on the specific method for identifying the device group, and it can be identified based on the identification method provided in the applicant's previous application for a chip design method based on intelligent analysis.

[0042] After all device groups are identified, all device groups are added to a mapping library containing several prototype devices. The mapping library is a library that needs to be used when performing process mapping on the existing chip to be designed. It contains several prototype devices, and common prototype devices such as LUTs and registers, etc. On the basis of the conventional mapping library, this application adds the device groups identified above. The device group is a module with certain functions and is relatively independent. It cannot be determined and pre-prepared in the mapping library before the start of the design process, but can only be identified and added to the mapping library by parsing the RTL-level description file in this step.

[0043] 2. Create a general netlist

[0044] Perform module binding and refinement, and convert the RTL-level description file into a general circuit that is independent of the specific process to obtain a general netlist. The specific operation of this step is similar to the conventional method, but since this application identifies the device group in the RTL-level description file, the general netlist obtained in this step includes the general subnet table of each device group, as well as the general subnet table of other circuit structures other than the device group.

[0045] 3. Logic optimization

[0046] Based on the design goal optimization, the general circuit represented by the general netlist is logically optimized to obtain an optimized general netlist. Since the general netlist includes the general subnetlists of each device group and the general subnetlists of other circuit structures, during the logic optimization step, the general subnetlists of each device group and the general subnetlists of other circuit structures are optimized. The corresponding optimized general netlist also includes the optimized general subnetlists of each device group and the optimized general subnetlists of other circuit structures.

[0047] 4. Perform device mapping based on the mapping library and establish multiple netlist scenarios, including establishing the following netlist scenarios and obtaining corresponding netlists:

[0048] (1) Netlist View: obtain the logical subnet tables of several device groups and other logical subnet tables of other circuit structures other than the device groups. Each logical subnet table is expressed using prototype devices with connection relationships as basic units.

[0049] The optimized general netlist is mapped to the mapping library of the chip to be designed to obtain a logical subnetlist. Specifically, the optimized general subnetlist for each device group is mapped to the corresponding device group in the mapping library to obtain a logical subnetlist for each device group. Each device group's logical subnetlist is internally bound to several prototype devices in the mapping library contained in that device group. The optimized general subnetlists for other circuit structures are bound to the prototype devices in the mapping library to obtain other logical subnetlists for other circuit structures.

[0050] During the mapping process, for circuit structures within the device group that use common circuit models, the macrocells formed by these circuit structures are commonly used. Based on the on-chip resources, we can directly construct the physical implementation for the optimal mapping. For example, for N-to-one multiplexers and N-bit adders, the optimal implementation architecture can be directly determined during mapping, resulting in a logical subnet table with optimal mapping results.

[0051] Therefore, no matter whether it is the logical subnet table of the device group or other logical subnet tables of other circuit structures, each logical subnet table obtained in this logical subnet table scenario is expressed with the prototype device as the basic unit, that is, it is bound to the prototype device in the mapping library, and each logical subnet table reflects the connection relationship between the prototype devices contained in its corresponding circuit structure.

[0052] (2) Packing View: The physical scene netlists of several device groups are obtained. The physical scene netlist of each device group is expressed as a slice structure with a connection relationship. All prototype devices bound to the device group are assigned to the corresponding slice structure, and each prototype device belongs to one and only one slice structure. When the prototype devices contained in two slice structures have a connection relationship, the two slice structures also have a connection relationship.

[0053] The prototype devices in each device group's logical subnetlist are assigned to corresponding bin structures based on the device group's functional and architectural information determined during the logic synthesis phase. This information determines how all prototype devices are assigned to different bin structures. Since the device group's functional and architectural information is known during the logic synthesis phase, this information can be used to naturally construct binning scenarios and generate the physical scenario netlist for each device group.

[0054] The functional information of a device group indicates the logical function implemented by the device group as a whole and / or the logical function implemented by a portion of the circuit structures within the device group. In one embodiment, for several typical and commonly used circuit structures for implementing predetermined logical functions, a preset optimal packaging method for the circuit structures having the predetermined logical functions can be directly constructed based on on-chip resources. For example, the circuit structures used to implement the predetermined logical functions can be directly assigned to the same or multiple bin structures, or other preset optimal packaging methods can be used. Common predetermined logical functions include multi-way selection and arithmetic functions.

[0055] The architecture information of the device group indicates the circuit architecture of the circuit structure within the device group, including the circuit architecture of each general circuit model included in the device group, the circuit architecture other than the general circuit model, the circuit architecture between each part of the circuit architecture, including the connection trigger relationship, etc. In one embodiment, for several typical and commonly used predetermined circuit architectures, a preset optimal packing method of the circuit structure of the predetermined circuit architecture can be directly constructed based on the resources on the chip: for example, the circuit structure with the predetermined circuit architecture is directly assigned to the same or multiple box structures in a preset optimal packing method. A common example of a predetermined circuit architecture is a circuit architecture of a multi-way selection circuit formed by multiple N-to-one selectors.

[0056] In one embodiment, when determining the box structure to which each prototype device in the device group belongs based on the functional information and architectural information of the device group, the prototype devices contained in the circuit structure for realizing a predetermined logical function and / or having a predetermined circuit architecture in the device group are assigned to the box structure according to the corresponding preset optimal packing method. The preset optimal packing method corresponding to the predetermined logical function and the preset optimal packing method corresponding to the predetermined circuit architecture can be preset. The device group may contain multiple groups of circuit structures for realizing different predetermined logical functions and / or having different predetermined circuit architectures, and they are respectively assigned according to the corresponding preset optimal packing method. In addition to the circuit structure for realizing a predetermined logical function and / or having a predetermined circuit architecture, the device group may also include other circuit structures. At this time, the remaining circuit structures can be assigned to other box structures according to the circuit scale, so as to finally obtain the physical scenario netlist of the device group.

[0057] For example, in one instance, the functional information of a device group indicates that the device group implements a 256-to-1 multiplexing function, and the architectural information of the device group indicates that the device group contains 17 16-to-1 selectors. Each 16-to-1 selector has an optimal packaging method: the prototype devices bound to the same 16-to-1 selector are assigned to the same box structure. Based on the architectural information of the device group, the prototype devices bound to the circuit structure of each 16-to-1 selector are assigned to the same box structure, thereby directly assigning the device group to the 17 box structures, and the connection relationship between the 17 box structures can be naturally determined. In addition to the 17 16-to-1 selectors, there are no other unassigned circuit structures in the device group, so the physical scenario netlist of the device group is finally obtained.

[0058] (3) Placement View: obtain the layout scenario netlists of several device groups. Each layout scenario netlist is expressed as a box structure with layout constraints as the basic unit.

[0059] All box structures in the physical scenario netlist of each device group determine the layout constraints based on the functional information and architectural information of the device group determined in the logic synthesis stage, that is, the layout constraints according to which all box structures in each device group should be laid out are determined by the functional information and architectural information of the device group. The functional information and architectural information of the device group are known in the logic synthesis stage, so according to the above information obtained in the logic synthesis stage, the layout scenario can be naturally constructed to obtain the layout scenario netlist of each device group. It should be noted that the layout constraints recorded in the layout scenario netlist of the device group in this application are generated based on the functional information and architectural information of the device group, and are different from the layout constraints input by the user.

[0060] The layout constraints between the box structures recorded in the layout scenario netlist of the device group include two parts:

[0061] The first part constrains the relative positions of multiple box structures with functional and / or architectural associations within the same device group.

[0062] As described above, the logic synthesis stage can determine the functional information and circuit architecture of the device group, and the circuit structures used to implement different logical functions in the device group will have functional correlations, and / or, there will be architectural correlations between circuit structures with different circuit architectures. Then, after obtaining the physical scenario netlist of the device group and determining the box structure to which the prototype devices of each part of the circuit structure in the device group belong, it can naturally be determined that the box structures to which the circuit structures with functional correlations and / or architectural correlations belong also have functional correlations and / or architectural correlations. That is, in this application, multiple box structures with functional correlations and / or architectural correlations refer to circuit structures constituted by the prototype devices contained in these multiple box structures having functional correlations and / or architectural correlations.

[0063] In one embodiment, for a combination of several typical and commonly used box structures with functional correlation and / or architectural correlation, a preset optimal relative position between these box structures can be directly constructed, and then the layout constraints between the multiple box structures with functional correlation and / or architectural correlation are directly determined to layout these multiple box structures according to the preset optimal relative positions corresponding to the functional correlation and / or architectural correlation.

[0064] For example, in one example, a circuit structure consisting of prototype devices contained within four box structures is used to implement a carry chain function. These four box structures are functionally related. The layout constraints directly added to these four box structures are the preset optimal relative positions corresponding to the carry chain function. The preset optimal relative positions indicate that the four box structures should be laid out vertically from bottom to top in carry order.

[0065] In the second part, regardless of whether the device group contains box structures with functional and / or architectural associations, the layout constraints between the box structures recorded in the layout scenario netlist of the device group also need to constrain the layout position relationship between different device groups.

[0066] Specifically, the layout constraints between all box structures in the same device group are determined to be compactly arranged in the same local area. That is, it is expected that the box structures in the same device group will be arranged together as much as possible, and different device groups will be arranged in different local areas.

[0067] In an embodiment of the second part, it is applicable to a scenario where a layout tool uses a virtual rectangular layout method, that is, each device group is laid out in a virtual layout area.

[0068] In this embodiment, the layout constraints of the box structures in each device group include the relative layout positions of each box structure within a virtual layout area of ​​the corresponding size of the device group, and each device group corresponds to a different virtual layout area. In this embodiment, it is first necessary to determine the size of the virtual layout area corresponding to each device group, specifically based on the total number of box structures and the preset optimal relative positions between multiple box structures with functional associations and / or architectural associations. Generally, the size of the virtual layout area can be determined based on the number of box structures included in the device group. However, since the first part of this application also requires the addition of layout constraints to ensure that the box structures with functional associations and / or architectural associations are laid out according to the preset optimal relative positions, and multiple box structures used to collaboratively implement the carry chain function in the above example will have requirements on the height of the virtual layout area under the constraints of the vertical layout, and in other cases, when the box structures are laid out according to the preset optimal relative positions, there will also be other requirements on the size of the virtual layout area. Therefore, in addition to meeting the requirements for the number of box structures, the size of the virtual layout area also needs to meet the size requirements of the virtual layout area generated by the layout constraints of the first part.

[0069] After determining the size of the virtual layout area required for a component group, the relative layout positions of each box structure within the correspondingly sized virtual layout area for the component group are determined. For multiple box structures with functional and / or architectural dependencies, the relative layout positions of these box structures within the virtual layout area also meet the preset optimal relative positions required of these box structures.

[0070] When determining the relative layout positions of each box structure within the virtual layout area, the relative layout positions of each box structure within the virtual layout area are determined based on the connection relationships between the box structures. If multiple box structures with functional and / or architectural associations exist, the relative layout positions of each box structure within the virtual layout area are determined based on the connection relationships between the box structures, while satisfying layout constraints for pre-set optimal relative positions between these multiple box structures. In one embodiment, the relative layout position of each box structure in a device group within the virtual layout area corresponding to the device group is determined with the goal of minimizing the layout distance between box structures that have a direct drive relationship.

[0071] That is, combining the first part and the second part, in the scenario where the layout tool uses the virtual rectangular layout method, the layout constraints of the box structure recorded in the layout scenario netlist of the device group include the relative layout positions of each box structure in the virtual layout area of ​​the corresponding size of the device group, and the relative layout positions of multiple box structures with functional correlation and / or architectural correlation in the virtual layout area are also the preset optimal relative positions corresponding to the functional correlation and / or architectural correlation.

[0072] In another embodiment of the second part, applicable to scenarios where the layout tool is not convenient to use the virtual rectangle layout method, the layout constraints of the box structures in each device group include the layout weights of each box structure. All box structures in the same device group have the same layout weight, and box structures in different device groups have different layout weights.

[0073] That is, combining the first part and the second part, in a scenario where it is inconvenient for the layout tool to use the virtual rectangular layout method, the layout constraints of the box structure recorded in the layout scenario netlist of the device group include the layout weights of each box structure, and the preset optimal relative positions of multiple box structures that have functional and / or architectural associations.

[0074] According to the above method, a logical subnet list, a physical scenario netlist and a layout scenario netlist can be obtained for each device group respectively, and by utilizing the relative independence between different device groups, in one embodiment, parallel resources are used to construct a netlist scenario for each device group and obtain three types of netlists.

[0075] 3. Packing stage

[0076] As described in the background technology section, in conventional design methods, the logic synthesis stage only generates a global logic netlist (i.e., a logic subnetlist including device groups and other circuit structures) and passes it to the binning stage. In the binning stage, the information that can be obtained based on the global logic netlist is all the prototype devices bound in the logic netlist and the connection relationships of the prototype devices. It is necessary to analyze the connection relationships of the prototype devices in the logic netlist and use binning algorithms such as heuristics to perform a global search and binning of all prototype devices. This is quite difficult and often fails to produce optimal binning results. Furthermore, although conventional methods identify device groups in the logic synthesis stage, the logic netlist passed to the binning stage only contains information such as which prototype devices are bound to each device group and how these prototype devices are connected. The binning stage cannot obtain the functional and architectural information of the device groups as the logic synthesis stage does. Therefore, when searching and binning the prototype devices in the device groups and other circuit structures, it is often difficult to obtain the optimal binning result that meets the functional and architectural information requirements of the device groups.

[0077] However, this application is different from conventional methods. In the logic synthesis stage, after obtaining the device group and other circuit structure logical subnet tables through the logic netlist scene (Netlist View), obtaining the device group physical scene netlist through the packing scene (Packing View), and obtaining the device group layout scene netlist through the layout scene (Placement View), all these netlists are passed to the packing stage, so that the packing stage can use the information flow passed from the synthesis logic stage. The packing stage can not only determine the connection relationship of the prototype device through the logical subnet table, but also directly determine the box structure to which the prototype device in the device group belongs based on the physical scene netlist of the device group, and can also determine the layout constraints between the box structures in the device group based on the layout scene netlist of the device group.

[0078] Based on the method provided in this application, during the binning phase, the binning results of each device group are directly obtained according to the physical scenario netlist of each device group. According to other logical subnet tables, the prototype devices contained in the other logical subnet tables are searched and binned using a binning algorithm to obtain the binning results of other circuit structures other than the device group. That is, based on the method provided in this application, during the binning phase, the prototype devices in each device group no longer participate in the search and binning. During the binning phase, only the prototype devices in the circuit structures other than the device group are searched and binned using a binning algorithm, which greatly reduces the search space during the binning phase and improves the efficiency of the binning phase.

[0079] Moreover, the physical scenario netlist of the device group is obtained based on the functional information and architectural information of the device group. The packing result directly obtained according to the physical scenario netlist of each device group is the optimal packing result that meets the requirements of the functional information and architectural information of the device group, which can achieve accurate and efficient packing of the device group.

[0080] 4. Layout Phase

[0081] The layout phase is based on the global binning results. In conventional design methods, the binning phase passes the binned structures and their interconnected relationships to the layout phase, which then lays out each bin structure in a global state. Given the large number of bin structures, the layout phase is time-consuming in conventional design methods. Furthermore, it's difficult to obtain the desired layout structure solely based on the interconnected relationships between bin structures. For example, in the example above, the circuit structures contained within the four bin structures are used to jointly implement a carry chain function. Conventional design methods only determine that the four bin structures have a connection relationship during the layout phase. Based solely on these interconnected relationships, it's impossible to accurately lay out the four bin structures vertically from bottom to top in carry order as needed. Therefore, the layout results obtained using conventional design methods are often inaccurate, or multiple iterative adjustments are usually required to obtain an accurate layout result.

[0082] In the method provided by this application, the logic subnetlist, physical scenario netlist, and layout scenario netlist generated in the logic synthesis phase are sequentially passed to the binning phase and the layout phase, allowing the layout phase to also use the information flow passed from the synthesis logic phase. When performing layout based on the global binning results, the global binning results are placed based on the layout constraints of the bin structure indicated by the layout scenario netlists of each device group.

[0083] In scenarios where the layout tool uses a virtual rectangular layout method, a global layout is performed using the virtual layout area of ​​the size corresponding to each device group and each box structure obtained by boxing other logical subnet lists as basic units. Each device group directly obtains the relative layout position of each box structure within the corresponding virtual layout area according to the layout constraints of the box structure indicated by the device group's layout scenario netlist. As a result, the box structures in the same device group are all laid out within the virtual layout area of ​​the size corresponding to the device group, achieving a compact layout of the same device group. Moreover, since the relative layout positions of multiple box structures with functional and / or architectural associations within the virtual layout area are also the preset optimal relative positions corresponding to the functional and / or architectural associations, in the obtained layout results, the multiple box structures with functional and / or architectural associations in each device group are directly laid out according to the preset optimal relative positions.

[0084] When the layout tool uses a virtual rectangle layout method, it no longer performs a global layout of the box structures within the device group separately. Instead, it treats each device group as a whole, processes it as a single target body, and places the box structures generated by binning other logical subnets at the same level. This significantly reduces the number of basic units processed during the layout phase and improves global layout efficiency. Furthermore, based on the layout constraints recorded in the device group's layout scenario netlist, it can directly obtain the optimal layout result that meets the functional and architectural requirements of the device group, enabling accurate and efficient layout of the device group.

[0085] In scenarios where it is inconvenient for the layout tool to use the virtual rectangular layout method, the box structures contained in the device group and the box structures obtained by packing other logical subnet tables are at the same level for global layout, that is, each box structure in the obtained packing result is used as the basic unit for global layout, and according to the layout constraints of the box structure indicated by the layout scenario netlist of each device group, the box structures with the same layout weight are compactly laid out in the same local area, and multiple box structures with functional correlation and / or architectural correlation in each device group are directly laid out according to the preset optimal relative positions.

[0086] In scenarios where it is inconvenient for layout tools to use the virtual rectangular layout method, although global layout is still performed with a single box structure as the basic unit, combined with the layout constraints provided by the layout scenario netlist, a compact layout of the same device group can be quickly achieved. Moreover, based on the layout constraints recorded in the layout scenario netlist of the device group, the optimal layout result that meets the functional and architectural information requirements of the device group can be directly obtained, which can achieve accurate and efficient layout of the device group.

[0087] For example, in the example of the carry chain function, since the present application generates a layout scenario netlist in the logic synthesis stage and passes it to the layout stage, based on the layout constraints provided by the layout scenario netlist, the four box structures can be directly laid out vertically from bottom to top in the carry order without the need for multiple iterative adjustments, and the result is an accurate and optimal layout result.

[0088] 5. Wiring stage

[0089] After completing the layout of the chip to be designed, wiring is performed based on the global layout results. This is similar to the method of this stage in the conventional chip design process and will not be described in detail in this application.

[0090] 6. Complete the design phase

[0091] This stage mainly includes operations such as timing analysis and bit stream generation, which are similar to the methods of this stage in the conventional chip design process. This application will not go into details and will eventually complete the chip design of the chip to be designed.

[0092] Based on the method provided in this application, in one example, assuming that a device group includes a 256-to-1 multiplexer circuit, during the logic synthesis stage:

[0093] The logical subnet list of the device group obtained through the logic netlist scene (Netlist View) is as follows Figure 3 As shown, due to limited space, the overall logic subnet table of the device group cannot show the connection relationship in detail, but the connection relationship of the 256-to-1 multiplexer circuit is known to those skilled in the art, and the dotted box shows an enlarged view of the logic subnet table of part of the circuit structure.

[0094] The physical scene netlist of the device group is obtained through the packing view. Figure 4 As shown, the physical scene netlist of the device group includes 17 box structures S0 to S16, and the box structures S0 to S15 are directly connected to the box structure S16 and have a direct drive relationship. The specific connection relationship is as follows Figure 4 As shown, the 256-to-1 multiplexer selection circuit includes 17 16-to-1 multiplexers, and each box structure includes a circuit structure of a 16-to-1 multiplexer.

[0095] The layout scene netlist obtained through the layout scene (Placement View) is as follows Figure 5 As shown, the layout constraints between the box structures added to the layout scenario netlist of the device group relative to the physical scenario netlist include: the relative layout position of each box structure S0~S16 in the virtual layout area, such as Figure 5 As shown, for example, the box structure S0 is located at the horizontal coordinate X0 and the vertical coordinate Y0 of the virtual layout area. The device group includes a total of 17 box structures, and there is no box structure with functional relevance and / or architectural relevance. Therefore, according to the number of box structures, the width of the virtual layout area is determined to be 4 columns, respectively recorded as X0 to X3, and the height is determined to be 5 rows, respectively recorded as Y0 to Y4. The relative layout position of each box structure in the virtual layout area is determined according to the connection relationship between the box structures, so that the layout distance between the box structures with a direct drive relationship, that is, the total layout distance of the box structures S0 to S15 relative to the box structure S16 is minimized, thereby obtaining the following Figure 5 The relative layout positions of the various box structures shown are within the virtual layout area.

[0096] The obtained logical subnet list, physical scene netlist and layout scene netlist of the device group are passed to the packing stage. In the packing stage, there is no need to search the box structure in the device group for packing. The structure indicated by the physical scene netlist is directly obtained. Figure 4 The layout scenario netlist is passed to the layout stage. In the layout stage, there is no need to layout the box structures in the device group separately. Instead, the device group is taken as a whole to determine the layout position of the virtual layout area of ​​the device group. Then, according to the information provided by the layout scenario netlist, the following can be directly implemented: Figure 5 The layout shown.

Claims

1. A chip design method based on the transmission of integrated information flow, characterized in that: The method comprises: Obtaining an RTL-level description file, parsing description statements in the RTL-level description file, identifying and obtaining a plurality of device groups, and adding the groups to a mapping library containing a plurality of prototype devices; Performing logic synthesis on the RTL-level description file based on the mapping library to obtain respective logical subnet tables and physical scenario netlists for several device groups, as well as other logical subnet tables for other circuit structures other than the device groups; wherein each logical subnet table is expressed using prototype devices with connection relationships as basic units; the physical scenario netlist of each device group is expressed using box structures with connection relationships as basic units, and the prototype devices in the logical subnet table of each device group are assigned to corresponding box structures based on functional information and architectural information of the device group determined in the logic synthesis stage; In the binning stage, the binning results of each device group are directly obtained according to the physical scenario netlist of each device group, and the prototype devices contained in the other logical subnet tables are searched and binned using the binning algorithm according to the other logical subnet tables to obtain the binning results; Placement and routing are performed based on the global binning results, and chip design for the chip to be designed is completed.

2. The method according to claim 1, characterized in that When determining the box structure to which each prototype device in the device group belongs based on the functional information and architectural information of the device group during the logic synthesis processing stage, the prototype devices contained in the circuit structure in the device group used to implement predetermined logical functions and / or have a predetermined circuit architecture are assigned to the box structure according to the corresponding preset optimal packing method.

3. The method according to claim 1, characterized in that The method further comprises: In the logic synthesis processing stage, a layout scenario netlist of each device group is obtained by logic synthesis processing of the RTL-level description file, each layout scenario netlist is expressed using a box structure with layout constraints as a basic unit, and the box structure in the physical scenario netlist of each device group determines the layout constraints based on the functional information and architecture information of the device group determined in the logic synthesis stage; When performing layout based on the global binning result, the layout of the global binning result is completed based on the layout constraints of the bin structure indicated by the layout scenario netlist of each device group.

4. The method according to claim 3, characterized in that When determining the layout constraints of the box structures in the device group based on the functional information and architectural information of the device group during the logic synthesis processing stage, the layout constraints between multiple box structures with functional associations and / or architectural associations are determined to be layout of these multiple box structures according to preset optimal relative positions corresponding to the functional associations and / or architectural associations.

5. The method according to claim 4, characterized in that When determining the layout constraints of the box structures in the device group based on the functional information and architectural information of the device group during the logic synthesis processing stage, it also includes determining the layout constraints between all box structures in the same device group to compactly layout all box structures in the same device group within the same local area.

6. The method according to claim 5, characterized in that The layout constraints of the box structures in each device group include the relative layout positions of each box structure within a virtual layout area of ​​a corresponding size of the device group. Each device group corresponds to a different virtual layout area, and the size of the virtual layout area corresponding to each device group corresponds to the total number of box structures included and the preset optimal relative positions between multiple box structures that have functional associations and / or architectural associations.

7. The method according to claim 6, characterized in that The relative layout position of each box structure in the device group within the virtual layout area corresponding to the device group is determined with the goal of minimizing the layout distance between box structures in a direct driving relationship.

8. The method according to claim 6, characterized in that When performing layout based on global box packing results, global layout is performed with the virtual layout area of ​​the size corresponding to each device group and each box structure obtained by box packing other logical subnet tables as basic units, and each device group directly obtains the relative layout positions of each box structure in the corresponding virtual layout area according to the layout constraints of the box structure indicated by the layout scenario netlist of the device group to achieve compact layout. In the obtained layout results, multiple box structures with functional correlation and / or architectural correlation in each device group are directly laid out according to the preset optimal relative positions.

9. The method according to claim 5, characterized in that The layout constraints of the box structures in each device group include the layout weights of the box structures. All box structures contained in the same device group have the same layout weight, and box structures contained in different device groups have different layout weights.

10. The method according to claim 9, characterized in that When performing layout based on global binning results, global layout is performed using each box structure in the obtained binning results as a basic unit, and box structures with the same layout weights are compactly laid out in the same local area according to the layout constraints of the box structures indicated by the layout scenario netlist of each device group. Multiple box structures with functional and / or architectural associations in each device group are directly laid out according to preset optimal relative positions.

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