An anti-miswriting control method, device and electrical equipment for a memory chip

Abstract

The present invention discloses a memory chip anti-miswrite control method, device and electrical equipment. The method includes: judging whether the main control chip has a write demand for the memory chip; when there is a write demand, recording the memory chip page number corresponding to the write demand; after a first preset time delay, judging again whether the main control chip has a new write demand for the memory chip; when there is a new write demand, after a first preset time delay, performing a write operation on the memory chip according to the recorded page number; wherein the first preset time is greater than or equal to the time required for the main control chip to drop from the lowest working voltage to the lowest working voltage of the memory chip after power failure. The present invention uses a dual delay strategy to make the mainboard power supply voltage decay to below the lowest working voltage of the memory chip before performing a write operation when power failure occurs, thereby avoiding performing a write operation during the time period from the lowest working voltage of the main control chip to the lowest working voltage of the memory chip, and avoiding the possibility of the memory chip being miswritten in the low voltage range.

Description

Technical Field

[0001] The present invention relates to the field of control technology, and in particular to a memory chip anti-miswriting control method, device and electrical equipment. Background Art

[0002] EEPROM (Electrically Erasable Programmable Read Only Memory) is a memory chip that retains data after a power outage. Electrical devices (such as air conditioners and washing machines) use EEPROM as a memory chip to store important operating parameters. Accidental writes to the memory chip, such as incorrect data, can cause malfunction. When the device's controller motherboard is in a low-voltage state after a power outage, this can easily cause an inadvertent write to the memory chip.

[0003] The minimum operating voltage of the main control chip (MCU) is higher than the minimum operating voltage of the memory chip (EEPROM). After the controller motherboard loses power, the power supply voltage drops, and there is a low voltage range. This range is lower than the minimum operating voltage of the main control chip and higher than the minimum operating voltage of the memory chip. At this time, the main control chip's RAM (Random Access Memory) data becomes abnormal due to the low voltage, but the memory chip can still be written normally, which may cause the memory chip to be written incorrectly.

[0004] The current method for preventing device parameters from being rewritten can determine whether the data in the memory chip is normal after power-on. If it is normal, it will be used. If it is not normal, the backup data from the last power failure will be used. This method can restore the data in the memory chip to the normal state data of the last backup, but it cannot prevent the memory chip from being written by mistake, which will cause more updated parameters to not be memorized.

[0005] With respect to the problem in the prior art that the main control chip of a device may miswrite the memory chip when the power is off, no effective solution has been proposed. Summary of the Invention

[0006] The embodiments of the present invention provide a memory chip miswrite prevention control method, device and electrical equipment, so as to at least solve the problem in the prior art that the main control chip of the equipment may miswrite the memory chip when the power is off.

[0007] To solve the above technical problems, an embodiment of the present invention provides a memory chip anti-miswrite control method, comprising:

[0008] Determine whether the main control chip has a writing requirement for the memory chip;

[0009] When there is a writing demand, the memory chip page number corresponding to the writing demand is recorded;

[0010] After a first preset delay, determining again whether the main control chip has a new write request for the memory chip;

[0011] When there is a new write request, after a first preset time delay, a write operation is performed on the memory chip according to the recorded page number;

[0012] The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.

[0013] Optionally, after determining whether the main control chip has a write requirement for the memory chip, it also includes: when there is no write requirement, after a delay of a second preset time, returning to execute the step of determining whether the main control chip has a write requirement for the memory chip; wherein, the second preset time is less than the first preset time.

[0014] Optionally, after determining again whether the main control chip has a new write request for the memory chip, the method further includes: when there is no new write request, directly performing a write operation on the memory chip according to the recorded page number.

[0015] Optionally, judging whether the main control chip has a write requirement for the memory chip, or judging again whether the main control chip has a new write requirement for the memory chip, includes: judging whether the data in the data update area and the data backup area of the main control chip are consistent; if the data are consistent, determining that there is no write requirement; if the data are inconsistent, determining that there is a write requirement; wherein, the data update area is used to store data that needs to be written to the memory chip, and the data backup area is used to back up the data written to the memory chip.

[0016] Optionally, recording the memory chip page number corresponding to the write demand includes: adding the memory chip page number corresponding to the write demand to a delay queue, and writing the data in the data update area into the data backup area.

[0017] Optionally, the first preset time is N memory chip update cycles.

[0018] Optionally, the second preset time is a memory chip update cycle.

[0019] An embodiment of the present invention further provides a memory chip anti-miswrite control device, comprising:

[0020] The first judgment module is used to judge whether the main control chip has a writing requirement for the memory chip;

[0021] A recording module, configured to record the memory chip page number corresponding to a writing demand when there is a writing demand;

[0022] A first delay module, used for delaying a first preset time;

[0023] A second judgment module is used to judge again whether the main control chip has a new writing demand for the memory chip after a first preset delay time;

[0024] The second delay module is used to delay the first preset time when there is a new write request;

[0025] An execution module, configured to execute a write operation on the memory chip according to the recorded page number after a first preset delay time;

[0026] The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.

[0027] An embodiment of the present invention further provides an electrical device, comprising: the memory chip anti-miswrite control device according to the embodiment of the present invention.

[0028] Optionally, the electrical equipment includes: an air conditioner, a washing machine, a refrigerator, a water heater, a fan, a dryer, an air purifier, a water purifier or a water purifier.

[0029] An embodiment of the present invention further provides a non-volatile computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method described in the embodiment of the present invention are implemented.

[0030] The technical solution of the present invention is applied to determine whether the main control chip has a write demand for the memory chip. When there is a write demand, the memory chip page number corresponding to the write demand is recorded. After a delay of a first preset time, it is again determined whether the main control chip has a new write demand for the memory chip. When there is a new write demand, after a delay of a first preset time, a write operation is performed on the memory chip according to the recorded page number, wherein the first preset time is greater than or equal to the time required for the voltage to drop from the lowest operating voltage of the main control chip to the lowest operating voltage of the memory chip after power failure. After the need to write to the memory chip is generated, a double delay strategy is used to allow the power supply voltage of the controller mainboard to decay to below the lowest operating voltage of the memory chip in the event of a power failure before the write operation is performed, thereby avoiding the write operation from the time when the lowest operating voltage of the main control chip drops to the lowest operating voltage of the memory chip, thereby avoiding the possibility of the memory chip being mistakenly written in the low voltage range, ensuring stable operation of the device, and solving the problem that the main control chip of the device may mistakenly write to the memory chip when the power is off. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a graph showing the voltage drop of the controller mainboard after power failure of the air-conditioning unit according to an embodiment of the present invention;

[0032] Figure 2 This is a flow chart of a memory chip anti-miswrite control method provided by an embodiment of the present invention;

[0033] Figure 3 This is a control flow chart of a dual-delay write memory chip provided by an embodiment of the present invention;

[0034] Figure 4 This is a structural block diagram of a memory chip anti-miswrite control device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products, or apparatus.

[0037] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] The optional embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] like Figure 1The figure shows the voltage drop curve of the controller mainboard after the air conditioner loses power. During the time period t0 to t1, the unit loses power, but the main control chip and memory chip continue to operate normally. During the time period t1 to t2, the main control chip does not operate normally, while the memory chip continues to operate normally. During the time period t1 to t2, the main control chip may generate abnormal data. Due to the difference in the operating voltage of the main chip and the memory chip, the memory chip may be incorrectly written. During the time period greater than t2, both the main chip and the memory chip do not operate normally. When the controller mainboard is in the time period t1 to t2, because the voltage during this time period is lower than the minimum operating voltage of the main chip but higher than the minimum operating voltage of the memory chip, it is easy to trigger the operation of incorrectly writing to the memory chip.

[0040] An embodiment of the present invention provides a memory chip anti-miswrite control method, which can be executed by a main control chip. Figure 2 Flowchart of the memory chip anti-miswrite control method provided by the embodiment of the present invention. Figure 2 As shown, the method includes the following steps:

[0041] S201, determining whether the main control chip has a writing requirement for the memory chip.

[0042] S202: When there is a writing requirement, the memory chip page number corresponding to the writing requirement is recorded.

[0043] S203, after delaying the first preset time, determining again whether the main control chip has a new write request to the memory chip.

[0044] S204 , when there is a new write request, after a first preset time delay, a write operation is performed on the memory chip according to the recorded page number.

[0045] The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure (ie Figure 1 The time period t1 to t2 corresponds to the duration t2-t1). The memory chip is internally divided into several pages, each of which can store several bytes of data. The data of the memory chip is updated in units of pages.

[0046] During the operation of the main control chip, no matter the main control chip is in a normal power supply state or a power-off state, the writing operation is performed on the memory chip according to the method described in the embodiment of the present invention, specifically, the judgment process is performed twice in a cycle.

[0047] The first time it is determined that there is a write request, after the first delay, if the power supply voltage drops below the minimum operating voltage of the memory chip, that is, Figure 1During the period after t2, the memory chip is no longer functioning properly, and no data can be written to it. Consequently, regardless of the second judgment result, no data can be written to the memory chip. In other words, if the write request initially determined to be caused by an abnormal change in the main control chip's RAM due to a power failure, the first delay prevents the write operation from occurring between t1 and t2, and the abnormal data (or erroneous data) will not be written to the memory chip.

[0048] If the first time it is determined that there is a write demand occurs Figure 1 Before time t1, after the first delay, it may fall into the time period of t1 to t2. At this time, no write operation is performed. If a new write demand is determined for the second time, it means that abnormal data is generated in the time period of t1 to t2. After the second delay, it will enter Figure 1 In the time period after t2, the write operation is performed for the first determined write demand, but the memory chip is no longer able to work normally and any data cannot be written into the memory chip. That is, the write operation in the time period t1 to t2 is avoided through two delays.

[0049] In the above two cases, if the write request determined for the first time is normal data and cannot be written into the memory chip, the data will be discarded. This is mainly to prevent the memory chip from being accidentally written during a power outage. By discarding some normal data, the device can still operate normally according to the previous data in the memory chip. However, if the memory chip is accidentally written, when the device uses the erroneous data, it will not operate normally.

[0050] The dual-delay strategy can ensure that no write operation is performed on the memory chip during the time period t1 to t2, thereby preventing accidental writing to the memory chip during power failure.

[0051] This embodiment determines whether the main control chip has a write request to the memory chip. If there is a write request, the memory chip page number corresponding to the write request is recorded. After a first preset time delay, it is determined again whether the main control chip has a new write request to the memory chip. If there is a new write request, after a first preset time delay, a write operation is performed on the memory chip according to the recorded page number, wherein the first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure. After the need to write to the memory chip is generated, a dual delay strategy is used to allow the power supply voltage of the controller motherboard to decay to below the minimum operating voltage of the memory chip in the event of a power failure before performing the write operation. This avoids performing the write operation during the period from the minimum operating voltage of the main control chip to the minimum operating voltage of the memory chip, thereby avoiding the possibility of the memory chip being mistakenly written in the low voltage range, ensuring stable operation of the device, and solving the problem that the main control chip of the device may mistakenly write to the memory chip when the power is off.

[0052] After determining whether the main control chip has a write request to the memory chip in S201, the process further includes: if there is no write request, delaying for a second preset time, and then returning to S201 to determine whether the main control chip has a write request to the memory chip; wherein the second preset time is less than the first preset time. In other words, if the first determination determines that there is no write request, the first determination is repeated after a shorter delay. This ensures that the entire control process for writing to the memory chip continues to execute and that a write request can be detected in a timely manner.

[0053] After S203 determines again whether the main control chip has a new write request to the memory chip, the following further includes: when there is no new write request, directly performing a write operation on the memory chip according to the recorded page number. That is, for the second judgment, if it is determined that there is no new write request, then directly performing a write operation on the memory chip according to the write request determined for the first time. As mentioned above, if the first judgment that there is a write request occurs Figure 1 Before time t1, after the first delay, it may fall into the time period t1~t2. At this time, the write operation is not performed. If it is determined for the second time that there is no new write demand, it means that no abnormal data is generated in the time period t1~t2. There is no need for delay. The write operation is directly performed according to the write demand determined for the first time, and it will not cause the memory chip to be written incorrectly.

[0054] Specifically, the main control chip includes a data update area and a data backup area. The data update area is used to store data that needs to be written to the memory chip, and the data backup area is used to back up the data written to the memory chip. During device operation, after the memory parameters are updated, the data will be written to the data update area.

[0055] S201 determines whether the main control chip has a write request to the memory chip, or S203 determines again whether the main control chip has a new write request to the memory chip, including: determining whether the data in the data update area and the data backup area of the main control chip are consistent; if the data are consistent, it is determined that there is no write request; if the data are inconsistent, it is determined that there is a write request. By comparing the data update area and the data backup area, it is possible to quickly and accurately determine whether a write request has occurred.

[0056] Furthermore, the memory chip page number corresponding to the write request is recorded, including: adding the memory chip page number corresponding to the write request to a delay queue, and writing the data in the data update area to the data backup area. The memory chip page number corresponding to the write request is the page number corresponding to the area where the data in the data update area and the data backup area are inconsistent. Writing the data in the data update area to the data backup area ensures the accuracy of the second judgment. The delay queue effectively implements the delayed write operation.

[0057] The write operation is performed on the memory chip according to the recorded page number, including: reading the memory chip page number from the delay queue, and performing the write operation on the memory chip according to the memory chip page number.

[0058] The memory chip is divided into several pages, each of which can store several bytes of data. The data of the memory chip is updated in units of pages, and each page is scanned in sequence according to a fixed time interval. This time interval is recorded as the memory chip update period T.

[0059] Preferably, the first preset time may be N memory chip update cycles. The second preset time may be one memory chip update cycle. N>0, where the value of N needs to ensure that the time corresponding to N memory chip update cycles is greater than or equal to the time required for the main control chip's minimum operating voltage to drop to the memory chip's minimum operating voltage after power failure.

[0060] The following describes the memory chip miswrite prevention control method using a specific embodiment. However, it should be noted that this specific embodiment is intended only to better illustrate the present application and does not constitute an undue limitation of the present application. Terms that are identical or corresponding to those in the above embodiment will not be repeated in this embodiment.

[0061] Two storage areas are allocated in the main control chip's RAM to store data written to the memory chip: a data update area and a data backup area. The data update area stores data to be written to the memory chip, while the data backup area backs up the data written to the memory chip. During device operation, when memory parameters are updated, the data is written to the data update area.

[0062] like Figure 3 As shown, the control process of the dual-delay write memory chip includes the following steps:

[0063] S301, start.

[0064] S302: First determine whether the data in the data update area and the data backup area are consistent. If they are consistent, proceed to S303; if not, proceed to S304. The purpose of the first data comparison in this step is to determine whether the device has any memory parameter updates during operation, that is, whether there is a need to write to the memory chip.

[0065] S303, delay T, where T represents the memory chip update cycle, and return to execute S302.

[0066] S304: Add the memory chip page number corresponding to the area with inconsistent data to a delay queue.

[0067] S305, writing the data in the data update area into the data backup area.

[0068] S306, first delay N memory chip update cycles T (i.e., delay N×T), where the value of N is based on ensuring that N×T ≥ t2-t1. After the first delay, if the power supply voltage drops below the minimum operating voltage of the memory chip, that is, Figure 1 During the period after t2, the memory chip cannot function normally and will not be written. If the data inconsistency between the data update area and the data backup area is caused by abnormal changes in the RAM of the main control chip due to low voltage, the abnormal data will not be written to the memory chip after the delayed write operation in this step.

[0069] S307, after the first delay, it is determined again whether the data in the data update area is consistent with the data in the data backup area. If they are consistent, the process goes to S308; if they are inconsistent, the process goes to S309.

[0070] S308, performing a write operation on the memory chip according to the memory chip page number recorded in the delay queue, and then returning to S302 to enter the next round of judgment.

[0071] S309, again delay N memory chip update cycles T (ie, delay N × T), after the delay ends, enter S308 to perform a write operation on the memory chip. Figure 1 Before the time t1 in the figure, after the first delay, it may fall into the time period t1 to t2, so another delay is performed to ensure that the memory chip will not be written during the time period t1 to t2 to avoid erroneous write operations.

[0072] Through the dual-delay writing memory chip control method of this embodiment, when the main control chip generates a write request under normal power supply state, the normal data corresponding to the write request will be delayed to be written into the memory chip. However, since the real-time requirement for writing the memory chip is not very high, the delayed writing of the memory chip will not affect the normal operation of the device. It is mainly to avoid miswriting the memory chip and ensure the accuracy of the memory chip data. In the power-off state, the timing of the main control chip executing the write operation is controlled to Figure 1 After time t2.

[0073] The dual-delay writing control method of the memory chip of this embodiment adopts a dual-delay strategy after the demand for writing the memory chip is generated, so that the power supply voltage of the controller mainboard is attenuated to below the minimum operating voltage of the memory chip, avoiding the main control chip from accidentally writing to the memory chip in the low-voltage state of power failure, avoiding the possibility of the memory chip being accidentally written in the low-voltage range, preventing the memory chip from being accidentally written at low voltage during power failure, and ensuring stable operation of the equipment.

[0074] Based on the same inventive concept, this embodiment provides a memory chip anti-miswrite control device that can be used to implement the memory chip anti-miswrite control method described in the above embodiment. The device can be implemented through software and / or hardware and can generally be integrated into a main control chip.

[0075] Figure 4 : is a structural block diagram of a memory chip anti-miswrite control device provided by an embodiment of the present invention, such as Figure 4 As shown, the device includes:

[0076] The first judgment module 41 is used to judge whether the main control chip has a writing requirement for the memory chip;

[0077] The recording module 42 is used to record the memory chip page number corresponding to the writing request when there is a writing request;

[0078] A first delay module 43, configured to delay for a first preset time;

[0079] A second judgment module 44 is used to judge again whether the main control chip has a new writing request for the memory chip after a first preset delay time;

[0080] The second delay module 45 is used to delay the first preset time when there is a new write request;

[0081] An execution module 46 is configured to execute a write operation on the memory chip according to the recorded page number after a first preset delay time;

[0082] The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.

[0083] Optionally, the above-mentioned device also includes: a third delay module, which is used to, after determining whether the main control chip has a write requirement for the memory chip, return to execute the step of determining whether the main control chip has a write requirement for the memory chip after a second preset time when there is no write requirement; wherein, the second preset time is less than the first preset time.

[0084] Optionally, the execution module 46 is further configured to: after again determining whether the main control chip has a new write request for the memory chip, when there is no new write request, directly perform a write operation on the memory chip according to the recorded page number.

[0085] Optionally, the first judgment module 41 or the second judgment module 44 includes:

[0086] A judging unit, configured to judge whether the data in the data update area and the data backup area of the main control chip are consistent;

[0087] A first determining unit, configured to determine that there is no write requirement if the data is consistent;

[0088] A second determining unit, configured to determine that a write request exists if the data is inconsistent;

[0089] The data update area is used to store data that needs to be written into the memory chip, and the data backup area is used to back up the data written into the memory chip.

[0090] Optionally, the recording module 42 is specifically configured to: add the memory chip page number corresponding to the write request to a delay queue, and write the data in the data update area into the data backup area.

[0091] Optionally, the first preset time is N memory chip update cycles.

[0092] Optionally, the second preset time is a memory chip update cycle.

[0093] The aforementioned memory chip miswrite prevention control device can execute the memory chip miswrite prevention control method provided by the embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not fully described in this embodiment, please refer to the memory chip miswrite prevention control method provided by the embodiment of the present invention.

[0094] An embodiment of the present invention further provides an electrical device, comprising: the memory chip anti-miswrite control device described in the above embodiment.

[0095] Electrical appliances may include: air conditioners, washing machines, refrigerators, water heaters, fans, dryers, air purifiers, water purifiers or water purifiers.

[0096] An embodiment of the present invention further provides a non-volatile computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method described in the above embodiment are implemented.

[0097] An embodiment of the present invention further provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in the above embodiment when executing the computer program.

[0098] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0099] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A memory chip anti-miswrite control method, characterized in that: include: Determine whether the main control chip has a writing requirement for the memory chip; When there is a writing demand, the memory chip page number corresponding to the writing demand is recorded; After a first preset delay, determining again whether the main control chip has a new write request for the memory chip; When there is a new write request, after a first preset time delay, a write operation is performed on the memory chip according to the recorded page number; When there is no new write demand, the write operation is directly performed on the memory chip according to the recorded page number; The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.

2. The method according to claim 1, characterized in that After determining whether the main control chip has a write requirement for the memory chip, it also includes: When there is no write request, after a second preset time delay, returning to the step of determining whether the main control chip has a write request for the memory chip; The second preset time is shorter than the first preset time.

3. The method according to claim 1, characterized in that Determining whether the main control chip has a write demand for the memory chip, or determining again whether the main control chip has a new write demand for the memory chip, includes: Determine whether the data in the data update area and the data backup area of the main control chip are consistent; If the data is consistent, it is determined that there is no write requirement; If the data is inconsistent, it is determined that there is a write requirement; The data update area is used to store data that needs to be written into the memory chip, and the data backup area is used to back up the data written into the memory chip.

4. The method according to claim 3, characterized in that Recording the memory chip page number corresponding to the write request includes: The memory chip page number corresponding to the write request is added to a delay queue, and the data in the data update area is written into the data backup area.

5. The method according to any one of claims 1 to 4, characterized in that The first preset time is N memory chip update cycles.

6. The method according to claim 2, characterized in that The second preset time is a memory chip update cycle.

7. A memory chip anti-miswriting control device, characterized in that: include: The first judgment module is used to judge whether the main control chip has a writing requirement for the memory chip; A recording module, configured to record the memory chip page number corresponding to a writing demand when there is a writing demand; A first delay module, used for delaying a first preset time; A second judgment module is used to judge again whether the main control chip has a new writing demand for the memory chip after a first preset delay time; The second delay module is used to delay the first preset time when there is a new write request; an execution module, configured to execute a write operation on the memory chip according to the recorded page number after the second delay module delays for a first preset time; and, when there is no new write request, directly execute a write operation on the memory chip according to the recorded page number; The first preset time is greater than or equal to the time required for the minimum operating voltage of the main control chip to drop to the minimum operating voltage of the memory chip after power failure.

8. An electrical device, characterized in that: include: The memory chip anti-miswriting control device as claimed in claim 7.

9. The electrical equipment according to claim 8, characterized in that: The electrical equipment includes: air conditioners, washing machines, refrigerators, water heaters, fans, dryers, air purifiers, water purifiers or water purifiers.

10. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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