Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a display area and a non-display area that at least partially surrounds the display area. The non-display area includes a first frame and a second frame that are relatively arranged along a first direction. The first frame and / or the second frame include virtual pixels. The virtual pixels are arranged along a second direction. The first direction intersects with the second direction. The first frame and / or the second frame also include a first type of signal line. The first type of signal line extends along the second direction. The display panel includes a substrate. In the present invention, in a direction perpendicular to the plane where the substrate is located, the first type of signal line at least partially overlaps with the virtual pixel, so that the first frame and / or the second frame can be further compressed to achieve a narrow frame.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] As full-screen phones become more and more popular, users have higher and higher requirements not only for the functions and performance of full-screen phones, but also for their appearance. For example, full-screen phones with narrower borders can have a larger effective display area, thus providing users with a better visual experience. Full-screen phones are a relatively broad definition of ultra-high screen-to-body ratio phones in the mobile phone industry. Literally, the front of the phone is all screen, and the four borders of the phone are borderless, pursuing a screen-to-body ratio close to 100%. However, multiple signal lines and electronic components such as gate drive circuits need to be arranged in the left and right borders, so the left and right borders cannot be further compressed in the existing technology.

[0003] Therefore, there is an urgent need to provide a display panel and a display device that can further compress the left and right frames. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device, which are used to further compress the left and right frames to achieve a narrow frame.

[0005] In one aspect, the present invention provides a display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a first frame and a second frame arranged opposite to each other along a first direction, the first frame and / or the second frame include virtual pixels, the virtual pixels are arranged along a second direction, the first direction intersects with the second direction, the first frame and / or the second frame further include a first type of signal line, and the first type of signal line extends along the second direction;

[0006] The display panel includes a base substrate, and in a direction perpendicular to a plane where the base substrate is located, the first-type signal lines at least partially overlap with the virtual pixels.

[0007] On the other hand, the present invention further provides a display device, comprising the above display panel.

[0008] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0009] The display panel of the present invention includes virtual pixels in the first frame and / or the second frame, and also includes a first type of signal line in the first frame and / or the second frame. The virtual pixels and the first type of signal lines are elements that must be set up in the display panel. The first type of signal lines extend along the second direction and are used to transmit electrical signals. In the direction perpendicular to the plane where the substrate is located, the first type of signal lines and the virtual pixels at least partially overlap, which can save the space occupied by the first type of signal lines, further compress the first frame and / or the second frame, and achieve a narrow frame.

[0010] Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0011] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0014] Figure 2 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0015] Figure 3 yes Figure 1 A cross-section in the A-A' direction;

[0016] Figure 4 This is a pixel circuit structure diagram provided by the present invention;

[0017] Figure 5 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0018] Figure 6 yes Figure 5 A cross-section in the B-B' direction;

[0019] Figure 7 yes Figure 5 Another cross-section in the B-B' direction;

[0020] Figure 8 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0021] Fig. 9 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0022] Fig.10 yes Fig. 9 A cross-section in the C-C' direction;

[0023] Fig.11 is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0024] Fig.12 It is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0026] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0027] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0028] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0029] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0030] In view of the problem that the display panel of the related art cannot further compress the left and right borders, the present invention provides a display panel and a display device for further compressing the left and right borders to achieve a narrow border. The embodiments of the display panel and the display device will be described in detail below.

[0031] Reference Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by the present invention, Figure 21 is a schematic diagram of a planar structure of another display panel provided by the present invention. The display panel 100 of the present embodiment includes a display area AA and a non-display area BB at least partially surrounding the display area AA. The non-display area BB includes a first frame BB1 ​​and a second frame BB2 that are arranged opposite to each other along a first direction X. The first frame BB1 ​​and / or the second frame BB2 include virtual pixels P2, and the virtual pixels P2 are arranged along a second direction Y. The first direction X intersects with the second direction Y. The first frame BB1 ​​and / or the second frame BB2 also include a first type of signal line 111, and the first type of signal line 111 extends along the second direction Y.

[0032] The display panel 100 includes a base substrate 91 . In a direction perpendicular to a plane where the base substrate 91 is located, the first-type signal line 111 at least partially overlaps with the virtual pixel P2 .

[0033] Specifically, Figure 1 Only the case where the non-display area BB completely surrounds the display area AA is shown. Of course, the non-display area BB may also partially surround the display area AA, which is not specifically limited here. The non-display area BB includes a first frame BB1 ​​and a second frame BB2 that are arranged opposite to each other along the first direction X. Here, the first frame BB1 ​​may be a left frame, and the second frame BB2 may be a right frame. A gate driving circuit VSR needs to be set in the left frame or the right frame of the display panel 100 to control the scan line in the pixel circuit Q. If the display panel 100 is unilaterally driven, such as Figure 2 As shown, the gate driving circuit VSR is only located in the first frame BB1 ​​or the second frame BB2. Figure 2 In the example, the gate driving circuit VSR is located in the first frame BB1. Of course, the gate driving circuit VSR can also be located only in the second frame BB2. No specific limitation is made here. If the display panel 100 is bilaterally driven, refer to Figure 1 , then the gate drive circuit VSR is set in both the first frame BB1 ​​and the second frame BB2. The first frame BB1 ​​and / or the second frame BB2 also include a first type of signal line 111, and the first type of signal line 111 extends along the second direction Y. Here, the first type of signal line 111 can transmit electrical signals for the pixels P1 in the display area AA, and can also transmit electrical signals for the gate drive circuit VSR, which is not specifically limited here.

[0034] It can be understood that the pixels P of the display panel 100 include normal display pixels P1 and dummy pixels P2 in the display area AA. The normal display pixels P1 are arranged in the display area AA, and the dummy pixels P2 surround the display pixels P1 and are arranged in the non-display area BB, that is, the dummy pixels P2 are arranged in the frame. The dummy pixels P2 are mainly arranged to alleviate the load effect in the display panel manufacturing process and to improve the uniformity of the high-precision metal mask evaporation process, thereby improving the uniformity of the display of the display pixels P1 in the display area AA. The dummy pixels P2 are not connected to the electrical signal, and the dummy pixels P2 do not emit light. Figure 1 and Figure 2 The number and shape of the display pixels P1 and the virtual pixels P2 are only for schematic illustration and are not intended to limit actual products. The number and shape of the display pixels P1 and the virtual pixels P2 may be set according to actual product requirements.

[0035] Figure 1 and Figure 2 The figure also shows a driver chip IC, which provides electrical signals for the first type signal line 111. Figure 1 and Figure 2 The scanning line G and the data line D are also shown.

[0036] The display panel 100 of the present invention may be an organic self-luminous display panel. Each pixel P1 in the display area of ​​the display panel 100 includes a pixel circuit Q. Figure 4 , Figure 4: is a pixel circuit structure diagram provided by the present invention, the pixel circuit Q can be 7T1C, including: a first transistor M1, a control end of which is electrically connected to the light emitting signal input end, a first end of which is electrically connected to the first power signal end PVDD, and a second end of which is electrically connected to the first end of the driving transistor M; a second transistor M2, a control end of which is electrically connected to the second scan signal input end S2, a first end of which is electrically connected to the data signal input end Vdata, and a second end of which is electrically connected to the first end of the driving transistor M; a driving transistor M, a control end of which is electrically connected to the second end of the fourth transistor M4, a first end of which is electrically connected to the second end of the first transistor M1 and the second end of the second transistor M2; a third transistor M3, a control end of which is electrically connected to the second scan signal input end S2, a first end of which is electrically connected to the second end of the fourth transistor M4 and the second end of the storage capacitor Cst, and a second end of which is electrically connected to the second end of the driving transistor M and the first end of the fifth transistor M5; a fourth transistor M4, a control end of which is electrically connected to the second scan signal input end S2, a first end of which is electrically connected to the second end of the fourth transistor M4 and the second end of the storage capacitor Cst, and a second end of which is electrically connected to the second end of the driving transistor M and the first end of the fifth transistor M5; The first end of the storage capacitor Cst is electrically connected to the first scan signal input terminal S1, the first end is electrically connected to the reference voltage signal input terminal Vref, and the second end is electrically connected to the control end of the driving transistor M; the fifth transistor M5, the control end of which is electrically connected to the light-emitting signal input terminal Emit, the first end is electrically connected to the second end of the driving transistor M and the second end of the third transistor M3, and the second end is electrically connected to the anode of the light-emitting element O; the sixth transistor M6, the control end of which is electrically connected to the second scan signal input terminal, the first end is electrically connected to the reference voltage signal input terminal Vref, and the second end is electrically connected to the first end of the light-emitting element O; the light-emitting element O, the first end of which is electrically connected to the second end of the fifth transistor M5 and the second end of the sixth transistor M6, and the second end is electrically connected to the second power signal terminal PVEE; the storage capacitor Cst, the first end of which is electrically connected to the first power signal terminal PVDD, and the second end is electrically connected to the control end of the driving transistor M, the first end of the third transistor M3 and the second end of the fourth transistor M4.

[0037] Reference Figure 3 , Figure 3 yes Figure 1 A cross-sectional view taken along the A-A' direction in the figure, in this embodiment, the display panel 100 includes: a base substrate 91; a thin film transistor 20 located on one side of the base substrate 91; a light emitting device 30 located on the side of the thin film transistor 20 away from the base substrate 91; the light emitting device 30 includes an anode layer 310, a light emitting layer 320 located on the side of the anode away from the base substrate 91, and a cathode 330 located on the side of the light emitting layer 320 away from the base substrate 91. The thin film transistor 20 drives the light emitting device 30 to emit light for display. Figure 4The figure also shows a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a planarization layer 97, and a pixel definition layer 98. The thin film transistor 20 includes a second metal layer M12 (source and drain), and a first metal layer M11 is provided between the anode layer 310 and the second metal layer M12. Optionally, the thin film transistor is located on the buffer layer 92. Figure 3 In the structure description, only the top-gate thin film transistor is used as an example. The thin film transistor 20 includes a semiconductor active layer 201 located on the buffer layer 92, and the semiconductor active layer 201 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions. The region between the source region and the drain region is a channel region in which impurities are not doped. The semiconductor active layer 201 can be formed by changing amorphous silicon into polycrystalline silicon by crystallization of amorphous silicon. In order to crystallize amorphous silicon. The first metal layer M11 (gate) is located on the gate insulating layer, and the gate may include a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo) or chromium (Cr), or an alloy such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy. The first metal layer M11 has a source and a drain, and the source and the drain are electrically connected (or coupled) to the source region and the drain region of the active layer 201 respectively through contact holes, and the contact holes are formed by selectively removing the insulating layer. Figure 3 Also shown is the encapsulation layer 50 located on the side of the light-emitting device 30 away from the base substrate 91. The optional encapsulation layer 50 is a stacked structure of an inorganic encapsulation layer, an organic encapsulation layer and an inorganic encapsulation layer. Of course, the specific structure of the encapsulation layer 50 is not limited in the present invention. The encapsulation layer 50 can have multiple layers of inorganic encapsulation layers and multiple layers of organic encapsulation layers, so as to provide good protection for the light-emitting device 30 in the display area AA. Figure 1 In order to distinguish the data lines from the first type of signal lines, different patterns are filled for the data lines and the first type of signal lines.

[0038] In the related art, in the direction from the non-display area BB to the display area AA, the first type of signal line 111 can be located between the virtual pixel P2 and the gate drive circuit VSR, or the first type of signal line 111 is located on the side of the gate drive circuit VSR away from the display area AA, so that the non-display area BB cannot be further compressed, which is not conducive to achieving a narrow frame. In the present invention, in the direction perpendicular to the plane where the substrate 91 is located, the first type of signal line 111 at least partially overlaps with the virtual pixel P2, so that the first type of signal line 111 is set at the position of the virtual pixel P2, which can save the space occupied by the first type of signal line 111, that is, the space between the virtual pixel P2 and the gate drive circuit VSR occupied by the first type of signal line 111 is saved, or the space on the side of the gate drive circuit VSR away from the display area AA occupied by the first type of signal line 111 is saved, thereby further compressing the first frame BB1 ​​and / or the second frame BB2, and further achieving a narrow frame.

[0039] In some optional embodiments, continue to refer to Figure 1 The first type signal line 111 includes at least one of a reset signal line 1111 , a high potential signal line 1112 , and a low potential signal line 1113 .

[0040] It can be understood that the first type of signal line 111 can be a reset signal line 1111, and the reset signal line 1111 extends along the second direction Y. Figure 4 The reference voltage signal input terminal Vref of the pixel circuit Q transmits a reset signal, and the reset signal line 1111 is electrically connected to the pixel circuit Q. The reset signal only needs a fixed potential, so the reset signal line 1111 here can extend along the second direction Y and transmit the same fixed potential. The first type of signal line 111 can also be a high potential signal line 1112 or a low potential signal line 1113. The high potential signal line 1112 transmits a high level for the gate drive circuit VSR, and the low potential signal line 1113 transmits a low level for the gate drive circuit VSR. The high potential signal line 1112 and the low potential signal line 1113 are electrically connected to the gate drive circuit VSR.

[0041] The reset signal line 1111, the high potential signal line 1112, and the low potential signal line 1113 are all signal lines that must be set in the first frame BB1 ​​or the second frame BB2, and they must occupy the space of the first frame BB1 ​​or the second frame BB2. In the direction perpendicular to the plane where the substrate 91 is located, at least one of the reset signal line 1111, the high potential signal line 1112, and the low potential signal line 1113 is at least partially overlapped with the virtual pixel P2, for example, the reset signal line 1111 is at least partially overlapped with the virtual pixel P2, or the high potential signal line 1112 is overlapped with the virtual pixel P2. 112 at least partially overlaps with the virtual pixel P2, or the low potential overlaps with the virtual pixel P2 at least partially, or the reset signal line 1111 and the high potential signal line 1112 at least partially overlap with the virtual pixel P2, or the reset signal line 1111 and the low potential signal line 1113 at least partially overlap with the virtual pixel P2, all of which can save the space occupied by the reset signal line 1111, the high potential signal line 1112, or the low potential signal line 1113, can further compress the first border BB1 and / or the second border BB2, and can further achieve a narrow border.

[0042] In some optional embodiments, referring to Figure 5 , Figure 5 It is a schematic diagram of the planar structure of another display panel provided by the present invention. In this embodiment, the first type of signal line 111 is a reset signal line 1111. The reset signal line 1111 includes an electrically connected first portion 1111a and a second portion 1111b. The first portion 1111a extends along the second direction Y, and the second portion 1111b extends from the first frame BB1 ​​and / or the second frame BB2 to the display area AA.

[0043] It can be understood that the first portion 1111a of the reset signal line 1111 extends along the second direction Y, the second portion 1111b is electrically connected to the first portion 1111a, and the second portion 1111b is electrically connected to the first portion 1111a. Figure 4 The reference voltage signal input terminal Vref of the pixel circuit Q is electrically connected, and the reset signal line 1111 transmits a reset signal. Figure 5 The figure shows the situation where the reset signal line 1111 is located in the first frame BB1 ​​and the second frame BB2. In this case, the second part 1111b extends from the first frame BB1 ​​and the second frame BB2 to the display area AA respectively. Of course, the reset signal line 1111 may be located only in the first frame BB1. In this case, the second part 1111b extends from the first frame BB1 ​​to the display area AA, or the reset signal line 1111 is located only in the second frame BB2. In this case, the second part 1111b extends from the second frame BB2 to the display area AA.

[0044] In this embodiment, in a direction perpendicular to the plane of the base substrate 91, the reset signal line 1111 is at least partially overlapped with the virtual pixel P2, so that the space occupied by the reset signal line 1111 can be saved, the first border BB1 and / or the second border BB2 can be further compressed, and a narrow border can be further achieved.

[0045] In some optional embodiments, continue to refer to Figure 5 and reference Figure 6 , Figure 6 yes Figure 5 A cross-sectional view taken along the B-B' direction, the display panel 100 further includes a first metal layer M11 located on one side of the base substrate 91, a capacitor metal layer MC located on the side of the first metal layer M11 away from the base substrate 91, a second metal layer M12 located on the side of the capacitor metal layer MC away from the base substrate 91, and a third metal layer M13 located on the side of the second metal layer M12 away from the base substrate 91, wherein the first portion 1111a is in the same layer as the third metal layer M13, the second portion 1111b is in the same layer as the capacitor metal layer MC, and the first portion 1111a is electrically connected to the second portion 1111b.

[0046] Combination Figure 3 and Figure 6 The display panel 100 includes a first metal layer M11 located on one side of the base substrate 91, the scanning line G is located on the first metal layer M11, and a capacitor metal layer MC is provided on the side of the first metal layer M11 away from the base substrate 91. The capacitor metal layer MC is used to form Figure 4 The second metal layer M12 is located on the side of the capacitor metal layer MC away from the substrate 91, the source and drain of the driving transistor are located on the second metal layer M12, the third metal layer M13 is located on the side of the second metal layer M12 away from the substrate 91, the data line D is formed on the third metal layer M13, in this embodiment, the first part 1111a is in the same layer with the third metal layer M13, the second part 1111b is in the same layer with the capacitor metal layer MC, the first part 1111a is electrically connected to the second part 1111b, and at the position corresponding to the virtual pixel P2, the reset signal line 1111 is switched from the third metal layer M13 to The capacitor metal layer MC, so the second part 1111b is routed along the capacitor metal layer MC, and in the display area AA, the data line D is routed along the third metal layer M13. If the second part 1111b and the first part 1111a are in the same layer and still route the third metal layer M13, then in the display area AA, the second part 1111b will cross-circuit with the data line D and cause a short circuit, thereby affecting the display of the display area AA. In this embodiment, the first part 1111a routes along the third metal layer M13, and the second part 1111b routes along the capacitor metal layer MC, so that the second part 1111b will not cross-electrically connect with the data line D and will not cause a short circuit with the data line D, thereby ensuring the stability of the display in the display area AA.

[0047] Optionally, the first portion 1111a is electrically connected to the second portion 1111b through a via.

[0048] In some optional embodiments, referring to Figure 7 , Figure 7 yes Figure 5 In another cross-sectional view along the BB′ direction, the reset signal line 1111 further includes a transition connection portion 1111c, which is electrically connected to the first portion 1111a and the second portion 1111b, respectively, and the transition connection portion 1111c is in the same layer as the second metal layer M12.

[0049] It can be understood that the first part 1111a is on the same layer as the third metal layer M13, and the second part 1111b is on the same layer as the capacitor metal layer MC. The first part 1111a and the second part 1111b need to be electrically connected through a via. However, there are more film layers between the third metal layer M13 and the capacitor metal layer MC, and the depth of the electrical connection via is relatively large. In this embodiment, a transition connection part 1111c is set between the first part 1111a and the second part 1111b, and the transition connection part 1111c is on the same layer as the second metal layer M12. In this way, the first part 1111a is first electrically connected to the transition connection part 1111c of the second metal layer M12 through the via, and the transition connection part 1111c is then electrically connected to the second part 1111b of the capacitor metal layer MC through the via. In this way, the first part 1111a and the second part 1111b do not need to be directly electrically connected through a deeper via.

[0050] In some optional embodiments, continue to refer to Figure 1 and Figure 4 The display area AA includes a plurality of pixel circuits Q arranged in an array. The pixel circuit Q includes a reset module 211 . The reset signal line 1111 is electrically connected to the reset module 211 .

[0051] Figure 1 The display area AA includes a plurality of pixel circuits Q arranged in an array, the pixel circuit Q has a reset module 211, a reset signal line 1111 and a reset signal line 1112. Figure 4 The reset module 211 in the embodiment is electrically connected to transmit a reset signal to the reset module 211, which will not be described in detail here. In this embodiment, the reset module 211 may include a first reset module 2111 and a second reset module 211, the first reset module 2111 includes a fourth transistor M4, the second reset module 2112 includes a sixth transistor M6, and the reset signal line 1111 for transmitting the reset signal to the first reset module 2111 and the second reset module 211 may be the same, so that only the same reset signal is transmitted to the first reset module 2111 and the second reset module 211.

[0052] In some optional embodiments, continue to refer to Figure 4 and reference Figure 8 , Figure 8 is a schematic diagram of a planar structure of another display panel provided by the present invention, Figure 8 The reset signal line 1111 includes a first reset signal line 11111 and a second reset signal line 11112, the reset module 211 includes a first reset module 2111 and a second reset module 211, the first reset signal line 11111 is electrically connected to the first reset module 2111, the second reset signal line 11112 is electrically connected to the second reset module 211, and the first reset signal line 11111 and the second reset signal line 11112 have different potentials.

[0053] Specifically, Figure 4 The pixel circuit Q has a first reset module 2111 and a second reset module 211. The reset signals input to the first reset module 2111 and the second reset module 211 may be different, that is, the reset signal potentials transmitted to the first reset module 2111 and the second reset module 211 are different. In this case, a double reset signal line may be set, that is, a first reset signal line 11111 and a second reset signal line 11112 are set in the first frame BB1 ​​and / or the second frame BB2. The embodiment of the first reset signal line 11111 and the second reset signal line 11112 is applicable to In any of the above embodiments, of course, the first reset signal line 11111 also has a first portion 1111a and a second portion 1111b. The first portion 1111a of the first reset signal line 11111 can be switched to the second portion 1111b of the capacitor metal layer MC. The second reset signal line 11112 also has a first portion 1111a and a second portion 1111b. The first portion 1111a of the second reset signal line 11112 is switched to the second portion 1111b of the capacitor metal layer MC. In this case, the positions where the first reset signal line 11111 and the second reset signal line 11112 are switched can be different.

[0054] In this embodiment, in a direction perpendicular to the plane of the base substrate 91, the first reset signal line 11111 and the second reset signal line 11112 are at least partially overlapped with the virtual pixel P2, so that the space occupied by the first reset signal line 11111 and the second reset signal line 11112 can be saved, the first border BB1 and / or the second border BB2 can be further compressed, and a narrow border can be further achieved.

[0055] In some optional embodiments, referring to Fig. 9 , Fig. 9It is a schematic diagram of the planar structure of another display panel provided by the present invention, wherein the first type of signal line 111 is a high potential signal line 1112 or a low potential signal line 1113; the first frame BB1 ​​and / or the second frame BB2 also includes a gate drive circuit VSR located on the side of the virtual pixel P2 away from the display area AA, and the high potential signal line 1112 or the low potential signal line 1113 is electrically connected to the gate drive circuit VSR.

[0056] Understandably, Fig. 9 The figure shows bilateral driving, but it can also be unilateral driving, which is not specifically limited here. Fig. 9 The first type of signal line 111 is a high-potential signal line 1112 or a low-potential signal line 1113, and the gate drive circuit VSR is located on the side of the virtual pixel P2 away from the display area AA. The high-potential signal line 1112 is for the gate drive circuit VSR to transmit a high potential, and the low-potential signal line 1113 is for the gate drive circuit VSR to transmit a low potential. Of course, the first type of signal line 111 here cannot be set with a high-potential signal line 1112 and a low-potential signal line 1113 at the same time, because the high-potential signal line 1112 and the low-potential signal line 1113 are on the same layer, and a cross short circuit will be formed when connected to the gate drive circuit VSR. Therefore, one of the high-potential signal line 1112 or the low-potential signal line 1113 can be at least partially overlapped with the virtual pixel P2 in a direction perpendicular to the plane of the substrate 91, thereby saving the space occupied by the high-potential signal line 1112 or the low-potential signal line 1113, and further compressing the first frame BB1 ​​and / or the second frame BB2 of the display panel 100 to achieve a narrow frame.

[0057] In some optional embodiments, continue to refer to Fig. 9 The high potential signal line 1112 or the low potential signal line 1113 includes a third portion and a fourth portion 1112b, the third portion 1112a extends along the second direction Y, the fourth portion 1112b extends along the first direction X, and the fourth portion 1112b is electrically connected to the gate driving circuit VSR.

[0058] Specifically, in a direction perpendicular to the plane of the substrate 91, the high potential signal line 1112 at least partially overlaps with the virtual pixel P2, and the high potential signal line 1112 includes a third portion 1112a and a fourth portion 1112b, the third portion 1112a extends along the second direction Y, the third portion 1112a is electrically connected to the driver chip IC, and the fourth portion 1112b extends along the first direction X, so that the fourth portion 1112b is electrically connected to the gate driver circuit VSR, so that the high potential of the driver chip IC is transmitted to the gate driver circuit VSR through the third portion 1112a and the fourth portion 1112b.

[0059] Alternatively, in a direction perpendicular to the plane of the substrate 91, the low potential signal line 1113 at least partially overlaps with the virtual pixel P2, and the low potential signal line 1113 includes a third portion 1112a and a fourth portion 1112b, the third portion 1112a extends along the second direction Y, the third portion 1112a is electrically connected to the driver chip IC, and the fourth portion 1112b extends along the first direction X, so that the fourth portion 1112b is electrically connected to the gate drive circuit VSR, so that the low potential of the driver chip IC is transmitted to the gate drive circuit VSR through the third portion 1112a and the fourth portion 1112b.

[0060] In some optional embodiments, referring to Fig.10 , Fig.10 yes Fig. 9 A cross-sectional view taken along the C-C' direction, the display panel 100 further includes a first metal layer M11 located on one side of the base substrate 91, a capacitor metal layer MC located on the side of the first metal layer M11 away from the base substrate 91, a second metal layer M12 located on the side of the capacitor metal layer MC away from the base substrate 91, and a third metal layer M13 located on the side of the second metal layer M12 away from the base substrate 91, wherein the third portion 1112a and the fourth portion 1112b are both in the same layer as the third metal layer M13.

[0061] Fig.10 The cross-sectional view of the gate driving circuit VSR is only schematically shown. Of course, the gate driving circuit VSR may include multiple transistors, which are not shown here. It only schematically shows the connection relationship between the fourth part 1112b and the gate driving circuit VSR, and does not represent the actual film layer of the gate driving circuit VSR.

[0062] Combination Fig. 9 The display panel 100 includes a first metal layer M11 located on one side of the base substrate 91, the scanning line G is located on the first metal layer M11, and a capacitor metal layer MC is provided on the side of the first metal layer M11 away from the base substrate 91. The capacitor metal layer MC is used to form Figure 4 A plate of the storage capacitor Cst, the second metal layer M12 is located on the side of the capacitor metal layer MC away from the substrate 91, the source and drain of the driving transistor are located on the second metal layer M12, the third metal layer M13 is located on the side of the second metal layer M12 away from the substrate 91, and the data line D is formed on the third metal layer M13. In this embodiment, the third part 1112a and the fourth part 1112b are both in the same layer as the third metal layer M13, and the third part 1112a and the fourth part 1112b do not need to change lines to achieve electrical connection, which can reduce the complexity of the process and reduce production costs.

[0063] In some optional embodiments, referring to Fig.11 , Fig.11 is a schematic diagram of a planar structure of another display panel provided by the present invention, Fig.11 The first type of signal line 111 includes a reset signal line 1111 and a high potential signal line 1112, and the high potential signal line 1112 is located on a side of the reset signal line 1111 close to the gate drive circuit VSR; or, the first type of signal line 111 includes a reset signal line 1111 and a low potential signal line 1113, and the low potential signal line 1113 is located on a side of the reset signal line 1111 close to the gate drive circuit VSR.

[0064] Specifically, if the first type of signal line 111 is a reset signal line 1111 and a high potential signal line 1112, along the first direction X, the high potential signal line 1112 is located between the reset signal line 1111 and the gate drive circuit VSR; if the first type of signal line 111 is a reset signal line 1111 and a low potential signal line 1113, the low potential signal line 1113 is located between the reset signal line 1111 and the gate drive circuit VSR.

[0065] Combination Figure 6 and Fig.10 It can be seen that the high potential signal line 1112 is on the same layer as the third metal layer M13, and the reset signal line 1111 needs to switch lines from the third metal layer M13 to the capacitor metal layer MC. Therefore, if the high potential signal line 1112 is located between the reset signal line 1111 and the display area AA, the high potential signal line 1112 will cross-circuit with the reset signal line 1111 when it is electrically connected to the gate drive circuit VSR, affecting the drive of the gate drive circuit VSR. Therefore, the high potential signal line 1112 is located on the side of the reset signal line 1111 close to the gate drive circuit VSR, which can avoid the high potential signal line 1112 and the reset signal line 1111 from cross-circuiting. Similarly, the low-potential signal line 1113 is on the same layer as the third metal layer M13, and the reset signal line 1111 needs to switch lines from the third metal layer M13 to the capacitor metal layer MC. Therefore, if the low-potential signal line 1113 is located between the reset signal line 1111 and the display area AA, the low-potential signal line 1113 will cross-circuit with the reset signal line 1111 when it is electrically connected to the gate drive circuit VSR, affecting the drive of the gate drive circuit VSR. Therefore, the low-potential signal line 1113 is located on the side of the reset signal line 1111 close to the gate drive circuit VSR, which can avoid the low-potential signal line 1113 and the reset signal line 1111 from cross-circuiting.

[0066] In some alternative embodiments, please refer to Fig.12 , Fig.12 2 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 200 provided in this embodiment includes the display panel 100 provided in the above embodiment. Fig.12The embodiment only takes a mobile phone as an example to illustrate the display device 200. It can be understood that the display device 200 provided in the embodiment of the present invention can be a computer, a television, a car display device or other display device 200 with a display function, and the present invention does not specifically limit this. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0067] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0068] The display panel of the present invention includes virtual pixels in the first frame and / or the second frame, and also includes a first type of signal line in the first frame and / or the second frame. The virtual pixels and the first type of signal lines are elements that must be set up in the display panel. The first type of signal lines extend along the second direction and are used to transmit electrical signals. In the direction perpendicular to the plane where the substrate is located, the first type of signal lines and the virtual pixels at least partially overlap, which can save the space occupied by the first type of signal lines, further compress the first frame and / or the second frame, and achieve a narrow frame.

[0069] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: The device comprises a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises a first frame and a second frame arranged opposite to each other along a first direction, wherein the first frame and / or the second frame comprises virtual pixels, wherein the virtual pixels are arranged along a second direction, wherein the first direction intersects with the second direction, and wherein the first frame and / or the second frame further comprises a first type of signal line, wherein the first type of signal line extends along the second direction; The display panel comprises a base substrate, and in a direction perpendicular to a plane where the base substrate is located, the first type of signal line at least partially overlaps with the virtual pixel; The first type of signal line is a reset signal line, and the reset signal line includes a first portion and a second portion that are electrically connected, the first portion extends along the second direction, and the second portion extends from the first frame and / or the second frame to the display area.

2. The display panel according to claim 1, characterized in that: The display panel also includes a first metal layer located on one side of the base substrate, a capacitor metal layer located on a side of the first metal layer away from the base substrate, a second metal layer located on a side of the capacitor metal layer away from the base substrate, and a third metal layer located on a side of the second metal layer away from the base substrate, wherein the first part is in the same layer as the third metal layer, the second part is in the same layer as the capacitor metal layer, and the first part is electrically connected to the second part.

3. The display panel according to claim 2, characterized in that: The reset signal line further includes a transition connection portion, the transition connection portion is electrically connected to the first portion and the second portion respectively, and the transition connection portion is in the same layer as the second metal layer.

4. The display panel according to claim 1, characterized in that: The display area includes a plurality of pixel circuits arranged in an array, the pixel circuit includes a reset module, and the reset signal line is electrically connected to the reset module.

5. The display panel according to claim 4, characterized in that: The reset signal line includes a first reset signal line and a second reset signal line, the reset module includes a first reset module and a second reset module, the first reset signal line is electrically connected to the first reset module, the second reset signal line is electrically connected to the second reset module, and the first reset signal line and the second reset signal line have different potentials.

6. A display panel, characterized in that: The device comprises a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises a first frame and a second frame arranged opposite to each other along a first direction, wherein the first frame and / or the second frame comprises virtual pixels, wherein the virtual pixels are arranged along a second direction, wherein the first direction intersects with the second direction, and wherein the first frame and / or the second frame further comprises a first type of signal line, wherein the first type of signal line extends along the second direction; The display panel comprises a base substrate, and in a direction perpendicular to a plane where the base substrate is located, the first type of signal line at least partially overlaps with the virtual pixel; The first type of signal line is a high potential signal line or a low potential signal line; The first frame and / or the second frame further includes a gate driving circuit located at a side of the virtual pixel away from the display area, and the high potential signal line or the low potential signal line is electrically connected to the gate driving circuit.

7. The display panel according to claim 6, characterized in that: The high potential signal line or the low potential signal line includes a third portion and a fourth portion, the third portion extends along the second direction, the fourth portion extends along the first direction, and the fourth portion is electrically connected to the gate driving circuit.

8. The display panel according to claim 7, characterized in that: The display panel also includes a first metal layer located on one side of the base substrate, a capacitor metal layer located on a side of the first metal layer away from the base substrate, a second metal layer located on a side of the capacitor metal layer away from the base substrate, and a third metal layer located on a side of the second metal layer away from the base substrate, wherein the third part and the fourth part are both in the same layer as the third metal layer.

9. The display panel according to claim 6, characterized in that: The first type of signal lines are reset signal lines and high potential signal lines, and the high potential signal lines are located on a side of the reset signal lines close to the gate drive circuit; Alternatively, the first type of signal lines are reset signal lines and low potential signal lines, and the low potential signal lines are located on a side of the reset signal lines close to the gate driving circuit.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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