A method for manufacturing a solar cell and a solar cell

Abstract

The application discloses a preparation method of a solar cell and the solar cell. The method comprises the following steps: sequentially preparing a first tunneling silicon oxide layer, a first polysilicon layer, a first oxide layer and a first doping layer containing a first type of doping element from inside to outside on one side of the thickness direction of a silicon substrate; sequentially preparing a second tunneling silicon oxide layer and a second polysilicon layer from inside to outside on the other side of the thickness direction of the silicon substrate; and performing high-temperature annealing on the silicon substrate containing the second polysilicon layer and the doping layer, so as to introduce and activate a second type of doping element for the second polysilicon layer, and meanwhile, make the first type of doping element contained in the first doping layer enter the first polysilicon layer and activate the first type of doping element. According to the embodiment, the thickness of the first oxide layer and / or the concentration of the doping element in the first doping layer are adjusted, so that the doping concentration of the doping element in the first polysilicon layer and the second polysilicon layer is simultaneously ensured to be optimal through one-time annealing, and the preparation efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cell manufacturing, in particular to a preparation method of a solar cell and the solar cell. BACKGROUND

[0002] The solar cell with a passivated contact structure is a new type of high-efficiency solar cell, wherein the passivated contact structure comprises a tunneling oxide layer and a doped polysilicon layer, and the solar cell realizes selective passing of photo-generated carriers by tunneling of silicon oxide and doped polysilicon to passivate the surface of a crystalline silicon solar cell. When the passivated contact structure is used, the control of the doping concentration of the doped polysilicon layer is particularly important to the cell efficiency, and most of the existing passivated contact solar cells are single-sided passivated, and the photoelectric conversion efficiency of the cell is low and the product yield is low.

[0003] If a high-efficiency solar cell with double-sided passivation or simultaneous passivation at the positive and negative electrodes is to be prepared, the positive and negative electrodes of the solar cell need to be prepared separately, and since the doping concentration of the doped polysilicon layer required for passivation at the positive and negative electrodes of the solar cell is usually different, two annealing processes are required to prepare the doped polysilicon layer with different concentrations, which is complex in operation process and low in preparation efficiency. SUMMARY

[0004] Therefore, the embodiments of the present application provide a preparation method of a solar cell and the solar cell, a first oxide layer and a first doped layer are arranged outside a first polysilicon layer, by adjusting the thickness of the first oxide layer and / or the concentration of the doped elements in the first doped layer, the doping concentration of the first polysilicon layer can be optimized under the condition of one annealing, that is, the first type of doped elements in the first doped layer enters the first polysilicon layer through the first oxide layer at the same time as the second type of doped elements enters the second polysilicon layer, without the need for two annealing processes to prepare the positive and negative electrodes of the solar cell, which effectively improves the preparation efficiency and improves the photoelectric conversion efficiency and product yield of the passivated contact solar cell. The preparation method of the solar cell provided by the embodiments of the present application is simple in preparation process and suitable for mass production and promotion.

[0005] To solve the above technical problems, the present application provides the following technical solutions:

[0006] In a first aspect, the present application provides a method for preparing a solar cell, comprising: step 1, sequentially preparing a first tunneling silicon oxide layer, a first polysilicon layer, a first oxide layer and a first doped layer containing a first type of doping element from inside to outside on one side of the thickness direction of a silicon substrate; step 2, sequentially preparing a second tunneling silicon oxide layer and a second polysilicon layer from inside to outside on the other side of the thickness direction of the silicon substrate; step 3, performing high-temperature annealing on the silicon substrate containing the second polysilicon layer and the first doped layer, so as to introduce and activate a second type of doping element for the second polysilicon layer, and at the same time, make the first type of doping element contained in the first doped layer enter the first polysilicon layer and activate the first type of doping element.

[0007] In a second aspect, the present application provides another method for preparing a solar cell, comprising: step 1, sequentially preparing a third tunneling silicon oxide layer, a third polysilicon layer, a second oxide layer, a second doped layer containing a second type of doping element and an external oxide layer from inside to outside on the other side of the thickness direction of a silicon substrate; step 2, removing the second oxide layer, the second doped layer containing the second type of doping element and the external oxide layer in part of the region for the side on which the external oxide layer is prepared, so as to form adjacent third and fourth regions on the other side of the thickness direction of the silicon substrate, the outer layer of the third region being the external oxide layer, and the outer layer of the fourth region being the third polysilicon layer; step 3, performing high-temperature annealing on the silicon substrate containing the third and fourth regions, so as to introduce and activate the second type of doping element for the third polysilicon layer corresponding to the third region, forming a third doped region; at the same time, making the exogenous first type of doping element enter the third polysilicon layer corresponding to the fourth region and activate the first type of doping element, forming a fourth doped region.

[0008] In a third aspect, the present application provides a method for preparing a solar cell, comprising: step 1, sequentially preparing a fourth tunneling silicon oxide layer, a fourth polysilicon layer, a third oxide layer and a third doped layer containing a first type of doping element from inside to outside on one side of the thickness direction of a silicon substrate; step 2, for the side on which the third oxide layer is prepared, shielding part of the third doped layer by using a patterned shielding layer, and removing the fourth tunneling silicon oxide layer, the fourth polysilicon layer and the third oxide layer in the unshielded part of the region to form a fifth region and a sixth region arranged at intervals; wherein the fifth region is a region containing the third doped layer, and the sixth region is a region in which the silicon substrate is exposed; step 3, forming a first type of front surface field in the sixth region, wherein the first type is the same as the doping type of the silicon substrate; step 4, preparing a silicon glass layer containing a second type of doping element on the other side of the silicon substrate, and performing high-temperature annealing on the silicon substrate containing the fifth region, the sixth region and the silicon glass layer to introduce and activate the first type of doping element into the fourth polysilicon layer of the fifth region to form a fourth doped polysilicon layer, and simultaneously form a back emitter containing the first type of doping element on the other side of the silicon substrate.

[0009] In a fourth aspect, the present application provides a solar cell, comprising: a silicon substrate; a first tunneling silicon oxide layer and a first doped polysilicon layer containing a first type of doping element sequentially arranged from inside to outside on one side of the thickness direction of the silicon substrate; a second tunneling silicon oxide layer and a second doped polysilicon layer containing a second type of doping element sequentially arranged from inside to outside on the other side of the thickness direction of the silicon substrate.

[0010] In a fifth aspect, the present application provides another solar cell, comprising: a silicon substrate; a third tunneling silicon oxide layer arranged on the other side of the silicon substrate and a third doped polysilicon layer laminated on the third tunneling silicon oxide layer; wherein the third doped polysilicon layer is divided into a third doped region containing a second type of doping element and a fourth doped region containing a first type of doping element.

[0011] In a sixth aspect, the present application provides still another solar cell, comprising: a silicon substrate; wherein one side of the thickness direction of the silicon substrate is divided into a fifth region containing a fourth doped polysilicon layer and a sixth region containing a front surface field of a first type of doping element; wherein the first type is the same as the type of the silicon substrate; a fourth tunneling silicon oxide layer and a fourth doped polysilicon layer laminated on the fourth tunneling silicon oxide layer are arranged in the fifth region; and a back emitter is arranged on the other side of the thickness direction of the silicon substrate.

[0012] The technical scheme of the first aspect of the above application has the following advantages or beneficial effects: the first oxide layer and the first doped layer are arranged outside the first polysilicon layer, and by adjusting the thickness of the first oxide layer and / or the concentration of the doped elements in the first doped layer and / or the concentration of the doped elements contained in the first polysilicon layer, the doped concentration of the first polysilicon layer can be ensured to be optimal under one-time annealing. Meanwhile, the doped concentration of the second polysilicon layer does not affect the doped concentration of the first polysilicon layer, which makes the doped concentrations of the first polysilicon layer and the second polysilicon layer be able to be adjusted independently. Moreover, the preparation of the first polysilicon layer and the second polysilicon layer of the solar cell can be realized by one-time high-temperature annealing, without the need for two-time annealing, thereby avoiding the mutual influence of the doped concentrations of the first polysilicon layer and the second polysilicon layer, which effectively improves the preparation efficiency and improves the photoelectric conversion efficiency and product yield of the passivated contact solar cell. Meanwhile, the preparation method of the solar cell provided in the embodiment of the application has simple preparation process and is suitable for mass production and promotion.

[0013] Meanwhile, taking the optimal doped concentration of the second polysilicon layer as a reference, the doped concentration of the first polysilicon layer is adjusted, so that the optimal doped concentration of the doped elements in the first polysilicon layer and the second polysilicon layer can be ensured, that is, the first type of doped elements in the first doped layer enters the first polysilicon layer through the first oxide layer, and the second type of doped elements enters the second polysilicon layer, BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings are used to better understand the application and do not constitute an improper limitation on the application. Among them:

[0015] FIG. 1(A) is a flowchart of a preparation method of a solar cell according to an embodiment of the application;

[0016] FIG. 1(B) is a flowchart of the preparation method after step S103 according to an embodiment of the application;

[0017] Figure 2 FIG. 2 is a schematic diagram of a cross-sectional structure of a solar cell according to an embodiment of the application;

[0018] Figure 3 FIG. 3 is a schematic diagram of a cross-sectional structure of a solar cell obtained after step S101 according to an embodiment of the application;

[0019] Figure 4 FIG. 4 is a schematic diagram of a cross-sectional structure of a solar cell after the first type of doped elements and the second type of doped elements enter the first polysilicon layer and the second polysilicon layer, respectively, according to an embodiment of the application;

[0020] Figure 5is a cross-sectional structure schematic diagram of a battery substrate with a polycrystalline silicon doped layer according to the embodiment of the present application after step S104;

[0021] Figure 6 is a cross-sectional structure schematic diagram of a solar cell with a passivation anti-reflection layer 600 according to the embodiment of the present application after step S105;

[0022] Figure 7 is a flowchart of another method for preparing a solar cell according to the embodiment of the present application;

[0023] Figure 8 is a cross-sectional structure schematic diagram of a bifacial passivation contact solar cell with a local passivation structure on the front side according to the embodiment of the present application;

[0024] Figure 9 is a cross-sectional structure schematic diagram of a solar cell with a first region and a second region according to the embodiment of the present application after step S701;

[0025] Figure 10 is a cross-sectional structure schematic diagram of a solar cell with a second region in a textured structure according to the embodiment of the present application after step S702;

[0026] Figure 11 is a cross-sectional structure schematic diagram of a battery substrate with an emitter on the front side according to the embodiment of the present application after step S703;

[0027] Figure 12 is a cross-sectional structure schematic diagram of a bifacial passivation contact solar cell with a local passivation contact on the front side and a second tunneling silicon oxide layer and a second polycrystalline silicon layer according to the embodiment of the present application;

[0028] Figure 13 is a cross-sectional structure schematic diagram of a solar cell with a local passivation structure on the front side according to the embodiment of the present application after step S104;

[0029] Figure 14 is a cross-sectional structure schematic diagram of a solar cell with a local passivation structure on the front side according to the embodiment of the present application after step S106;

[0030] FIG. 15(A) is a flowchart of another method for preparing a solar cell according to the embodiment of the present application;

[0031] FIG. 15(B) is a flowchart of the preparation method after step S1503 according to the embodiment of the present application;

[0032] Figure 16 is a cross-sectional structure schematic diagram of an IBC solar cell according to the embodiment of the present application;

[0033] Figure 17 is a cross-sectional structure schematic diagram of the solar cell after the step S1500 according to the embodiment of the present application, wherein the upper surface of one side of the silicon substrate in the thickness direction is subjected to alkali texturing;

[0034] Figure 18 is a cross-sectional structure schematic diagram of the solar cell with the first type of front surface field after the step S1500 according to the embodiment of the present application;

[0035] Figure 19 is a cross-sectional structure schematic diagram of the solar cell after the step S1501 according to the embodiment of the present application;

[0036] Figure 20 is a cross-sectional structure schematic diagram of the solar cell after the step S1502 according to the embodiment of the present application;

[0037] Figure 21 is a cross-sectional structure schematic diagram of the solar cell after the step S1503 according to the embodiment of the present application, wherein the third polysilicon layer includes the third region with the first type of doping element and the fourth region with the second type of doping element;

[0038] Figure 22 is a cross-sectional structure schematic diagram of the solar cell after the step S1504 according to the embodiment of the present application;

[0039] Figure 23 is a cross-sectional structure schematic diagram of the solar cell after the step S1505 according to the embodiment of the present application;

[0040] Figure 24 is a cross-sectional structure schematic diagram of the solar cell after the step S1506 according to the embodiment of the present application;

[0041] FIG. 25(A) is a schematic diagram of main steps of another method for preparing a solar cell according to an embodiment of the present application;

[0042] FIG. 25(B) is a schematic diagram of main steps of the method for preparing a solar cell according to the embodiment of the present application after the step S2504;

[0043] Figure 26 is a cross-sectional structure schematic diagram of a single-side passivated back junction solar cell structure according to the embodiment of the present application;

[0044] Figure 27 is a cross-sectional structure schematic diagram of the solar cell after the step S2501 according to the embodiment of the present application;

[0045] Figure 28 is a cross-sectional structure schematic diagram of the solar cell after the step S2502 according to the embodiment of the present application;

[0046] Figure 29 is a cross-sectional structure diagram of a solar cell obtained after step S2502-1 according to an embodiment of the present application;

[0047] Figure 30 is a cross-sectional structure diagram of a solar cell with a first type of front surface field obtained after step S2503 according to an embodiment of the present application;

[0048] Figure 31 is a cross-sectional structure diagram of a diffused solar cell obtained after annealing according to step S2504 of an embodiment of the present application;

[0049] Figure 32 is a cross-sectional structure diagram of a back junction cell substrate obtained after step S2505 according to an embodiment of the present application;

[0050] Figure 33 is a cross-sectional structure diagram of a back contact cell substrate with a passivation anti-reflection layer obtained after step S2506 according to an embodiment of the present application;

[0051] Figure 34 is a structure diagram of a second metal electrode according to an embodiment of the present application;

[0052] Figure 35 is a structure diagram of a second metal electrode and a third metal electrode in a longitudinal direction according to an embodiment of the present application;

[0053] Figure 36 is a structure diagram of a second metal electrode and a third metal electrode in a planar direction according to an embodiment of the present application.

[0054] Reference signs are as follows:

[0055] 100 - silicon substrate; 101 - first region; 102 - second region; 1021 - front side emitter; 1022 - back side emitter; 110 - front surface field; 103 - third region; 1031 - third doped region; 104 - fourth region; 1041 - fourth doped region; 105 - fifth region; 106 - sixth region; 201 - first tunneling silicon oxide layer; 202 - second tunneling silicon oxide layer; 203 - third tunneling silicon oxide layer; 204 - fourth tunneling silicon oxide layer; 301 - first polysilicon layer; 301' - first doped polysilicon layer; 302 - second polysilicon layer; 302' - second doped polysilicon layer; 303 - third polysilicon layer; 303' - third doped polysilicon layer; 401 - first oxide layer; 402 - second oxide layer; 403 - third oxide layer; 501 - first doped layer; 502 - second doped layer; 503 - third doped layer; 600 - passivation anti-reflection layer; 601 - electrode grid line; 6011 - first metal electrode; 6012 - second metal electrode; 6013 - third metal electrode; 700 - external oxide layer. Detailed Implementation

[0056] A solar cell is a thin-film photovoltaic semiconductor that directly generates electricity using sunlight. Also known as a "solar chip" or "photovoltaic cell," it can instantly output voltage and generate current when a circuit is established, provided it receives sufficient illumination. In physics, this is called solar photovoltaic (PV). To facilitate and clearly describe the fabrication method and the solar cell of this invention, exemplary embodiments of the invention are described below with reference to the accompanying drawings. These embodiments include various details to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0057] In existing crystalline silicon solar cell structures, passivated contact solar cells, as a novel type of high-efficiency solar cell, passivate the surface of the silicon substrate by tunneling silicon oxide layer and doped polycrystalline silicon layer. This enables selective passage of photogenerated carriers in the fabricated solar cell. This ensures that majority carriers can pass through the tunneling silicon oxide layer unimpeded into the doped polycrystalline silicon layer and be collected. At the same time, minority carriers have a low recombination rate at the interface between the tunneling silicon oxide layer and crystalline silicon and cannot pass through the tunneling silicon oxide layer to reach the doped polycrystalline silicon layer. This achieves one-dimensional collection of photogenerated carriers, reducing the probability of minority carrier recombination while increasing the probability of majority carrier collection. To maximize the photoelectric conversion efficiency and product yield of solar cells by using passivated contact structures on both sides, current technology requires the fabrication of passivated contact structures on both sides of the crystalline silicon. This involves boron doping and phosphorus doping on both sides of the crystalline silicon (poly) respectively. However, it is difficult to achieve ideal doping concentrations for both n+poly and p+poly at the same time, resulting in low photoelectric conversion efficiency and product yield of double-sided passivated contact solar cells. This limits the development and application of double-sided passivated contact structure solar cells.

[0058] It should be noted that when the passivation contact structure is adopted, the doping concentration of the doped polysilicon layer is particularly important for the cell efficiency. If the doping concentration of the doped polysilicon is too high: ①diffusion source atoms are prone to penetrate the tunneling oxide layer, in which case the integrity of the tunneling oxide layer is destroyed, and the ability of the tunneling oxide layer passivation contact structure to select carriers will be weakened; ②the doped source atoms are prone to penetrate the silicon oxide layer into the silicon substrate to cause an increase in recombination; and if the doping concentration of the doped polysilicon is too low, the doping concentration reaching the tunneling oxide layer is light, it is difficult to form the field passivation effect of the high-low structure, and meanwhile the contact resistance of the metal contact area is large and is not conducive to the export of external circuit electrons. Therefore, the embodiment of the present application provides a preparation method which can ensure that the doping concentration of the doped polysilicon layer of the positive and negative electrodes of a solar cell reaches the optimum. Whether it is a solar cell with a double-sided passivation contact structure of the positive and negative electrodes on both sides of the silicon substrate or a solar cell with a back contact passivation structure of the positive and negative electrodes on one side of the silicon substrate, the doping concentration of the doped polysilicon layer of the positive and negative electrodes of the cell can be ensured to be optimal through a simple preparation process of one-time annealing.

[0059] In an embodiment of the present application, as shown in FIG. 1(A), the embodiment provides a preparation method of a solar cell, which can include the following steps:

[0060] Step S101, a first tunneling silicon oxide layer 201, a first polysilicon layer 301, a first oxide layer 401 and a first doped layer 501 containing a first type of doped element are prepared from inside to outside in the thickness direction of the silicon substrate 100 on one side;

[0061] Step S102, a second tunneling silicon oxide layer 202 and a second polysilicon layer 302 are prepared from inside to outside on the other side of the silicon substrate 100 in the thickness direction;

[0062] Step S103, high-temperature annealing is performed on the silicon substrate containing the second polysilicon layer 302 and the first doped layer 501 to introduce and activate the second type of doped element for the second polysilicon layer 302, and to make the first type of doped element contained in the first doped layer 501 enter the first polysilicon layer 301 and activate the first type of doped element.

[0063] In an alternative embodiment, in order to obtain a complete cell structure, as shown in FIG. 1(B), after step S103, it further includes:

[0064] Step S104, the first oxide layer 401 and the first doped layer 501 are removed by using an acidic etching solution to form a cell substrate with a first doped polysilicon layer 301' and a second doped polysilicon layer 302' on both sides;

[0065] Step S105, forming a passivation anti-reflection layer 600 and an electrode grid line 601 on the outside of the first doped polysilicon layer 301' and the second doped polysilicon layer 302' of the battery substrate in sequence;

[0066] Step S106, connecting the corresponding first doped polysilicon layer 301' and the second doped polysilicon layer 302' through the passivation anti-reflection layer by sintering the electrode grid line 601 on both sides.

[0067] Wherein, the one side and the other side of the thickness direction of the silicon substrate 100 generally refer to the two opposite main surfaces of the silicon substrate 100, and after the silicon substrate is made into a solar cell, the one side and the other side can correspond to the front surface and the back surface of the solar cell. Exemplarily, if the one side of the thickness direction of the silicon substrate 100 corresponds to the front surface of the solar cell, then the other side of the thickness direction of the silicon substrate 100 corresponds to the back surface of the solar cell.

[0068] It should be noted that the embodiment of the present application is to set the first oxide layer 401 and the first doped layer 501 containing the first type of doped elements in the preparation process, control the thickness of the first oxide layer 401 and the concentration of the first type of doped elements, so that under the condition of ensuring that the second polysilicon layer can realize the optimal annealing condition of the doped concentration, the first type of doped elements in the first doped layer 501 can also enter the first polysilicon layer with the optimal concentration, that is, the optimal concentration of different types of doped elements in the polysilicon doped layer (the first doped polysilicon layer 301' and the second doped polysilicon layer 302') on both sides of the thickness direction of the silicon substrate 100 is ensured in one annealing process. After the annealing process of step 3, the first oxide layer 401 and the first doped layer 501 are removed through step S104, which not only ensures the simple battery structure, but also effectively improves the photoelectric conversion efficiency and product yield of the battery. In an optional embodiment, the thickness of the first oxide layer 401 is 1nm-2nm, for example, 1nm, 1.2nm, 1.4nm, 1.8nm or 2nm, by selecting the appropriate thickness and the concentration of the doped elements in the first doped layer, the independent curve of the thickness of the first oxide layer 401 and the doped concentration of the doped polysilicon layer can be obtained to ensure that the passivation contact reaches the ideal state.

[0069] In an alternative embodiment, the second type of doping elements doped in the second polysilicon layer can be introduced into the second polysilicon layer by means of liquid source, solid source or gaseous source. Specifically, before the annealing step in step S103, a silicon glass layer containing the second type of doping elements is prepared on the outside of the second polysilicon layer 302, which can be specifically a layer of amorphous silicon film containing the second type of doping elements deposited on the surface of the second polysilicon layer 302 by means of magnetron sputtering or vacuum evaporation. In this way, during the annealing process, the second type of doping elements in the amorphous silicon film layer can enter the second polysilicon layer to form a second doped polysilicon layer 302'. That is, the second type of doping elements is introduced into and activated in the second polysilicon layer 302 in step S103, which includes: by high-temperature annealing, the second type of doping elements contained in the silicon glass layer enter the second polysilicon layer 302 and activate the second type of doping elements. In a further alternative embodiment, the annealing temperature of high-temperature annealing in step S103 is 700-1000°C, preferably 700-900°C, for example 700°C, 750°C, 800°C, 850°C or 900°C.

[0070] For the preparation method of the first tunneling silicon oxide layer 201, the first polysilicon layer 301, the first oxide layer 401 and the first doped layer 501 containing the first type of doping elements in step S101, in an alternative embodiment, any one of the deposition methods of LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapour Deposition) and ALD (atomic layer deposition) or a combination of multiple deposition methods can be used to prepare them in sequence. For the second tunneling silicon oxide layer 202 and the second polysilicon layer 302 in step 2, similarly, any one of the deposition methods of LPCVD, PECVD, PVD and ALD or a combination of multiple deposition methods can be used to prepare them in sequence.

[0071] The material of the first tunneling silicon oxide layer 201 can be silicon oxide, and the thickness can be 0.5-3nm. The material of the second tunneling silicon oxide layer 202 is silicon oxide, and the thickness is 0.5-3nm. By reasonably controlling the thickness of the first tunneling silicon oxide layer 201 and the second tunneling silicon oxide layer 202, the collection probability of majority carriers can be increased, and thus the photoelectric conversion efficiency of the battery can be improved.

[0072] In an alternative embodiment of the present application, the material of the first oxide layer 401 is also silicon oxide. Since in the actual preparation process, after step S101, the first oxide layer 401 and the first doped layer 501 formed by plating on the other side of the silicon substrate in the thickness direction, an alternative embodiment before step S102 can also include: step S101-1, using an acid etching solution to remove the first oxide layer 401 and the first doped layer 501 including the first type of doping elements formed by plating on the other side of the silicon substrate 100 in the thickness direction. The acid solution is a common etching solution, which can include the following mass fractions of each component: 30-40 parts by mass of nitric acid, 30-40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water. For example, the nitric acid can be 30 parts by mass, 32 parts by mass, 34 parts by mass, 36 parts by mass, 38 parts by mass and 40 parts by mass, etc., and the hydrofluoric acid can be 30 parts by mass, 32 parts by mass, 34 parts by mass, 36 parts by mass, 38 parts by mass and 40 parts by mass, etc. By etching with an acid solution, the first oxide layer 401 and the first doped layer 501 formed by plating on the other side of the silicon substrate in the thickness direction can be effectively removed, thereby ensuring the preparation of the second tunneling silicon oxide layer 202 and the second polysilicon layer 302 on the surface of the silicon substrate on the other side in the thickness direction. It should be noted that the acid solution does not have etching effect on the silicon substrate 100, so it will not damage the silicon substrate 100 itself.

[0073] In a further alternative embodiment, before step S101, the two sides of the silicon substrate 100 in the thickness direction can also be textured. The texturing process is the usual alkali texturing, and the reaction principle is that in a low-concentration alkali solution, the surface of the silicon substrate undergoes anisotropic etching to produce a dense pyramid-shaped pyramid structure, i.e. the pyramid structure of the textured surface. By texturing the silicon substrate, the mechanical damage layer on the surface of the single crystal silicon substrate can be removed, and the pyramid structure formed can reduce the light reflectivity. In an alternative embodiment, the specific process of texturing includes: placing the silicon substrate 100 in an etching solution at 80-85°C for 20-25min, using the anisotropy of the etching solution to obtain the textured surface. The etching solution includes an alkali solution and an additive; further, the alkali solution can include any one of sodium hydroxide, potassium hydroxide, sodium silicate and sodium phosphate, and the additive can include any one of isopropyl alcohol, ammonium thiosulfate and hydrazine hydrate. The specific concentration of the alkali solution and the additive can be set according to the actual process requirements, which is not limited in the present application.

[0074] It should be noted that the battery substrate with the polycrystalline silicon doped layer on both sides in step S104 is a battery substrate with a first doped polycrystalline silicon layer 301' doped with a first type of doping element on the front side and a second doped polycrystalline silicon layer 302' doped with a second type of doping element on the back side. Further, the passivation and anti-reflection layer 600 provided in step S104 is provided on the outer side of the first doped polycrystalline silicon layer 301' doped with the first type of doping element and the second doped polycrystalline silicon layer 302' doped with the second type of doping element, respectively, and functions to passivate defects on the surface and in the bulk of the polycrystalline silicon wafer and reduce reflection of incident light. The specific material can be at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride. The material of the passivation and anti-reflection layer 600 on the front side and the material of the passivation and anti-reflection layer 600 on the back side can be the same or different, which is not limited in the present application, i.e., the material of the passivation and anti-reflection layer 600 provided on the outer side of the first doped polycrystalline silicon layer 301' and the material of the passivation and anti-reflection layer 600 provided on the outer side of the second doped polycrystalline silicon layer 302' can be the same or different.

[0075] For different types of silicon substrates 100, the doping elements in the first doped layer 501 are also different. In an optional embodiment, for the case that the silicon substrate 100 is N-type silicon, the first doped layer 501 is a BSG layer, i.e., a boron-doped layer, and the doping element is boron; for the case that the silicon substrate 100 is P-type silicon, the first doped layer 501 is a PSG layer, i.e., a phosphorus-doped layer, and the doping element is phosphorus.

[0076] Figure 2 A cross-sectional structure schematic diagram of a solar cell provided by an embodiment of the present application is shown, Figures 3 to 6 Cross-sectional structure diagrams of solar cells obtained after different steps in an embodiment of the present application are shown respectively. Among them, Figure 2 The relative position relationship of the silicon substrate 100, the first tunneling silicon oxide layer 201, the first polycrystalline silicon layer 301, the passivation and anti-reflection layer 600 provided on the one side of the silicon substrate 100 from inside to outside, and the second tunneling silicon oxide layer 202, the second polycrystalline silicon layer 302 and the passivation and anti-reflection layer 600 provided on the other side of the silicon substrate 100 from inside to outside is shown, and the setting position of the electrode grid line 601 is also shown; Figure 3 The relative position relationship of the first tunneling silicon oxide layer 201, the first polycrystalline silicon layer 301, the first oxide layer 401 and the first doped layer 501 containing the first type of doping element and the silicon substrate 100 after step S101 is shown; Figure 4 A cross-sectional structure schematic diagram after the first type of doping element and the second type of doping element enter the first polycrystalline silicon layer 301 and the second polycrystalline silicon layer 302 respectively after annealing in step S103 is shown; Figure 5A cross-sectional structure diagram of the battery substrate with the first oxide layer 401 and the first doped polysilicon layer 501 removed is shown in step S104. Figure 6 A cross-sectional structure diagram of the solar cell with the passivation anti-reflective layer 600 is shown after step S105.

[0077] As shown in the drawings, Figures 2 to 6 The solar cell provided by the present application comprises a silicon substrate 100, a first tunneling silicon oxide layer 201 and a first doped polysilicon layer 301' containing a first type of doping element arranged in sequence from inside to outside on one side of the silicon substrate 100 in the thickness direction, and a second tunneling silicon oxide layer 202 and a second doped polysilicon layer 302' arranged in sequence from inside to outside on the other side of the silicon substrate 100 in the thickness direction. In a further optional embodiment, the solar cell provided by the present application further comprises a passivation anti-reflective layer 600 arranged on the first doped polysilicon layer 301' and the second doped polysilicon layer 302', and an electrode grid line 601 passing through the passivation anti-reflective layer 600 and connected to the corresponding doped polysilicon layer.

[0078] In the structure of the double-sided passivation contact solar cell, for the passivation contact structure on the front side, in order to better improve the selective passage of photo-generated carriers, in an optional embodiment, a local passivation contact structure can be adopted, that is, the passivation contact structure is not used in the non-metal electrode contact area (the area not in contact with the fine grid), and the passivation contact structure is used in the metal electrode contact area (the area in contact with the fine grid). Compared with the traditional full-area passivation contact structure design, the application of the local passivation contact structure to the front side of the cell can avoid the problem of greater light absorption caused by the use of a doped polysilicon layer in the non-metal electrode area of the front side of the cell, thereby increasing the amount of incident light entering the crystalline silicon substrate and further increasing the amount of photo-generated carriers in the crystalline silicon substrate. Therefore, in an optional embodiment, after step S101-1 and before step S102, as shown in the drawings, Figure 7 A step S701 of shielding part of the first doped layer 501 with a patterned shielding layer and removing the first tunneling silicon oxide layer 201, the first polysilicon layer 301, the first oxide layer 401 and the first doped layer 501 in the unshielded area by laser stripping to form first areas 101 and second areas 102 arranged at intervals can be further included, wherein the first areas 101 are areas including the first doped layer 501, and the second areas 102 are areas exposing the silicon substrate 100.

[0079] The patterned shielding layer corresponds to the arrangement of the fine grid, the shielded part is the area in contact with the fine grid, and the unshielded area is the area not in contact with the fine grid. Through the shielding of the shielding layer, the silicon substrate 100 in the area not in contact with the fine grid can be exposed. In an optional embodiment, the first tunneling silicon oxide layer 201, the first polysilicon layer 301, the first oxide layer 401, and the first doped layer 501 in the unshielded area can be removed by a laser stripping method.

[0080] In a further optional embodiment, as shown in FIG. 1C, after step S701 and before step S102, the method further comprises: Figure 7

[0081] Step S702, alkali texturing is performed on the front surface of the second area 102 to form a textured structure on the upper surface of the second area 102, and the alkali solution in the alkali texturing is used to remove the first tunneling silicon oxide layer 201 and the first polysilicon layer 301 formed by plating on the other side of the silicon substrate 100 in the thickness direction;

[0082] Step S703, for the case that the silicon substrate 100 is N-type silicon / P-type silicon, boron diffusion / phosphorus diffusion is performed on the textured structure on the front surface of the second area 102 to form a cell substrate with an emitter 1021 on one side in the thickness direction;

[0083] Step S704, wet etching is performed on the other side in the thickness direction and the two sides in the length direction of the cell substrate with the front emitter 1021 to remove the PN junction on the side of the silicon substrate 100 and the diffusion doped layer formed on the other side in the thickness direction.

[0084] Since the material of the first tunneling silicon oxide layer 201 is silicon oxide and the material of the first polysilicon layer 301 is silicon oxide, the first tunneling silicon oxide layer 201 and the first polysilicon layer 301 formed by plating on the other side of the silicon substrate 100 in the thickness direction can be removed by the alkali solution in the etching solution during the alkali texturing. In an optional embodiment, the wet etching in step S704 can further include etching the back surface and the side surface of the cell substrate with the front emitter 1021 on the front surface by using an etching solution for 0.5-10 min; wherein the etching solution includes 20-40 parts by mass of nitric acid, 30-60 parts by mass of hydrofluoric acid, and 20-30 parts by mass of deionized water.

[0085] ​In the case of adopting the local passivation contact structure on the front side, after step S704, the same as the solar cell preparation process of the double-side passivation contact structure, steps S102 to S106 are continuously executed; wherein the process of removing the first oxide layer 401 and the first doped layer 501 by using the acidic etching solution in step S104 can be understood as removing the first oxide layer 401 and the first doped layer 501 of the first region 101 by using the acidic etching solution, and forming the battery substrate with the double-side specific polycrystalline silicon doped layer.

[0086] In an optional embodiment, the sintering temperature in step S106 above can be set to 100-500℃, and through the sintering process, the final battery structure is integrally formed. In another optional embodiment, the electrode grid line 601 is obtained by printing the metal paste, wherein the metal paste is any one or a combination of aluminum paste, silver-aluminum paste, low-temperature aluminum paste, low-temperature silver-aluminum paste, and low-temperature silver paste. The sintering temperature of the low-temperature aluminum paste, the low-temperature silver-aluminum paste, and the low-temperature silver paste is 100-500℃; the sintering temperature of the aluminum paste and the silver-aluminum paste is greater than 500℃. Generally, the low-temperature metal paste of the positive electrode and the negative electrode can be the same or different, and can be self-defined according to the actual demand and the photoelectric conversion efficiency, which is not limited in the present application.

[0087] Figure 8 A cross-sectional structure schematic diagram of the double-side passivation contact solar cell with the local passivation structure on the front side provided by the embodiment of the present application is shown, Figures 9 to 14 The cross-sectional structure diagrams of the solar cells obtained after different steps of the embodiment of the present application are shown respectively. Among them, Figure 9 A cross-sectional structure schematic diagram of the solar cell with the first region 101 and the second region 102 formed after step S701 is shown; Figure 10 A cross-sectional structure schematic diagram of the solar cell with the second region 102 as a textured structure obtained after step S702 is shown; Figure 11 A cross-sectional structure schematic diagram of the battery substrate with the emitter 1021 on the front side formed after step S703 is shown; Figure 12 A cross-sectional structure schematic diagram of the double-side passivation contact solar cell with the local passivation contact on the front side with the first doped polycrystalline silicon layer 301' doped with the first type of doped elements, the second tunneling silicon oxide layer 202, and the second doped polycrystalline silicon layer 302' after the annealing process of step S103 is shown; Figure 13 A cross-sectional structure schematic diagram of the solar cell with the local passivation structure on the front side after step S104 is shown; Figure 14 A cross-sectional structure schematic diagram of the solar cell with the local passivation structure on the front side after step S106 is shown. Through the above Figures 9 to 14The preparation process of the double-sided passivation contact solar cell with the front surface having a local passivation structure and the positional relationship between the various structures can be directly observed, thereby facilitating the understanding and description of the preparation method.

[0088] As shown in Figures 8 to 14 The solar cell provided by the application comprises a silicon base 100, a first tunneling silicon oxide layer 201 and a first polycrystalline silicon layer 301 containing a first type of doping element arranged in sequence from inside to outside on one side of the silicon base 100 in the thickness direction, a second tunneling silicon oxide layer 202 and a second polycrystalline silicon layer 302 arranged in sequence from inside to outside on the other side of the silicon base 100 in the thickness direction, a passivation anti-reflection layer 600 arranged on the first polycrystalline silicon layer 301 and the second polycrystalline silicon layer 302, and an electrode grid line 601 passing through the passivation anti-reflection layer 600 and connected to the corresponding doped polycrystalline silicon layer, wherein the first tunneling silicon oxide layer 201 and the first polycrystalline silicon layer 301 are arranged in correspondence on a local area on one side of the silicon base 100, and the local area arranged with the first tunneling silicon oxide layer 201 and the first polycrystalline silicon layer 301 is arranged in a spaced manner.

[0089] As can be seen, the preparation method of the double-sided passivation contact solar cell provided by the embodiment of the application sets the first oxide layer and the first doping layer on the outside of the first polycrystalline silicon layer, and by adjusting the thickness of the first oxide layer or the concentration of the doping elements in the first doping layer, the doping concentration of the doping elements in the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer can be simultaneously optimized under the condition of one-time annealing, that is, the first type of doping elements in the first doping layer enters the first polycrystalline silicon layer through the first oxide layer at the same time as the second type of doping elements enters the second polycrystalline silicon layer, without the need for two-time annealing to prepare the positive and negative electrodes of the solar cell, thereby effectively improving the preparation efficiency and the photoelectric conversion efficiency and product yield of the passivation contact solar cell.

[0090] Further, the preparation method of the double-sided passivation contact solar cell with front surface local passivation provided by the embodiment of the application further improves the passivation structure on the front surface on the basis of the double-sided passivation contact, and the passivation contact structure on the front surface locally avoids the problem of large light absorption caused by the use of the doped polycrystalline silicon layer in the non-metal electrode area of the front surface of the cell, thereby increasing the amount of incident light entering the crystalline silicon substrate and further increasing the amount of photo-generated carriers in the crystalline silicon substrate. Meanwhile, the preparation method of the solar cell provided by the embodiment of the application has simple preparation process and is suitable for mass production and popularization.

[0091] In another embodiment of the application, as shown in FIG. 15(A), the embodiment provides a preparation method of a solar cell, which can comprise the following steps:

[0092] Step S1501, sequentially prepare a third tunneling silicon oxide layer 203, a third polysilicon layer 303, a second oxide layer 402, a second doping layer 502 containing a second type of doping element, and an outer oxide layer 700 from inside to outside on the other side of the thickness direction of the silicon substrate 100;

[0093] Step S1502, for the side prepared with the outer oxide layer 700, remove part of the second oxide layer 402, the second doping layer 502 with the second type of doping element, and the outer oxide layer 700 to form adjacent third and fourth regions 103 and 104 on the other side of the thickness direction of the silicon substrate 100, the outer layer of the third region is the outer oxide layer 700, and the outer layer of the fourth region is the third polysilicon layer 303;

[0094] Step S1503, high-temperature anneal the silicon substrate containing the third and fourth regions 103 and 104 to introduce and activate the second type of doping element for the third polysilicon layer 303 corresponding to the third region 103, forming a third doped region 1031; at the same time, the exogenous first type of doping element enters the third polysilicon layer 303 corresponding to the fourth region 104 and activates the first type of doping element, forming a fourth doped region 1041.

[0095] In step S1503, the annealing process causes the third polysilicon layer 303 to change, so that the third and fourth regions 103 and 104 become the third and fourth doped regions 1301 and 1401.

[0096] In further optional embodiments, in order to obtain a complete battery structure, before step S1501, there is also step S1500: forming a first type of front surface field 110 on the side of the thickness direction of the silicon substrate 100, wherein the first type is the same as the doping type of the silicon substrate 100.

[0097] In further optional embodiments, after step S1503, as shown in Figure 15(B), there is also:

[0098] Step S1504, using an acidic etching solution to remove the second oxide layer 402, the second doping layer 502, and the outer oxide layer 700 corresponding to the third doped region 1031 to form a back contact battery substrate;

[0099] Step S1505, sequentially form a passivation anti-reflection layer 600 on both sides of the back contact battery substrate, and set an electrode grid line 601 on the side of the third doped polysilicon layer 303' containing the third doped region 1031 and the fourth doped region 1041;

[0100] Step S1506, by sintering, the electrode grid line 601 corresponding to the third doped region 103' and the fourth doped region 104' respectively on the other side of the thickness direction of the silicon substrate 100 is connected to the third doped polysilicon layer 303' on the other side of the thickness direction through the passivation anti-reflective layer 600 provided on the other side of the thickness direction of the silicon substrate 100.

[0101] It should be noted that the embodiment provides a back contact passivated contact solar cell structure with positive and negative electrodes on one side of the silicon substrate 100, i.e. a single-sided passivated solar cell structure. Since the positive and negative electrodes are on the same side of the silicon substrate 100, the preparation of different electrode corresponding regions is also different, i.e. in step S1502, the third region 103 and the fourth region 104 correspond to the positive and negative electrodes of the silicon substrate 100 respectively. At the same time, in order to make the doping elements of the positive and negative electrodes different and not affect each other during the preparation process, the external oxide layer 700 is provided in step S1501 to prevent the second type of doping element from entering the third region 103 during the process of entering the fourth region 104.

[0102] In an alternative embodiment, any one of LPCVD, PECVD, PVD and ALD or a combination of multiple deposition methods can be used in step S1502 to sequentially prepare the third tunneling silicon oxide layer 203, the third polysilicon layer 303, the second oxide layer 402, the second doped layer 502 containing the second type of doping element and the external oxide layer 700.

[0103] It should be noted that the purpose of high temperature annealing in step S1503 is to make the first doping type element enter the third polysilicon layer 303 corresponding to the third region 103, and the second doping type element enter the third polysilicon layer 303 corresponding to the fourth region 104, so as to form the third doped polysilicon layer 303' with different doping elements for the positive and negative electrodes. In an alternative embodiment, a source-carrying thermal diffusion process can also be used to achieve this effect, such as liquid source diffusion of phosphorus oxychloride, chain diffusion after spraying phosphoric acid aqueous solution, chain diffusion after screen printing phosphorus paste, etc. The phosphorus element to be doped is dispersed in the air in the form of a liquid source, and as the air temperature changes, it enters the fourth region 104. In another embodiment, a solid source can also be used to introduce the second doping type element into the third polysilicon layer 303 corresponding to the fourth region 104, i.e. after step S1502 and before step S1503, it further includes: step S1502-1: a silicon glass layer containing the first type of doping element is prepared outside the third polysilicon layer 303 outside the fourth region. Through high temperature annealing, the first type of doping element in the silicon glass layer containing the first type of doping element can also enter the fourth region 104 of the third polysilicon layer 303 and activate the first type of doping element.

[0104] In an optional embodiment of step S1502, the second oxide layer 402, the second doped layer 502 and the external oxide layer 700 in the partial region can be removed by any one of laser stripping, slurry etching and coating wet film photoresist or a combination of multiple ways. Specifically, the process of laser stripping is to remove the oxide layer by bombarding the surface with laser emitted by a laser; the process of slurry etching is to print etching slurry in the partial region and remove the second oxide layer 402, the second doped layer 502 and the external oxide layer 700 in the partial region by etching; the process of coating wet film photoresist is to coat wet film photoresist on the side provided with the external oxide layer 600, then perform baking, exposure and development treatment on the wet film photoresist to form solidified wet film photoresist, remove the solidified wet film photoresist in the partial region, then etch the part without solidified wet film photoresist by using hydrofluoric acid solution to remove the second oxide layer 402, the second doped layer 502 and the external oxide layer 700, and finally remove the remaining solidified wet film photoresist.

[0105] In an optional embodiment, the material of the second oxide layer 402 is silicon oxide, and the thickness of the third tunneling silicon oxide layer 203 is 0.5-3 nm. By reasonably controlling the thickness of the third tunneling silicon oxide layer 203, the collection probability of majority carriers can be increased, and thus the photoelectric conversion efficiency of the battery can be improved. Meanwhile, in a further optional embodiment, the passivation anti-reflection layer 600 includes at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride and silicon oxynitride. The materials of the passivation anti-reflection layers 600 arranged on the two sides of the back contact battery substrate can be the same or different, which is not limited in the present application.

[0106] It should be noted that the doping element in the second doped layer 502 is also different for different types of silicon substrate 100. For the case that the silicon substrate 100 is N-type silicon, the second doped layer 502 is a BSG layer, i.e. a boron doped layer, and the doping element is boron; for the case that the silicon substrate 100 is P-type silicon, the second doped layer 502 is a PSG layer, i.e. a phosphorus doped layer, and the doping element is phosphorus.

[0107] In an optional embodiment, before step S1500, the upper surface of one side of the silicon substrate 100 in the thickness direction can also be subjected to alkali texturing. The side subjected to texturing is the same side as the first type of front surface field 110, and the reaction principle of alkali texturing is that in a low-concentration alkali solution, the surface of the silicon substrate undergoes anisotropic etching to form a dense pyramid-shaped pyramid structure, that is, a pyramid structure of the textured surface. By texturing the silicon substrate, the mechanical damage layer on the surface of the single crystal silicon substrate can be removed, and the pyramid structure formed can reduce light reflectivity. In an optional embodiment, the specific process of texturing includes: placing the silicon substrate 100 in an etching solution at 80-85°C for 20-25 min to obtain a textured surface by using the anisotropy of the etching solution to the silicon substrate. The etching solution includes an alkali solution and an additive. Further, the alkali solution can include any one of sodium hydroxide, potassium hydroxide, sodium silicate, and sodium phosphate, and the additive can include any one of isopropyl alcohol, ammonium thiosulfate, and hydrazine hydrate. The specific addition concentration of the alkali solution and the additive can be set according to actual process requirements, which is not limited in the present application.

[0108] Figures 16 to 24 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, wherein, Figure 16 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given; Figure 17 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given;

[0109] Figure 18 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given; Figure 19 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given; Figure 20 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given;

[0110] Figure 21 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given; Figure 22 The cross-sectional structure of the IBC solar cell provided by the embodiment of the present application is shown, and the relative position relationship of the silicon substrate 100, the first type of front surface field 110, the third tunneling silicon oxide layer 203, the third region 103 containing the first type of doping elements and the fourth region 104 containing the second type of doping elements in the third polycrystalline silicon layer 303, the passivation anti-reflection layer 600, and the electrode grid line 601 is given; Figure 23A cross-sectional structure schematic diagram of the solar cell after step S1505 is shown; Figure 24 A cross-sectional structure schematic diagram of the solar cell after step S1506 is shown. Through the above Figures 16 to 24 It can be intuitively seen that the preparation process of the single-side passivation contact back contact solar cell and the positional relationship between various structures, facilitating the understanding and explanation of the preparation method.

[0111] As shown in Figures 16 to 24 The single-side passivation contact back contact solar cell provided by the application includes: a silicon substrate 100; a third tunneling silicon oxide layer 203 arranged on the other side of the silicon substrate 100 and a third doped polysilicon layer 303' stacked on the third tunneling silicon oxide layer 203. The third doped polysilicon layer is divided into a third doped region 1031 containing a second type of doped element and a fourth doped region 1041 containing a first type of doped element. In a further optional embodiment, the single-side passivation contact back contact solar cell provided by the application further includes: a first type of front surface field 110 arranged on one side of the silicon substrate 100; a passivation anti-reflection layer 600 arranged on the first type of front surface field 110 and the third doped polysilicon layer 303'; an electrode grid line 601 passing through the passivation anti-reflection layer 600 on the third doped region 1031 and connected to the third doped region 1031; and an electrode grid line 601 passing through the passivation anti-reflection layer 600 on the fourth doped region 1041 and connected to the fourth doped region 1041.

[0112] As can be seen from the above, the preparation method of the single-side passivation contact back contact solar cell provided by the embodiment of the application sets a second oxide layer, a second doped layer containing a second type of doped element and an external oxide layer outside the third polysilicon layer. By adjusting the thickness of the second oxide layer or the concentration of the doped element in the second doped layer, the optimal doping concentration of the third region doped element of the third polysilicon layer can be ensured under the condition of one-time annealing. At the same time, by setting the external oxide layer, different types of doped elements can be doped in the third region and the fourth region of the third polysilicon layer, and different doping concentrations of the two different regions of doped elements can be realized. Without two-time annealing for the preparation of the positive and negative electrodes of the solar cell, the preparation efficiency is effectively improved, and the photoelectric conversion efficiency and product yield of the passivation contact solar cell are improved.

[0113] In another embodiment of the application, as shown in FIG. 25(A), the embodiment provides a preparation method of a solar cell, which can include the following steps:

[0114] Step S2501, sequentially preparing a fourth tunneling silicon oxide layer 204, a fourth polysilicon layer 304, a third oxide layer 403 and a third doped layer 503 containing a first type of doping element from inside to outside in the thickness direction of the silicon substrate 100;

[0115] Step S2502, for the side prepared with the third oxide layer 403, using a patterned shielding layer to shield part of the third doped layer 503, so as to remove the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304 and the third oxide layer 403 in the unshielded area, to form a fifth region 105 and a sixth region 106 arranged at intervals; wherein the fifth region 105 is a region containing the third doped layer 503, and the sixth region 106 is a region exposing the silicon substrate 100;

[0116] Step S2503, forming a first type of front surface field 110 in the sixth region 106, wherein the first type is the same as the doping type of the silicon substrate 100;

[0117] Step S2504, preparing a silicon glass layer containing a second type of doping element on the other side of the silicon substrate 100, and performing high-temperature annealing on the silicon substrate containing the fifth region 105, the sixth region 106 and the silicon glass layer, so as to introduce and activate the first type of doping element into the fourth polysilicon layer 304 of the fifth region 105, to form a fourth doped polysilicon layer 304', and at the same time form a back emitter 1022 containing the second type of doping element on the other side of the silicon substrate 100.

[0118] In order to obtain a complete battery structure, in an alternative embodiment, as shown in FIG. 25(B), the preparation method further comprises:

[0119] Step S2505, removing the third oxide layer 403 and the third doped layer 503 containing the first type of doping element by using an acidic etching solution, to form a back junction battery substrate;

[0120] Step S2506, sequentially forming a passivation anti-reflection layer 600 and an electrode grid line 601 on both sides of the back junction battery substrate;

[0121] Step S2507, connecting the electrode grid line 601 provided on one side of the silicon substrate 100 through the corresponding passivation anti-reflection layer to the corresponding fourth doped polysilicon layer 304' by sintering; and connecting the electrode grid line 601 provided on the other side of the silicon substrate 100 through the corresponding passivation anti-reflection layer to the back emitter 1022.

[0122] It should be noted that in the solar cell, the surface field and the emitter are usually arranged oppositely, i.e. the front surface field 110 is arranged on the front surface of the silicon substrate 100, and then the emitter needs to be arranged on the back surface of the silicon substrate 100. Compared with the third tunneling silicon oxide layer 203, the third polysilicon layer 303, the second oxide layer 402 and the second doped layer 502 arranged on the side of the back surface emitter in the previous embodiment, the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304, the third oxide layer 403 and the third doped layer 503 including the second type of doped elements are arranged on the side of the first type of front surface field 110 arranged on the front surface in the above embodiment. It is illustrated that in the case of arranging the surface field and the emitter at will, the embodiments of the present application can realize the effect of simultaneously ensuring the optimal doping concentration of the doped elements in different polysilicon layers under the condition of one-time annealing, effectively improving the preparation efficiency and the photoelectric conversion efficiency.

[0123] In an optional embodiment, after step S2502, further comprising: step S2502-1, texturing is performed on the exposed surface of the silicon substrate 100 in the sixth region 106 to form a textured structure in the sixth region 106, and the fourth tunneling silicon oxide layer 204 and the fourth polysilicon layer 304 generated on the other side of the thickness direction of the silicon substrate 100 during the texturing process are removed.

[0124] Wherein, for different types of silicon substrate 100, the type of back surface emitter is also different, therefore step 2504 further comprises: for the case that the silicon substrate 100 is N-type silicon, boron diffusion is performed on the other side of the silicon substrate 100; for the case that the silicon substrate 100 is P-type silicon, phosphorus diffusion is performed on the other side of the silicon substrate 100, to form a cell substrate with a back surface emitter 1022 on the back surface. In addition, in an optional embodiment, the annealing temperature of high-temperature annealing in step 2504 is 700-1000°C, preferably 700-900°C, for example 700°C, 750°C, 800°C, 850°C or 900°C.

[0125] For the electrode grid line 601, in an alternative embodiment of the present application, it comprises: a first metal electrode 6011 disposed outside the fourth doped polysilicon layer 304' obtained through step S2504, a second metal electrode 6012 disposed in a discontinuous local point contact manner on the other side of the silicon substrate 100, and a third metal electrode 6013; wherein the second metal electrode 6012 corresponds to the fifth region 105, and the third metal electrode 6013 corresponds to the sixth region 106; the third metal electrode 6013 connects the adjacent second metal electrodes 6012 into one body. In actual application, it can be understood that the first metal electrode 6011 is disposed on the front side of the silicon substrate 100 and corresponds to the fifth region. The second metal electrode 6012 and the third metal electrode 6013 are disposed on the back side of the silicon substrate 100, wherein the second metal electrode 6012 is disposed opposite to the fifth region on the front side, and the third metal electrode 6013 is disposed opposite to the sixth region 106 on the front side. By disposing the second metal electrode 6012 in a discontinuous local point contact manner, a local back field can be formed on the other side of the silicon substrate 100, so as to reduce the resistance caused by the contact and improve the electric conversion efficiency.

[0126] In an alternative embodiment, any one of the deposition methods of LPCVD, PECVD, PVD and ALD or a combination of multiple deposition methods is adopted in step S2501 to sequentially prepare the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304, the third oxide layer 403 and the third doped layer 503 containing the second type of doped elements.

[0127] It can be understood that the phenomenon of around-plating occurs in the preparation of the battery. Therefore, in order to achieve the same effect, i.e. to remove the interference caused by around-plating, the embodiment of the present application further comprises the following step S2501-1 after step S2501 and before step S2502: removing the third oxide layer 403 and the third doped layer 503 containing the second type of doped elements generated on the other side of the silicon substrate 100 in the thickness direction by using an acidic etching solution. The etching time is 0.5 min to 10 min, and preferably 1 min to 2 min. The etching solution comprises 20 to 40 parts by mass of nitric acid, 30 to 60 parts by mass of hydrofluoric acid and 20 to 30 parts by mass of deionized water. At the same time, in order to reduce the light reflectivity, texturing can be performed on both sides of the silicon substrate, i.e. the following step can also be included after step S2501 and before step S2502: texturing the other side of the silicon substrate in the thickness direction with the third doped layer 503, and forming a textured structure on the side opposite to the third oxide layer 403.

[0128] In an alternative embodiment, after step S2504 and before step S2505, there can be further included: wet etching the other side of the silicon substrate including the first type of front surface field 110 to remove the doped diffusion layer formed on the other side of the length direction of the silicon substrate 100 and the thickness direction.

[0129] In an alternative embodiment, the sintering temperature in the above-mentioned embodiments can be set to 100-500°C, so that the final battery structure is integrally formed through the sintering process. In a further alternative embodiment, the electrode grid line 601 is obtained by printing metal paste, wherein the metal paste is any one or a combination of aluminum paste, silver-aluminum paste, low-temperature aluminum paste, low-temperature silver-aluminum paste, and low-temperature silver paste. The sintering temperature of the low-temperature aluminum paste, the low-temperature silver-aluminum paste, and the low-temperature silver paste is 100-500°C; the sintering temperature of the aluminum paste and the silver-aluminum paste is greater than 500°C. Generally, the low-temperature metal paste of the positive and negative electrodes of the battery can be the same or different, and can be customized according to the actual needs and the photoelectric conversion efficiency, which is not limited in the present application.

[0130] Figures 26 to 36 The cross-sectional structure of the single-side passivated back junction solar cell structure provided by the present application is shown, wherein, Figure 26 The cross-sectional structure of the single-side passivated back junction solar cell structure is shown, and the relative position relationship between the fourth tunneling silicon oxide layer 204 and the fourth polysilicon layer 304 arranged from inside to outside on one side of the thickness direction of the silicon substrate 100 and the electrode grid line 601 is given, and the relative position relationship between the first type of front surface field 110, the passivation and anti-reflection layer 600, the back emitter 1022, and the silicon substrate 100 is also given; Figure 27 The cross-sectional structure of the solar cell obtained after step S2501 is shown, and the relative position relationship between the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304, the third oxide layer 403, the third doped layer 503, and the silicon substrate 100 is given; Figure 28 The cross-sectional structure of the solar cell obtained after step S2502 is shown; Figure 29 The cross-sectional structure of the solar cell obtained after step S2502-1 is shown; Figure 30 The cross-sectional structure of the solar cell with the first type of front surface field 110 obtained after step S2503 is shown; Figure 31 The cross-sectional structure of the solar cell obtained after annealing in step S2504 is shown; Figure 32 The cross-sectional structure of the back contact battery substrate obtained after step S2505 is shown; Figure 33 The cross-sectional structure of the back contact battery substrate with the passivation and anti-reflection layer obtained after step S2506 is shown;Figures 34 to 36 The specific structure of the electrode grid line is shown, and the relative position relationship between the first metal electrode, the second metal electrode and the third metal electrode is given. Figures 26 to 36 The preparation process of the single-side passivated back junction solar cell structure and the position relationship between the structures can be directly observed, which facilitates the understanding and explanation of the preparation method.

[0131] As shown in the figure, the single-side passivated back junction solar cell structure provided by the present application comprises a silicon substrate 100. Figures 26 to 35 The fifth region 105 is provided with a fourth tunneling silicon oxide layer 204 and a fourth doped polysilicon layer 304' stacked on the fourth tunneling silicon oxide layer 204.

[0132] In a further optional embodiment, the single-side passivated back junction solar cell structure provided by the present application further comprises a passivation and anti-reflection layer 600 arranged outside the fifth region 105 and the sixth region 106 and outside the back surface emitter 1022; an electrode grid line 601 connected to the fourth polysilicon layer 304 through the passivation and anti-reflection layer 600 on the fifth region 105; and an electrode grid line 601 connected to the back surface emitter 1022 through the passivation and anti-reflection layer 600 arranged on the other side of the thickness direction of the silicon substrate 100.

[0133] As can be seen from the above, the preparation method of the single-side passivated back junction solar cell structure provided by the embodiments of the present application arranges a third oxide layer and a third doped layer comprising a second type of doped elements outside the fourth polysilicon layer, and by adjusting the thickness of the third oxide layer or the concentration of the doped elements in the third doped layer, the back surface emitter and the local front field with optimal concentration can be formed at one time under the condition of annealing, so as to ensure that the local passivation contact front field structure reaches an ideal state, effectively improve the preparation efficiency, and at the same time improve the photoelectric conversion efficiency of the passivation contact solar cell and the product yield.

[0134] The embodiments of the present application also provide a photovoltaic module, which can comprise a cell piece made of the solar cell of the above-mentioned embodiments.

[0135] The embodiments of the present application also provide a power station, which can comprise the photovoltaic module provided by the above-mentioned embodiments.

[0136] The above-mentioned preparation method will be described in detail in the following several specific embodiments.

[0137] Embodiment 1

[0138] A method for manufacturing a solar cell, comprising:

[0139] Step 1, soaking the N-type silicon substrate in an etching solution at 80℃ for 20 min, using the etching solution to anisotropically etch the silicon substrate, and alkali-texturing the two sides of the silicon substrate in the thickness direction; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0140] Step 2, sequentially preparing a first tunneling silicon oxide layer, a first polysilicon layer, a first oxide layer, and a BSG layer containing boron elements on one side of the N-type silicon substrate in the thickness direction by PVD; wherein the thickness of the first tunneling silicon oxide layer is 2 nm;

[0141] Step 3, soaking the other side of the N-type silicon substrate in the thickness direction in an acid etching solution to remove the first oxide layer and the BSG layer containing boron elements formed by plating on the other side of the silicon substrate in the thickness direction; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid, and 30 parts by mass of deionized water;

[0142] Step 4, sequentially preparing a second tunneling silicon oxide layer, a second polysilicon layer, and an amorphous silicon thin film layer containing phosphorus elements on the other side of the N-type silicon substrate obtained in step 3 in the thickness direction by PVD;

[0143] Step 5, high-temperature annealing the silicon substrate containing the second polysilicon layer and the BSG layer obtained in step 4 to introduce and activate phosphorus elements for the second polysilicon layer, obtaining a p+ second doped polysilicon layer, and to make the boron elements contained in the BSG layer enter the first polysilicon layer and activate the boron elements, forming an n+ first doped polysilicon layer; wherein the annealing temperature is 800℃;

[0144] Step 6, removing the first oxide layer and the BSG layer on one side of the silicon substrate in the thickness direction by using an acid etching solution, forming a cell substrate having the first doped polysilicon layer and the second doped polysilicon layer on the two sides, respectively; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid, and 30 parts by mass of deionized water;

[0145] Step 7, sequentially preparing a passivation anti-reflection layer on the outside of the first doped polysilicon layer and the second doped polysilicon layer of the cell substrate obtained in step 6 by PVD; wherein the material of the passivation anti-reflection layer is aluminum oxide;

[0146] Step 8, coating a metal paste with a low-temperature silver paste on the two sides of the silicon substrate with the passivation anti-reflection layer obtained in step 7 in the thickness direction, respectively;

[0147] Step 9, sintering the silicon substrate coated with low-temperature silver paste at a sintering temperature of 200℃, so that the electrode grid lines formed by sintering the low-temperature silver paste on both sides of the silicon substrate are connected with the corresponding first doped polycrystalline layer and the second doped polycrystalline silicon layer through the corresponding passivation anti-reflection layer, to obtain a solar cell.

[0148] Embodiment 2

[0149] A method for manufacturing a solar cell, comprising:

[0150] Step 1, soaking the P-type silicon substrate in an etching solution at 80℃ for 20 min, using the anisotropy of the etching solution to alkali-texture both sides of the silicon substrate in the thickness direction; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0151] Step 2, sequentially preparing a first tunneling silicon oxide layer, a first polycrystalline silicon layer, a first oxide layer and a PSG layer containing phosphorus on one side of the P-type silicon substrate in the thickness direction by PVD; wherein the thickness of the first tunneling silicon oxide layer is 1 nm;

[0152] Step 3, soaking the other side of the P-type silicon substrate in the thickness direction in an acid etching solution to remove the first oxide layer and the PSG layer containing phosphorus formed by plating on the other side of the silicon substrate in the thickness direction; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0153] Step 4, sequentially preparing a second tunneling silicon oxide layer, a second polycrystalline silicon layer and an amorphous silicon thin film layer containing boron on the other side of the P-type silicon substrate obtained in step 3 in the thickness direction by PVD;

[0154] Step 5, high-temperature annealing the silicon substrate containing the second polycrystalline silicon layer and the PSG layer obtained in step 4 to introduce and activate boron in the second polycrystalline silicon layer, to obtain an n+ second doped polycrystalline silicon layer; and at the same time, causing the phosphorus contained in the PSG layer to enter the first polycrystalline silicon layer and activate the phosphorus, to form a p+ first doped polycrystalline silicon layer; wherein the annealing temperature is 800℃;

[0155] Step 6, removing the first oxide layer and the PSG layer on one side of the silicon substrate in the thickness direction by using an acid etching solution, to form a cell substrate having the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on both sides respectively; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0156] Step 7, sequentially preparing a passivation anti-reflection layer on the outside of the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer of the cell substrate obtained in step 6 by PVD; wherein the material of the passivation anti-reflection layer is aluminum oxide.

[0157] Step 8, coating the silicon substrate with passivation anti-reflective layer obtained in step 7 with metal paste of low-temperature silver paste on both sides in the thickness direction of the silicon substrate;

[0158] Step 9, sintering the silicon substrate coated with low-temperature silver paste at a sintering temperature of 200℃, so that the electrode grid lines formed by sintering the low-temperature silver paste on both sides of the silicon substrate are connected with the corresponding first doped polysilicon layer and the second doped polysilicon layer through the corresponding passivation anti-reflective layer, to obtain a solar cell.

[0159] Example 3

[0160] A method for manufacturing a solar cell, comprising:

[0161] Step 1, using PECVD method to prepare a first tunneling silicon oxide layer, a first polysilicon layer, a first oxide layer and a BSG layer containing boron elements on one side of the N-type silicon substrate in the thickness direction from inside to outside; wherein the thickness of the first tunneling silicon oxide layer is 1 nm;

[0162] Step 2, using etching solution etching method to remove the first oxide layer and the BSG layer containing boron elements generated by plating on the other side of the silicon substrate in the thickness direction; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0163] Step 3, using a patterned shielding layer to shield part of the BSG layer containing boron elements, and using laser stripping method to remove the first tunneling silicon oxide layer, the first polysilicon layer, the first oxide layer and the BSG layer containing boron elements in the unshielded area, to form a first region and a second region arranged at intervals, wherein the first region is a region containing the BSG layer, and the second region is a region exposing the silicon substrate to the outside;

[0164] Step 4, placing the N-type silicon substrate obtained in step 3 into an etching solution at 80℃ for 20min, using the etching solution to etch the silicon substrate anisotropically, to perform alkaline texturing on the front surface of the second region to form a textured structure on the upper surface of the second region, and at the same time, using the alkali solution in the alkaline texturing to remove the first tunneling silicon oxide layer and the first polysilicon layer generated by plating on the other side of the silicon substrate in the thickness direction; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0165] Step 5, performing boron diffusion on the textured structure on the front surface of the second region to form a cell substrate with a p+ emitter on one side in the thickness direction;

[0166] Step 6, wet etching is performed on the other side of the battery substrate with a front emitter in the thickness direction to remove the PN junction on the side of the silicon substrate and the borosilicate glass formed on the other side in the thickness direction; the etching solution used in the wet etching includes 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid, and 30 parts by mass of deionized water;

[0167] Step 7, a second tunneling silicon oxide layer, a second polysilicon layer, and an amorphous silicon thin film layer containing phosphorus elements are sequentially prepared on the other side of the N-type silicon substrate in the thickness direction by PVD;

[0168] Step 8, high-temperature annealing is performed on the silicon substrate obtained in step 7 to introduce and activate phosphorus elements for the second polysilicon layer, thereby obtaining an n+ second doped polysilicon layer; at the same time, boron elements contained in the BSG layer enter the first polysilicon layer and activate the boron elements, thereby forming a p+ first doped polysilicon layer; wherein the annealing temperature is 800°C;

[0169] Step 9, the first oxide layer and the BSG layer in the first region are removed by using an acidic etching solution, thereby forming a battery substrate with a first doped polysilicon layer and a second doped polysilicon layer on both sides; wherein the etching solution includes 40 parts by mass of nitric acid, 30 parts by mass of hydrofluoric acid, and 30 parts by mass of deionized water;

[0170] Step 10, a passivation anti-reflection layer is sequentially prepared on the outer side of the first doped polysilicon layer and the second doped polysilicon layer of the battery substrate obtained in step 9 by PVD; wherein the material of the passivation anti-reflection layer is aluminum oxide;

[0171] Step 11, metal paste with low-temperature silver paste is coated on both sides of the silicon substrate with the passivation anti-reflection layer obtained in step 10 in the thickness direction;

[0172] Step 12, sintering is performed on the silicon substrate coated with low-temperature silver paste at a sintering temperature of 200°C, so that the electrode grid lines formed by sintering the low-temperature silver paste on both sides of the silicon substrate are connected to the corresponding first doped polysilicon layer and second doped polysilicon layer through the corresponding passivation anti-reflection layer, thereby obtaining a solar cell.

[0173] Example 4

[0174] A method for manufacturing a solar cell, comprising:

[0175] Step 1, a P-type silicon substrate is immersed in an etching solution at 80°C for 20 min, and anisotropy of the etching solution is used to alkali-texture both sides of the silicon substrate in the thickness direction; wherein the etching solution includes 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0176] Step 2, a first tunneling silicon oxide layer, a first polysilicon layer, a first oxide layer and a PSG layer containing phosphorus are prepared in turn from inside to outside on the textured structure of the P-type silicon substrate obtained in step 1 on the side in the thickness direction; wherein the thickness of the first tunneling silicon oxide layer is 1 nm;

[0177] Step 3, the first oxide layer and the PSG layer containing phosphorus generated by plating on the other side of the silicon substrate in the thickness direction are removed by etching solution etching; wherein the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0178] Step 4, a part of the PSG layer containing phosphorus is shielded by using a patterned shielding layer, and the first tunneling silicon oxide layer, the first polysilicon layer, the first oxide layer and the PSG layer containing phosphorus in the unshielded area are removed by using laser stripping to form a first region and a second region arranged at intervals, wherein the first region is a region containing the PSG layer, and the second region is a region exposing the silicon substrate;

[0179] Step 5, the P-type silicon substrate obtained in step 4 is soaked in an etching solution at 80°C for 20 min, and the alkali texturing is performed on the front surface of the second region by using the anisotropy of the etching solution to form a textured structure on the upper surface of the second region, and the first tunneling silicon oxide layer and the first polysilicon layer generated by plating on the other side of the silicon substrate in the thickness direction are removed by using the alkali solution in the alkali texturing; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0180] Step 6, phosphorus diffusion is performed on the textured structure on the front surface of the second region to form a cell substrate with an n+ emitter on the side in the thickness direction;

[0181] Step 7, wet etching treatment is performed on the other side of the cell substrate with the front emitter in the thickness direction to remove the PN junction and borosilicate glass formed on the side surface and the other side of the silicon substrate in the thickness direction; the etching solution used in the wet etching treatment comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0182] Step 8, a second tunneling silicon oxide layer, a second polysilicon layer and an amorphous silicon thin film layer containing boron are prepared in turn from inside to outside on the other side of the P-type silicon substrate in the thickness direction by using the PVD method;

[0183] Step 9, high-temperature annealing is performed on the silicon substrate obtained in step 8 to introduce and activate boron elements for the second polysilicon layer to obtain a p+ second doped polysilicon layer; at the same time, the phosphorus elements contained in the PSG layer enter the first polysilicon layer and activate the phosphorus elements to form an n+ first doped polysilicon layer; wherein the annealing temperature is 800°C;

[0184] Step 10, removing the first oxide layer and the PSG layer of the first region by using an acid etching solution to form a cell substrate with the first doped polysilicon layer and the second doped polysilicon layer on two sides respectively; wherein the etching solution comprises 40 parts by mass of nitric acid, 30 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0185] Step 11, sequentially preparing a passivation anti-reflection layer outside the first doped polysilicon layer and the second doped polysilicon layer of the cell substrate obtained in step 9 by using a PVD method; wherein the material of the passivation anti-reflection layer is aluminum oxide;

[0186] Step 12, coating a metal paste with low-temperature silver paste on both sides of the silicon substrate with the passivation anti-reflection layer obtained in step 11 in the thickness direction respectively;

[0187] Step 13, sintering the silicon substrate coated with the low-temperature silver paste at a sintering temperature of 200°C, so that the electrode grid lines formed by sintering the low-temperature silver paste on both sides of the silicon substrate pass through the corresponding passivation anti-reflection layer and are connected to the corresponding first doped polysilicon layer and the second doped polysilicon layer, to obtain a solar cell.

[0188] Example 5

[0189] A method for manufacturing a solar cell, comprising:

[0190] Step 1, placing an N-type silicon substrate into an etching solution at 80°C for 20 min, using the etching solution to perform anisotropic etching on one side of the silicon substrate in the thickness direction; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0191] Step 2, forming an n+ front surface field on the textured side of the silicon substrate;

[0192] Step 3, sequentially preparing, from the inside to the outside, a third tunneling silicon oxide layer, a third polysilicon layer, a second oxide layer, a BSG layer containing boron elements and an outer oxide layer on the other side of the silicon substrate in the thickness direction; wherein the thickness of the third tunneling silicon oxide layer is 3 nm;

[0193] Step 4, removing the second oxide layer, the BSG and the outer oxide layer in a partial region on the side with the outer oxide layer by using a laser lift-off method to form adjacent third and fourth regions on the back side of the silicon substrate in the thickness direction, wherein the outer layer of the third region is the outer oxide layer and the outer layer of the fourth region is the third polysilicon layer;

[0194] Step 5, a thermal diffusion process with phosphorus source is performed on the silicon substrate containing the third region and the fourth region, so as to introduce and activate phosphorus element into the third polysilicon layer corresponding to the fourth region, and form a fourth doped region; meanwhile, boron element contained in the BSG layer enters the third polysilicon layer corresponding to the third region and is activated, and a third doped region is formed;

[0195] Step 6, the second oxide layer, the second doped layer and the external oxide layer corresponding to the third doped region in step 5 are removed by using an etching solution, and a back contact cell substrate is formed; wherein the etching solution comprises 40 parts by mass of nitric acid, 30 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0196] Step 7, a passivation anti-reflection layer is sequentially formed on both sides of the back contact cell substrate by using a PVD method;

[0197] Step 8, the third doped region and the fourth doped region of the third doped polysilicon layer in step 7 are respectively coated with a metal paste whose material is low-temperature silver paste;

[0198] Step 9, the silicon substrate coated with the metal paste is sintered at a sintering temperature of 200℃, so that the electrode grid lines formed by sintering the third doped region and the fourth doped region on the other side (back surface) of the back contact cell substrate are connected to the third doped polysilicon layer on the other side (back surface) through the passivation anti-reflection layer arranged on the other side (back surface) of the silicon substrate, and a solar cell is obtained.

[0199] Example 6

[0200] A manufacturing method of a solar cell, comprising:

[0201] Step 1, a P-type silicon substrate is immersed in an etching solution at 80℃ for 20 min, and anisotropy of the etching solution is used to alkali-texture one side of the silicon substrate in the thickness direction; wherein the etching solution comprises 10 parts by mass of sodium hydroxide and 1 part by mass of isopropyl alcohol;

[0202] Step 2, a p+ front surface field is formed on one side of the textured surface of the silicon substrate;

[0203] Step 3, a third tunneling silicon oxide layer, a third polysilicon layer, a second oxide layer, a PSG layer containing phosphorus element and an external oxide layer are sequentially prepared from inside to outside on the other side of the silicon substrate in the thickness direction; wherein the thickness of the third tunneling silicon oxide layer is 3 nm;

[0204] Step 4, for the preparation of the side with the outer oxide layer, a portion of the second oxide layer, the BSG and the outer oxide layer are removed by laser stripping method to form adjacent third and fourth regions on the back side of the silicon substrate in the thickness direction, wherein the outer layer of the third region is the outer oxide layer, and the outer layer of the fourth region is the third polysilicon layer;

[0205] Step 5, a BSG layer containing boron element is prepared on the outer side of the fourth region by PVD method;

[0206] Step 6, the silicon substrate containing the outer oxide layer in the third region and the BSG layer in the fourth region obtained in step 5 is subjected to high temperature annealing to introduce and activate boron element for the third polysilicon layer corresponding to the fourth region, thereby forming a fourth doped region; at the same time, the phosphorus element contained in the PSG layer enters the third polysilicon layer corresponding to the third region and activates the phosphorus element, thereby forming a third doped region; wherein the annealing temperature is 800°C;

[0207] Step 7, the second oxide layer, the second doped layer and the outer oxide layer corresponding to the third doped region in step 6 are removed by etching solution to form a back contact cell substrate; wherein the etching solution comprises 40 parts by mass of nitric acid, 30 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0208] Step 8, a passivation anti-reflection layer is sequentially formed on both sides of the back contact cell substrate by PVD method;

[0209] Step 9, the third doped region and the fourth doped region of the third doped polysilicon layer in step 8 are respectively coated with a metal paste whose material is low-temperature silver paste;

[0210] Step 10, the silicon substrate coated with the metal paste is sintered at a sintering temperature of 200°C, so that the passivation anti-reflection layer on the other side (back surface) of the back contact cell substrate corresponding to the third doped region and the fourth doped region is connected with the third doped polysilicon layer on the other side after high temperature annealing, thereby obtaining a solar cell.

[0211] Example 7

[0212] A method for manufacturing a solar cell, comprising:

[0213] Step 1, a fourth tunneling silicon oxide layer, a fourth polysilicon layer, a third oxide layer and a PSG layer containing phosphorus element are sequentially deposited from inside to outside on the front side of the N-type silicon substrate in the thickness direction by PECVD method; wherein the thickness of the fourth tunneling silicon oxide layer is 3 nm;

[0214] Step 2, the third oxide layer and the PSG layer containing phosphorus element generated by the plating on the back side of the silicon substrate in the thickness direction are removed by etching with an etching solution; the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0215] Step 3, the fourth tunneling silicon oxide layer, the fourth polysilicon layer and the third oxide layer in the partial region are removed by laser stripping with the patterned shielding layer shielding part of the PSG layer on the side with the third oxide layer, so as to form the fifth region and the sixth region arranged at intervals; the fifth region is the region containing the PSG layer, and the sixth region is the region exposing the N-type silicon substrate;

[0216] Step 4, the N-type silicon substrate obtained in step 3 is soaked in the etching solution at 80°C for 20 min, and the alkali texturing is performed on the front surface of the sixth region by using the anisotropy of the silicon substrate to the etching solution, so as to form the textured structure on the upper surface of the sixth region, and the fourth tunneling silicon oxide layer and the fourth polysilicon layer generated by the plating on the back side of the silicon substrate in the thickness direction are removed by using the alkali solution in the alkali texturing;

[0217] Step 5, the n+ front surface field is formed by phosphorus diffusion on the front side of the N-type silicon substrate in the thickness direction;

[0218] Step 6, the wet etching treatment is performed on the back side of the silicon substrate obtained in step 5 to remove the n / n+ high-low junction on the side surface of the silicon substrate and the n / n+ high-low junction on the back surface; the etching solution used in the wet etching treatment comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0219] Step 7, the silicon glass layer containing the doping element B is prepared on the other side of the silicon substrate obtained in step 6;

[0220] Step 8, the high-temperature annealing is performed on the silicon substrate containing the fifth region, the sixth region and the silicon glass layer, so as to introduce and activate the doping element P in the fourth polysilicon layer of the fifth region to form the fourth doped polysilicon layer, and the doping element B is formed on the other side of the silicon substrate to form the p+ emitter;

[0221] Step 9, the third oxide layer corresponding to the fifth region and the PSG layer containing phosphorus element of the fourth doped polysilicon layer obtained in step 8 are removed by using the acidic etching solution to form the back junction battery substrate; the etching solution comprises 30 parts by mass of nitric acid, 40 parts by mass of hydrofluoric acid and 30 parts by mass of deionized water;

[0222] Step 10, the passivation anti-reflection layer is sequentially formed on both sides of the back junction battery substrate obtained in step 9;

[0223] Step 11, coating the fifth region on the front side of the N-type silicon substrate with the passivation anti-reflection layer obtained in step 10 with a low-temperature silver paste metal paste, and coating the back side with a low-temperature aluminum paste metal paste;

[0224] Step 12, sintering the silicon substrate coated with the metal paste at a sintering temperature of 200 DEG C, so that the first metal electrode formed by sintering on the front side of the fifth region is connected to the fourth doped polysilicon layer containing phosphorus through the corresponding passivation anti-reflection layer, and the second metal electrode formed by sintering on the back side is connected to the p+ emitter through the corresponding passivation anti-reflection layer;

[0225] Step 13, coating the back side of the N-type silicon substrate obtained in step 12 with a low-temperature aluminum paste metal paste;

[0226] Step 14, drying the N-type silicon substrate obtained in step 13 at a drying temperature of 200 DEG C to form a third metal electrode on the back side of the silicon substrate, and connecting the adjacent second metal electrodes into one body through the third metal electrode to obtain a solar cell.

[0227] The embodiment of the present application also provides the following technical solutions:

[0228] Technical solution 1. A preparation method of a solar cell, comprising:

[0229] Step 1, sequentially preparing a first tunneling silicon oxide layer 201, a first polysilicon layer 301, a first oxide layer 401 and a first doped layer 501 containing a first type of doped element on one side of a silicon substrate 100 in a thickness direction from inside to outside;

[0230] Step 2, sequentially preparing a second tunneling silicon oxide layer 202 and a second polysilicon layer 302 on the other side of the silicon substrate 100 in the thickness direction from inside to outside;

[0231] Step 3, high-temperature annealing the silicon substrate containing the second polysilicon layer 302 and the first doped layer 501 to introduce and activate a second type of doped element in the second polysilicon layer 302, and to make the first type of doped element contained in the first doped layer 501 enter the first polysilicon layer 301 and activate the first type of doped element.

[0232] Technical solution 2. The method according to technical solution 1, wherein the annealing temperature of the high-temperature annealing in step 3 is 700 DEG C-1000 DEG C.

[0233] Technical solution 3. The method according to technical solution 1, wherein the step 1 comprises: using any one of LPCVD, PECVD, PVD and ALD or a combination of multiple deposition methods to sequentially prepare the first tunneling silicon oxide layer 201, the first polysilicon layer 301, the first oxide layer 401 and the first doped layer 501; and / or the step 2 comprises: using any one of LPCVD, PECVD, PVD and ALD or a combination of multiple deposition methods to prepare the second tunneling silicon oxide layer 202 and the second polysilicon layer 302.

[0234] Technical solution 4. The method according to technical solution 1, further comprising, after the step 1 and before the step 2: step 1-1, removing the first oxide layer 401 and the first doped layer 501 including the first type of doped elements formed on the other side of the silicon substrate 100 in the thickness direction by using an acid etching solution.

[0235] Technical solution 5. The method according to technical solution 4, further comprising, after the step 1-1 and before the step 2: step 1-2, shielding part of the first doped layer 501 by using a patterned shielding layer, and removing the first tunneling silicon oxide layer 201, the first polysilicon layer 301, the first oxide layer 401 and the first doped layer 501 in the unshielded area by using a laser lift-off method to form a first area 101 and a second area 102 arranged in intervals, wherein the first area 101 is an area including the first doped layer 501, and the second area 102 is an area exposing the silicon substrate 100.

[0236] Technical solution 6. The method according to technical solution 5, further comprising, after the step 1-2 and before the step 2: step 1-3, performing alkali texturing on the front surface of the second area 102 to form a textured structure on the upper surface of the second area 102, and removing the first tunneling silicon oxide layer 201 and the first polysilicon layer 301 formed on the other side of the silicon substrate 100 in the thickness direction by using an alkali solution in the alkali texturing; step 1-4, performing boron diffusion / phosphorus diffusion on the textured structure on the front surface of the second area 102 for the case that the silicon substrate 100 is N-type silicon / P-type silicon to form a cell substrate having an emitter 1021 on one side in the thickness direction; and step 1-5, performing wet etching on the other side in the thickness direction and both sides in the length direction of the cell substrate having the front emitter 1021 to remove the PN junction on the side surface of the silicon substrate 100 and the diffusion doped layer formed on the other side in the thickness direction.

[0237] Technical solution 7. The method according to technical solution 6, wherein the steps 1-5 further comprise: etching the back surface and the side surface of the battery substrate with the front surface emitter 1021 by using an etching solution for 0.5-10 minutes; wherein the etching solution comprises 20-40 parts by mass of nitric acid, 30-60 parts by mass of hydrofluoric acid, and 20-30 parts by mass of deionized water.

[0238] Technical solution 8. The method according to technical solution 1, wherein the material of the first oxide layer 401 is silicon oxide; and / or, the thickness of the first tunneling silicon oxide layer 201 is 0.5-3 nm; and / or, the thickness of the second tunneling silicon oxide layer 202 is 0.5-3 nm; and / or, for the case that the silicon substrate 100 is N-type silicon, the first doped layer 501 is a BSG layer; for the case that the silicon substrate 100 is P-type silicon, the first doped layer 501 is a PSG layer.

[0239] Technical solution 9. The method according to technical solution 1, further comprising, after the step 2 and before the step 3: preparing a silicon glass layer containing a second type of doping element outside the second polysilicon layer 302; and in the step 3, introducing and activating the second type of doping element for the second polysilicon layer 302, comprising: by high-temperature annealing, making the second type of doping element contained in the silicon glass layer enter the second polysilicon layer 302 and activate the second type of doping element.

[0240] Technical solution 10. The method according to technical solution 1, further comprising, after the step 3:

[0241] Step 4: removing the first oxide layer 401 and the first doped layer 501 by using an acidic etching solution to form a battery substrate with the first doped polysilicon layer 301' and the second doped polysilicon layer 302' on both sides; Step 5: sequentially forming a passivation anti-reflection layer 600 and an electrode grid line 601 on the outside of the first doped polysilicon layer 301' and the second doped polysilicon layer 302' of the battery substrate, respectively; Step 6: by sintering, making the electrode grid line 601 on both sides pass through the corresponding passivation anti-reflection layer 600 and connect to the corresponding first doped polysilicon layer 301' and second doped polysilicon layer 302'.

[0242] Technical solution 11. The method according to technical solution 10, wherein the sintering temperature is set to 100-500°C; and / or, the electrode grid line 601 is obtained by printing a metal paste, and the metal paste is any one or a combination of aluminum paste, silver-aluminum paste, low-temperature aluminum paste, low-temperature silver-aluminum paste, and low-temperature silver paste; wherein the sintering temperature of the low-temperature aluminum paste, the low-temperature silver-aluminum paste, and the low-temperature silver paste is 100-500°C; and the sintering temperature of the aluminum paste and the silver-aluminum paste is greater than 500°C.

[0243] Technical solution 12. A method for preparing a solar cell, comprising:

[0244] Step 1, sequentially preparing a third tunneling silicon oxide layer 203, a third polysilicon layer 303, a second oxide layer 402, a second doping layer 502 containing a second type of doping element, and an outer oxide layer 700 from inside to outside on the other side of the thickness direction of the silicon substrate 100;

[0245] Step 2, for the side prepared with the outer oxide layer 700, removing part of the second oxide layer 402, the second doping layer 502 with the second type of doping element, and the outer oxide layer 700 to form adjacent third and fourth regions 103 and 104 on the other side of the thickness direction of the silicon substrate 100, the outer layer of the third region 103 being the outer oxide layer 700, and the outer layer of the fourth region 104 being the third polysilicon layer 303;

[0246] Step 3, high-temperature annealing the silicon substrate containing the third and fourth regions 103 and 104 to introduce and activate the second type of doping element for the third polysilicon layer 303 corresponding to the third region 103, forming a third doped region 1031, and at the same time allowing the exogenous first type of doping element to enter the third polysilicon layer 303 corresponding to the fourth region 104 and activate the first type of doping element, forming a fourth doped region 1041.

[0247] Technical solution 13. The method according to technical solution 12, further comprising after the step 3: step 4, removing the second oxide layer 402, the second doping layer 502, and the outer oxide layer 700 corresponding to the third doped region 1031 by using an acidic etching solution to form a back contact cell substrate; step 5, sequentially forming a passivation anti-reflection layer 600 on both sides of the back contact cell substrate, and arranging an electrode grid line 601 on the side of the third doped polysilicon layer 303' containing the third doped region 1031 and the fourth doped region 1041; step 6, by sintering, connecting the electrode grid line 601 corresponding to the third doped region 1031 and the fourth doped region 1041 on the other side of the thickness direction of the back contact cell substrate to the passivation anti-reflection layer 600 arranged on the other side of the thickness direction of the silicon substrate 100 and the third doped polysilicon layer 303' after high-temperature annealing on the other side of the thickness direction.

[0248] Technical solution 14. The method according to technical solution 12, further comprising before the step 1: step 0, forming a first type of front surface field 110 on the side of the thickness direction of the silicon substrate 100, wherein the first type is the same as the doping type of the silicon substrate 100.

[0249] Technical solution 15. The method according to technical solution 12, wherein the annealing temperature of the high-temperature annealing in step 3 is 700-1000℃.

[0250] Technical solution 16. The method according to technical solution 12, wherein step 1 comprises sequentially preparing the third tunneling silicon oxide layer 203, the third polysilicon layer 303, the second oxide layer 402, the second doped layer 502 containing the second type of doped elements, and the outer oxide layer 700 by using any one of LPCVD, PECVD, PVD, and ALD or a combination of multiple deposition methods.

[0251] Technical solution 17. The method according to technical solution 12, further comprising, after step 2 and before step 3, preparing a silicon glass layer containing the first type of doped elements outside the third polysilicon layer 303 on the outer layer of the fourth region 104; and step 3 comprises introducing and activating the first type of doped elements in the third polysilicon layer 303 corresponding to the fourth region 104, by high-temperature annealing, so that the first type of doped elements contained in the silicon glass layer enter the third polysilicon layer 303 corresponding to the fourth region 104 and activate the first type of doped elements.

[0252] Technical solution 18. The method according to technical solution 12, wherein step 2 comprises removing the second oxide layer 402, the second doped layer 502, and the outer oxide layer 700 in some regions by using any one of laser stripping, slurry etching, and coating wet film photoresist or a combination of multiple methods.

[0253] Technical solution 19. The method according to technical solution 12, wherein the material of the second oxide layer 402 is silicon oxide; and / or, the thickness of the third tunneling silicon oxide layer 203 is 0.5-3nm; and / or, for the case that the silicon substrate 100 is N-type silicon, the second doped layer 502 is a BSG layer; for the case that the silicon substrate 100 is P-type silicon, the second doped layer 502 is a PSG layer.

[0254] Technical solution 20. A method for preparing a solar cell, comprising:

[0255] Step 1: sequentially preparing, from inside to outside in the thickness direction of the silicon substrate 100, a fourth tunneling silicon oxide layer 204, a fourth polysilicon layer 304, a third oxide layer 403, and a third doped layer 503 containing the first type of doped elements;

[0256] Step 2, for the side with the third oxide layer 403, use a patterned shielding layer to shield part of the third doped layer 503, to remove the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304, and the third oxide layer 403 in the unshielded area, to form the fifth region 105 and the sixth region 106 arranged in intervals; wherein the fifth region 105 is a region including the third doped layer 503, and the sixth region 106 is a region exposing the silicon substrate 100.

[0257] Step 3, form a first type front surface field 110 in the sixth region 106, wherein the first type is the same as the doping type of the silicon substrate 100.

[0258] Step 4, prepare a silicon glass layer containing a second type doping element on the other side of the silicon substrate 100, and perform high-temperature annealing on the silicon substrate containing the fifth region 105, the sixth region 106, and the silicon glass layer, to introduce and activate a first type doping element in the fourth polysilicon layer 304 of the fifth region 105, to form a fourth doped polysilicon layer 304', and to form a back emitter 1022 containing the second type doping element on the other side of the silicon substrate 100.

[0259] Technical solution 21. The method according to technical solution 20, after the step 4, further comprising: step 5, using an acidic etching solution to remove the third oxide layer 403 and the third doped layer 503 containing the first type doping element, to form a back junction battery substrate; step 6, sequentially forming a passivation anti-reflection layer 600 and an electrode grid line 601 on both sides of the back junction battery substrate; step 7, by sintering, the electrode grid line 601 arranged on one side of the silicon substrate 100 is connected to the corresponding fourth doped polysilicon layer 304' through the corresponding passivation anti-reflection layer; the electrode grid line 601 arranged on the other side of the silicon substrate 100 is connected to the back emitter 1022 through the corresponding passivation anti-reflection layer.

[0260] Technical solution 22. The method according to technical solution 21, the electrode grid line 601 comprises: a first metal electrode 6011 arranged outside the fourth doped polysilicon layer 304' obtained by step 4, a second metal electrode 6012 arranged on the other side of the silicon substrate 100 in a discontinuous local point contact manner, and a third metal electrode 6013; wherein the third metal electrode 6013 connects adjacent second metal electrodes 6012 into one body.

[0261] Technical solution 23. The method according to technical solution 20, the annealing temperature of high-temperature annealing in the step 4 is 700-1000℃.

[0262] Technical solution 24. The method according to technical solution 20, after step 2, further comprising: step 2-1, texturing the exposed surface of the silicon substrate 100 in the sixth region 106 to form a textured structure in the sixth region 106, while removing the fourth tunneling silicon oxide layer 204 and the fourth polysilicon layer 304 formed on the other side of the thickness direction of the silicon substrate 100.

[0263] Technical solution 25. The method according to technical solution 21, wherein step 4 comprises: for the case that the silicon substrate 100 is N-type silicon, performing boron diffusion on the other side of the silicon substrate 100; for the case that the silicon substrate 100 is P-type silicon, performing phosphorus diffusion on the other side of the silicon substrate 100 to form a cell substrate with a back surface emitter 1022.

[0264] Technical solution 26. The method according to technical solution 20, wherein step 1 comprises: using any one of LPCVD, PECVD, PVD and ALD deposition methods or a combination of multiple deposition methods to sequentially prepare the fourth tunneling silicon oxide layer 204, the fourth polysilicon layer 304, the third oxide layer 403 and the third doping layer 503 containing the second type of doping elements.

[0265] Technical solution 27. The method according to technical solution 20, after step 1 and before step 2, further comprising: step 1-1, removing the third oxide layer 403 and the third doping layer 503 containing the second type of doping elements formed on the other side of the thickness direction of the silicon substrate 100 by using an acidic etching solution; wherein the etching solution comprises 20-40 parts by mass of nitric acid, 30-60 parts by mass of hydrofluoric acid and 20-30 parts by mass of deionized water.

[0266] Technical solution 28. The method according to technical solution 21, after step 3 and before step 4, further comprising: performing wet etching treatment on the other side of the silicon substrate containing the first type of front surface field 110 to remove the PN junction formed on both sides of the length direction of the silicon substrate 100 and the doping spread layer formed on the other side of the thickness direction of the silicon substrate 100.

[0267] Technical solution 29. The method according to technical solution 20, after step 1 and before step 2, further comprising: texturing the other side of the thickness direction of the silicon substrate with the third doping layer 503 to form a textured structure on the side opposite to the third oxide layer 403.

[0268] Technical solution 30. The method according to technical solution 21, wherein the sintering temperature is set to 100-500℃; and / or, the electrode grid line 601 is printed by using a metal paste, the metal paste being any one or a combination of aluminum paste, silver-aluminum paste, low-temperature aluminum paste, low-temperature silver-aluminum paste, and low-temperature silver paste; wherein the sintering temperature of the low-temperature aluminum paste, the low-temperature silver-aluminum paste, and the low-temperature silver paste is 100-500℃; and the sintering temperature of the aluminum paste and the silver-aluminum paste is greater than 500℃.

[0269] Technical solution 31. A solar cell prepared by any one of the preparation methods according to technical solutions 1-11, comprising: a silicon substrate 100; a first tunneling silicon oxide layer 201 and a first doped polysilicon layer 301' containing a first type of doping element arranged in sequence from inside to outside on one side of the silicon substrate 100 in the thickness direction; a second tunneling silicon oxide layer 202 and a second doped polysilicon layer 302' containing a second type of doping element arranged in sequence from inside to outside on the other side of the silicon substrate 100 in the thickness direction.

[0270] Technical solution 32. The solar cell according to technical solution 31, further comprising: a passivation anti-reflection layer 600 arranged on the first doped polysilicon layer 301' and the second doped polysilicon layer 302', respectively; and an electrode grid line 601 passing through the passivation anti-reflection layer 600 and connected to the corresponding doped polysilicon layer.

[0271] Technical solution 33. The solar cell according to technical solution 31, wherein the first tunneling silicon oxide layer 201 and the first doped polysilicon layer 301' are arranged in correspondence and in sequence on a local area on one side of the silicon substrate 100, and the local areas arranged with the first tunneling silicon oxide layer 201 and the first doped polysilicon layer 301' are arranged in intervals.

[0272] Technical solution 34. A solar cell prepared by any one of the preparation methods according to technical solutions 12-19, comprising: a silicon substrate 100; a third tunneling silicon oxide layer 203 arranged on the other side of the silicon substrate 100 and a third doped polysilicon layer 303' stacked on the third tunneling silicon oxide layer 203; wherein the third doped polysilicon layer 303' is divided into a third doped region 1031 containing a second type of doping element and a fourth doped region 1041 containing a first type of doping element.

[0273] Technical solution 35. The solar cell according to technical solution 34, further comprising: a first type of front surface field 110 arranged on one side of the silicon substrate 100, wherein the first type is the same as the doping type of the silicon substrate 100.

[0274] Technical solution 36. The solar cell according to technical solution 35, further comprising: a passivation anti-reflection layer 600 arranged on the first type of front surface field 110 and the third doped polysilicon layer 303'; an electrode grid line 601 connected with the third doped region 1031 through the passivation anti-reflection layer 600 on the third doped region 1031; and an electrode grid line 601 connected with the fourth doped region 1041 through the passivation anti-reflection layer 600 on the fourth doped region 1041.

[0275] Technical solution 37. A solar cell prepared by the method according to any one of technical solutions 20-30, comprising: a silicon substrate 100; wherein one side of the silicon substrate 100 in the thickness direction is divided into a fifth region 105 containing a fourth doped polysilicon layer 304' and a sixth region 106 containing a front surface field 110 of a first type of doped element; wherein the first type is the same as the type of the silicon substrate 100; the fourth doped polysilicon layer 304' is arranged on the fourth tunneling silicon oxide layer 204 arranged in the fifth region 105; and a back surface emitter 1022 is arranged on the other side of the silicon substrate 100 in the thickness direction.

[0276] Technical solution 38. The solar cell according to technical solution 37, further comprising: a passivation anti-reflection layer 600 arranged on the outside of the fifth region 105 and the sixth region 106 and on the outside of the back surface emitter 1022; an electrode grid line 601 connected with the fourth doped polysilicon layer 304' through the passivation anti-reflection layer 600 on the fifth region 105; and an electrode grid line 601 connected with the back surface emitter 1022 through the passivation anti-reflection layer 600 arranged on the other side of the silicon substrate 100 in the thickness direction.

[0277] Technical solution 39. A photovoltaic module, comprising: a cell piece made of the solar cell according to any one of technical solutions 31-38.

[0278] Technical solution 40. A power station, comprising: the photovoltaic module according to technical solution 39.

[0279] The above steps provide an introduction to help understand the structure, method and core idea of the present application. For those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also belong to the scope of protection of the claims of the present application.

Claims

1. A method for producing a solar cell, characterized by, Comprising: Step 1, sequentially preparing a first tunneling silicon oxide layer (201), a first polysilicon layer (301), a first oxide layer (401), and a first doped layer (501) containing a first type of doping element from inside to outside on one side of the thickness direction of a silicon substrate (100); Step 2, sequentially preparing a second tunneling silicon oxide layer (202) and a second polysilicon layer (302) from inside to outside on the other side of the thickness direction of the silicon substrate (100); Step 3, performing high-temperature annealing on the silicon substrate containing the second polysilicon layer (302) and the first doped layer (501) to introduce and activate a second type of doping element for the second polysilicon layer (302), and at the same time, causing the first type of doping element contained in the first doped layer (501) to enter the first polysilicon layer (301) and activate the first type of doping element; Step 4, removing the first oxide layer (401) and the first doped layer (501) using an acidic etching solution to form a battery substrate with a first doped polysilicon layer (301') and a second doped polysilicon layer (302') on both sides.

2. The method according to claim 1, characterized in that: The annealing temperature in step 3 is 700-1000°C.

3. The method of claim 1, wherein, Step 1 includes using any one of LPCVD, PECVD, PVD, and ALD deposition methods or a combination of multiple deposition methods to sequentially prepare the first tunneling silicon oxide layer (201), the first polysilicon layer (301), the first oxide layer (401), and the first doped layer (501); And / or; Step 2 includes using any one of LPCVD, PECVD, PVD, and ALD deposition methods or a combination of multiple deposition methods to prepare the second tunneling silicon oxide layer (202) and the second polysilicon layer (302).

4. The method of claim 1, wherein, After step 1 and before step 2, it further includes: Step 1-1, using an acidic etching solution to remove the first oxide layer (401) and the first doped layer (501) containing a first type of doping element generated by sputtering on the other side of the thickness direction of the silicon substrate (100).

5. The method of claim 4, wherein, After step 1-1 and before step 2, it further includes: Step 1-2, using a patterned shielding layer to shield part of the first doped layer (501), and using laser stripping to remove the first tunneling silicon oxide layer (201), the first polysilicon layer (301), the first oxide layer (401), and the first doped layer (501) in the unshielded area to form a first region (101) and a second region (102) arranged in intervals, wherein the first region (101) is a region containing the first doped layer (501), and the second region (102) is a region exposing the silicon substrate (100) to the outside.

6. The method of claim 5, wherein, After step 1-2 and before step 2, it further includes: Step 1-3, alkali texturing is performed on the front surface of the second region (102) to form a textured structure on the upper surface of the second region (102), and meanwhile, the first tunneling silicon oxide layer (201) and the first polysilicon layer (301) formed on the other side of the thickness direction of the silicon substrate (100) are removed by using an alkali solution in the alkali texturing; Step 1-4, for the case that the silicon substrate (100) is N-type silicon / P-type silicon, boron diffusion / phosphorus diffusion is performed on the textured structure on the front surface of the second region (102) to form a cell substrate with an emitter (1021) on one side of the thickness direction; Step 1-5, wet etching is performed on the other side of the thickness direction and the two sides of the length direction of the cell substrate with the emitter (1021) on the front surface to remove the PN junction on the side of the silicon substrate (100) and the diffusion doped layer formed on the other side of the thickness direction.

7. The method of claim 6, wherein, The step 1-5 comprises: Etching the back surface and the side surface of the cell substrate with the emitter (1021) on the front surface by using an etching solution for 0.5 min to 10 min; wherein the etching solution comprises 20-40 parts by mass of nitric acid, 30-60 parts by mass of hydrofluoric acid and 20-30 parts by mass of deionized water.

8. The method of claim 1, wherein, The material of the first oxide layer (401) is silicon oxide; and / or, The thickness of the first tunneling silicon oxide layer (201) is 0.5-3 nm; and / or, The thickness of the second tunneling silicon oxide layer (202) is 0.5-3 nm; and / or, For the case that the silicon substrate (100) is N-type silicon, the first doped layer (501) is a BSG layer; For the case that the silicon substrate (100) is P-type silicon, the first doped layer (501) is a PSG layer.

9. The method of claim 1, wherein, After the step 2 and before the step 3, the method further comprises: Preparation of a silicon glass layer containing a second type of doped elements on the outside of the second polysilicon layer (302); In the step 3, the second type of doped elements is introduced and activated for the second polysilicon layer (302), which comprises: through high-temperature annealing, the second type of doped elements contained in the silicon glass layer enter the second polysilicon layer (302) and activate the second type of doped elements.

10. The method of claim 1, wherein, After the step 4, the method further comprises: Step 5, sequentially forming a passivation anti-reflection layer (600) and an electrode grid line (601) on the outside of the first doped polysilicon layer (301') and the second doped polysilicon layer (302') of the cell substrate, respectively; Step 6, by sintering, the electrode grid line (601) on both sides passes through the corresponding passivation anti-reflection layer (600) and connects with the corresponding first doped polysilicon layer (301') and second doped polysilicon layer (302').

11. The method of claim 10, wherein: The temperature of the sintering is set to 100-500°C; and / or, ​ The electrode grid line (601) is obtained by printing metal paste, the metal paste is any one or combination of aluminum paste, silver aluminum paste, low-temperature aluminum paste, low-temperature silver aluminum paste and low-temperature silver paste; wherein the sintering temperature of the low-temperature aluminum paste, the low-temperature silver aluminum paste and the low-temperature silver paste is 100-500 DEG C; the sintering temperature of the aluminum paste and the silver aluminum paste is greater than 500 DEG C.

12. A method of manufacturing a solar cell, characterized by, Comprise: Step 1, on the other side of the thickness direction of the silicon substrate (100), from inside to outside, prepare a third tunneling silicon oxide layer (203), a third polysilicon layer (303), a second oxide layer (402), a second doped layer (502) comprising a second type of doped elements, and an external oxide layer (700); Step 2, for the side prepared with the external oxide layer (700), remove part of the second oxide layer (402), the second doped layer (502) with the second type of doped elements and the external oxide layer (700) in the region, to form adjacent third and fourth regions (103) and (104) on the other side of the thickness direction of the silicon substrate (100), the outer layer of the third region (103) is the external oxide layer (700), and the outer layer of the fourth region (104) is the third polysilicon layer (303); Step 3, high temperature annealing is performed on the silicon substrate containing the third and fourth regions (103) and (104) to introduce and activate the second type of doped elements for the third polysilicon layer (303) corresponding to the third region (103), forming a third doped region (1031), and at the same time, the exogenous first type of doped elements enters the third polysilicon layer (303) corresponding to the fourth region (104) and activates the first type of doped elements, forming a fourth doped region (1041); Step 4, using an acidic etching solution to remove the second oxide layer (402), the second doped layer (502) and the external oxide layer (700) corresponding to the third doped region (1031), forming a back contact cell substrate.

13. The method of claim 12, wherein, After step 4, further comprising: Step 5, forming a passivation anti-reflection layer (600) on both sides of the back contact cell substrate in sequence, and setting an electrode grid line (601) on one side of the third doped polysilicon layer (303') containing the third doped region (1031) and the fourth doped region (1041); Step 6, by sintering, the electrode grid line (601) corresponding to the third doped region (1031) and the fourth doped region (1041) on the other side of the thickness direction of the back contact cell substrate is connected to the passivation anti-reflection layer (600) provided on the other side of the thickness direction of the silicon substrate (100) and the third doped polysilicon layer (303') after high temperature annealing on the other side of the thickness direction.

14. The method of claim 13, wherein, Before step 1, further comprising: Step 0, forming a first type of front surface field (110) on one side of the thickness direction of the silicon substrate (100), wherein the first type is the same as the doping type of the silicon substrate (100).

15. The method of claim 13, wherein, The annealing temperature of high temperature annealing in step 3 is 700-1000 DEG C.

16. The method of claim 13, wherein, Step 1 includes: sequentially preparing the third tunneling silicon oxide layer (203), the third polysilicon layer (303), the second oxide layer (402), the second doped layer (502) containing the second type of doped elements, and the external oxide layer (700) by using any one of the deposition methods of LPCVD, PECVD, PVD, and ALD or a combination of multiple deposition methods.

17. The method of claim 13, wherein, After the step 2 and before the step 3, further comprising: Outside the third polysilicon layer (303) of the outer layer of the fourth region (104), a silicon glass layer containing the first type of doped elements is prepared; In step 3, the first type of doped elements is introduced and activated for the third polysilicon layer (303) corresponding to the fourth region (104), including: through high-temperature annealing, the first type of doped elements contained in the silicon glass layer enters the third polysilicon layer (303) corresponding to the fourth region (104) and activates the first type of doped elements.

18. The method of claim 13, wherein, Step 2 includes: Any one of the following methods or a combination of multiple methods is used to remove the second oxide layer (402), the second doped layer (502), and the external oxide layer (700) in part of the region: laser stripping, slurry etching, and coating wet film photoresist.

19. The method of claim 13, wherein, The material of the second oxide layer (402) is silicon oxide; And / or, The thickness of the third tunneling silicon oxide layer (203) is 0.5-3 nm; and / or, For the case that the silicon substrate (100) is N-type silicon, the second doped layer (502) is a BSG layer; For the case that the silicon substrate (100) is P-type silicon, the second doped layer (502) is a PSG layer.

20. A method for preparing a solar cell, characterized in that, Including: Step 1, from inside to outside on one side of the thickness direction of the silicon substrate (100), sequentially preparing a fourth tunneling silicon oxide layer (204), a fourth polysilicon layer (304), a third oxide layer (403), and a third doped layer (503) containing the first type of doped elements; Step 2, for the side on which the third oxide layer (403) is prepared, using a patterned shielding layer to shield part of the third doped layer (503), removing the fourth tunneling silicon oxide layer (204), the fourth polysilicon layer (304), and the third oxide layer (403) in the unshielded part of the region, to form the fifth region (105) and the sixth region (106) arranged in intervals; wherein the fifth region (105) is a region containing the third doped layer (503), and the sixth region (106) is a region exposed to the outside of the silicon substrate (100); Step 3, forming a first type of front surface field (110) in the sixth region (106), wherein the first type is the same as the doping type of the silicon substrate (100); Step 4, for the fifth region (105), introducing and activating the first type of doped elements in the third doped layer (503), including: through high-temperature annealing, the first type of doped elements contained in the third doped layer (503) enters the third polysilicon layer (304) corresponding to the fifth region (105) and activates the first type of doped elements. Step 4, a silicon glass layer containing a second type of doping element is prepared on the other side of the silicon substrate (100), and the silicon substrate containing the fifth region (105), the sixth region (106) and the silicon glass layer is subjected to high-temperature annealing to introduce and activate the first type of doping element for the fourth polysilicon layer (304) of the fifth region (105) to form a fourth doped polysilicon layer (304'), and meanwhile a back surface emitter (1022) containing the second type of doping element is formed on the other side of the silicon substrate (100); Step 5, the third oxide layer (403) and the third doped layer (503) containing the first type of doping element are removed by using an acidic etching solution to form a back junction battery substrate.

21. The method of claim 20, wherein, After the step 5, further comprising: Step 6, a passivation anti-reflection layer (600) and an electrode grid line (601) are sequentially formed on both sides of the back junction battery substrate; Step 7, the electrode grid line (601) arranged on the one side of the silicon substrate (100) is connected to the corresponding fourth doped polysilicon layer (304') through the corresponding passivation anti-reflection layer by sintering, and the electrode grid line (601) arranged on the other side of the silicon substrate (100) is connected to the back surface emitter (1022) through the corresponding passivation anti-reflection layer.

22. The method of claim 21, wherein, The electrode grid line (601) comprises: a first metal electrode (6011) arranged outside the fourth doped polysilicon layer (304') obtained in the step 4, a second metal electrode (6012) arranged on the other side of the silicon substrate (100) in a discontinuous and local point contact manner, and a third metal electrode (6013); The third metal electrode (6013) connects adjacent second metal electrodes (6012) into one body.

23. The method of claim 20, wherein, The annealing temperature of the high-temperature annealing in the step 4 is 700-1000℃.

24. The method of claim 20, wherein, After the step 2, further comprising: Step 2-1, texturing is performed on the surface of the silicon substrate (100) exposed by the sixth region (106) to form a textured structure on the sixth region (106), and meanwhile the fourth tunneling silicon oxide layer (204) and the fourth polysilicon layer (304) generated by around-plating on the other side of the silicon substrate (100) in the thickness direction are removed.

25. The method of claim 20, wherein, The step 4 comprises: For the case that the silicon substrate (100) is N-type silicon, boron diffusion is performed on the other side of the silicon substrate (100); for the case that the silicon substrate (100) is P-type silicon, phosphorus diffusion is performed on the other side of the silicon substrate (100) to form a battery substrate with a back surface emitter (1022) on the back surface.

26. The method of claim 20, wherein, The step 1 comprises: using any one of LPCVD, PECVD, PVD and ALD deposition methods or a combination of multiple deposition methods to sequentially prepare the fourth tunneling silicon oxide layer (204), the fourth polysilicon layer (304), the third oxide layer (403) and the third doped layer (503) containing the first type of doping element.

27. The method of claim 20, wherein, After the step 1 and before the step 2, further comprising: Step 1-1, removing the third oxide layer (403) and the third doped layer (503) including the first type of doped elements on the other side of the thickness direction of the silicon substrate (100) by using an acidic etching solution; wherein the etching solution includes 20-40 parts by mass of nitric acid, 30-60 parts by mass of hydrofluoric acid, and 20-30 parts by mass of deionized water.

28. The method of claim 20, wherein, After the step 3, before the step 4, further comprising: Performing wet etching treatment on the other side of the silicon substrate including the first type of front surface field (110) to remove the PN junction formed on both sides of the length direction of the silicon substrate (100) and the doped diffusion layer formed on the other side of the thickness direction.

29. The method of claim 20, wherein, After the step 1, before the step 2, further comprising: Texturing the other side of the silicon substrate with the third doped layer (503) in the thickness direction to form a textured structure on the side opposite to the third oxide layer (403).

30. The method of claim 21, wherein, the sintering temperature is set to 100-500°C; and / or, the electrode grid line (601) is printed using metal paste, and the metal paste is any one or a combination of aluminum paste, silver-aluminum paste, low-temperature aluminum paste, low-temperature silver-aluminum paste, and low-temperature silver paste; wherein the sintering temperature of the low-temperature aluminum paste, the low-temperature silver-aluminum paste, and the low-temperature silver paste is 100-500°C; and the sintering temperature of the aluminum paste and the silver-aluminum paste is greater than 500°C.

31. A solar cell prepared according to the method of any one of claims 1 to 11, characterized in that comprising: a silicon substrate (100); a first tunneling silicon oxide layer (201) and a first doped polysilicon layer (301') including a first type of doped elements are sequentially arranged from inside to outside on one side of the thickness direction of the silicon substrate (100); a second tunneling silicon oxide layer (202) and a second doped polysilicon layer (302') including a second type of doped elements are sequentially arranged from inside to outside on the other side of the thickness direction of the silicon substrate (100).

32. The solar cell of claim 31, wherein, further comprising: a passivation anti-reflection layer (600) is separately arranged on the first doped polysilicon layer (301') and the second doped polysilicon layer (302'); and an electrode grid line (601) is connected to the corresponding doped polysilicon layer through the passivation anti-reflection layer (600).

33. The solar cell of claim 31, wherein the back surface is textured. The first tunneling silicon oxide layer (201) and the first doped polysilicon layer (301') are correspondingly arranged in a local area on one side of the silicon substrate (100), and the local areas where the first tunneling silicon oxide layer (201) and the first doped polysilicon layer (301') are arranged are arranged at intervals.

34. A solar cell prepared according to the method of any one of claims 12 to 19, characterized in that comprising: a silicon substrate (100); a third tunneling silicon oxide layer (203) is arranged on the other side of the silicon substrate (100), and a third doped polysilicon layer (303') is arranged on the third tunneling silicon oxide layer (203); wherein the third doped polysilicon layer (303') is divided into a third doped region (1031) including a second type of doped elements and a fourth doped region (1041) including a first type of doped elements.

35. The solar cell of claim 34, wherein, further comprising: A first type front surface field (110) is arranged on one side of the silicon substrate (100), wherein the first type is the same as the doping type of the silicon substrate (100).

36. The solar cell of claim 34, wherein, Further comprising: A passivation anti-reflection layer (600) arranged on the first type front surface field (110) and the third doped polysilicon layer (303'); An electrode grid line (601) connected with the third doped region (1031) through the passivation anti-reflection layer (600) on the third doped region (1031); and an electrode grid line (601) connected with the fourth doped region (1041) through the passivation anti-reflection layer (600) on the fourth doped region (1041).

37. A solar cell produced according to the method of any one of claims 20 to 30, characterized in that Further comprising: A silicon substrate (100); wherein one side of the silicon substrate (100) in the thickness direction is divided into a fifth region (105) containing a fourth doped polysilicon layer (304') and a sixth region (106) containing a front surface field (110) of a first type doping element; wherein the first type is the same as the type of the silicon substrate (100); A fourth tunneling silicon oxide layer (204) is arranged in the fifth region (105), and a fourth doped polysilicon layer (304') is arranged on the fourth tunneling silicon oxide layer (204); A back surface emitter (1022) is arranged on the other side of the silicon substrate (100) in the thickness direction.

38. The solar cell of claim 37, wherein, Further comprising: A passivation anti-reflection layer (600) arranged on the outside of the fifth region (105) and the sixth region (106) and on the outside of the back surface emitter (1022); An electrode grid line (601) connected with the fourth doped polysilicon layer (304') through the passivation anti-reflection layer (600) on the fifth region (105); and an electrode grid line (601) connected with the back surface emitter (1022) through the passivation anti-reflection layer (600) arranged on the other side of the silicon substrate (100) in the thickness direction.

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