Single-channel wide dynamic range single fast pulse signal acquisition system

Abstract

This invention relates to a high-speed signal acquisition system, specifically a single-channel wide dynamic range single fast pulse signal acquisition system, solving the technical problem of acquiring a large dynamic range of a single fast pulse P1. The single-channel wide dynamic range single fast pulse signal acquisition system provided by this invention includes a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3. The composite pulse train shaping circuit S1 includes a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4, where N is an integer greater than 1. The input terminal of the composite pulse train shaping circuit S1 receives a fast pulse P1, first splits the input fast pulse P1, then delays each of the split circuits, and finally combines them into a pulse train P2. Multiple samplings of the single fast pulse P1 signal are achieved within a short time using a single recording channel. Furthermore, by configuring different attenuation parameters for each split circuit, a large dynamic range of the single fast pulse P1 signal can be acquired.

Description

Technical Field

[0001] This invention relates to a high-speed signal acquisition system, specifically a single-channel wide dynamic range single-shot fast pulse signal acquisition system. Background Technology

[0002] Fast pulse signal measurement has wide applications in scientific experiments such as high-energy physics, radiation detection, and detonation experiments. These physical experiments occur extremely briefly, and their physical detection signals are transient, typically ranging from nanoseconds to microseconds in duration. Most importantly, their amplitudes are uncertain and wide-ranging, potentially covering a few millivolts to hundreds of volts. Furthermore, these signals are non-periodic and non-repeatable, posing significant challenges to their accurate acquisition.

[0003] Currently, the acquisition of such single fast pulse signals often employs a multi-segment range coverage method. The principle is to first use a power divider to split the signal into multiple paths, and then acquire the signal using multiple oscilloscope or data acquisition instrument channels through range overlap. By setting different gains, these channels respectively cover different amplitude ranges of the fast pulse signal. While this acquisition method can achieve the acquisition of fast pulse signals, it suffers from inconsistencies due to differences in synchronization triggering, bias, conditioning circuits, and analog-to-digital converters between different channels. Summary of the Invention

[0004] The purpose of this invention is to address the technical problem of inconsistency caused by differences in synchronization triggering units, bias units, conditioning circuits, analog-to-digital converters, etc., between different channels in commonly used multi-segment range coverage methods for acquiring large dynamic range of single fast pulses. The invention provides a single-channel wide dynamic range single fast pulse signal acquisition system that uses a single recording channel to sample the single fast pulse P1 signal multiple times in a short period of time. At the same time, by configuring the attenuation parameters of different branches, a large dynamic range of the single fast pulse P1 signal can be acquired.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A single-channel wide dynamic range single-shot fast pulse signal acquisition system is characterized by comprising a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3.

[0007] The composite pulse train shaping circuit S1 includes a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4, where N is an integer greater than 1;

[0008] The input terminal of the power divider circuit U1 is used to receive the input fast pulse P1 and divide the input fast pulse P1 into N pulse signals, which are then input into N attenuation circuits U2 respectively.

[0009] N attenuation circuits U2 adjust the gain of N pulse signals respectively, forming N pulses with different gains, which are then input into the corresponding N analog delay circuits U3.

[0010] N analog delay circuits U3 will delay N signals by time T. D1 ... T DN N pulses with different gains are added respectively to generate N phase-separated pulses, which are then input to the input terminals of the composite circuit U4.

[0011] The composite circuit U4 combines N phase-separated pulses into a pulse train P2 and inputs it to the input terminal of the data acquisition unit S2;

[0012] The data acquisition unit S2 is used to digitize the waveform of the pulse train P2 to obtain waveform data; the data acquisition unit S2 and the acquisition and reconstruction unit S3 are interconnected.

[0013] The acquisition and restoration unit S3 is used to extract the sampling results of multiple fast pulses P1 from the digitized waveform data, and obtain sampling waveforms of different ranges according to the calibrated vertical sensitivity and delay time, thereby realizing the large dynamic range acquisition of a single input fast pulse P1.

[0014] Furthermore, the power divider circuit U1 is a discrete resistor circuit; the attenuation circuit U2 uses an integrated attenuator or a discrete resistor; the analog delay circuit U3 is an analog delay line device; and the composite circuit U4 is a composite pulse train shaper based on the adder principle.

[0015] Furthermore, the power divider circuit U1 includes resistor R1 and resistor R 01 Resistance R 02 ..., resistance R 0N ;

[0016] One end of resistor R1 is connected to the fast pulse P1, and the other end is connected to resistor R. 01 Resistance R 02 ..., resistance R 0N One end;

[0017] resistor R 01 Resistance R 02 ..., resistance R 0N The other end is connected to the input terminals of N attenuation circuits U2 respectively.

[0018] Furthermore, the attenuation circuit U2 includes resistors R5, R6, and R7;

[0019] One end of resistor R7 is connected to one end of resistor R5, and the other end of resistor R7 is connected to one end of resistor R6; the other end of resistor R5 is grounded, and the other end of resistor R6 is grounded.

[0020] One end of the N attenuation circuits U2 connected to resistors R7 and R5 is respectively connected to resistor R 01 Resistance R 02 ..., resistance R 0N The other end is connected;

[0021] One end of the resistors R7 and R6 of the N attenuation circuits U2 is connected to the input of the N analog delay circuits U3.

[0022] Furthermore, the analog delay circuit U3 includes resistors R, Rin, and Rout, as well as analog delay line devices;

[0023] One end of resistor Rin is connected to one end of resistor R, the other end of resistor Rin is connected to the input terminal of the analog delay line device, and the output terminal of the analog delay line device is connected to one end of resistor Rout.

[0024] The other end of resistor R is grounded, and the other end of resistor Rout is grounded;

[0025] The end of resistor Rin connected to resistor R is connected to the end of resistor R7 connected to resistor R6 in the corresponding attenuation circuit U2.

[0026] The output terminals of the analog delay line devices of N analog delay circuits U3 are respectively connected to the input terminal of the composite circuit U4.

[0027] Furthermore, the composite circuit U4 includes a resistor R. C1 Resistance R C2 ..., resistance R CN ;

[0028] resistor R C1 One end, resistor R C2 One end, ..., resistor R CN One end of each is connected to the output of the corresponding analog delay unit;

[0029] resistor R C1 The other end, resistor R C2 The other end, ..., resistor R CN The other end is connected to serve as the output of the composite circuit U4, and is also connected to the input of the data acquisition unit S2.

[0030] Furthermore, the data acquisition unit S2 includes a radio frequency drive unit, an analog-to-digital converter, a processor unit, a clock synchronization unit, a storage unit, a trigger unit, an interface unit, and a bias unit;

[0031] The input terminal of the RF driver unit is connected to the output terminal of the composite circuit U4; the output terminal of the RF driver unit is connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to the input terminal of the processor unit.

[0032] The output of the processor unit is connected to the control input of the RF drive unit and the analog-to-digital converter, respectively; the processor unit is also communicatively connected to the storage unit and the interface unit, respectively.

[0033] The output of the clock synchronization unit is connected to the analog-to-digital converter, the processor unit, and the storage unit, respectively, to provide clock signals;

[0034] The input terminal of the trigger unit is used to receive the external trigger unit signal Trig, and its output terminal is connected to the trigger unit input terminal of the processor unit;

[0035] The output of the bias unit is connected to the input of the RF drive unit;

[0036] The interface unit and the acquisition and restoration unit S3 are interconnected.

[0037] Furthermore, the composite pulse train shaping circuit S1 also includes a limiting protection circuit U5;

[0038] The limiting protection circuit U5 includes diodes Q1 and Q2; the positive terminal of diode Q1 and the negative terminal of diode Q2 are connected and connected to the output terminal of the composite circuit U4.

[0039] The cathode of diode Q1 is connected to the positive power supply V+, and the anode of diode Q2 is connected to the negative power supply V-.

[0040] Furthermore, the value of N is 3.

[0041] Furthermore, the impedance of the power divider circuit U1 is 50Ω, and R1=R2=R3=R4=24.9Ω;

[0042] R5=R6=61.1Ω, R7=24.7Ω;

[0043] The resistance R is 50Ω, Rin = Rout = Z line =50Ω, where Z line To simulate the impedance of the delayer;

[0044] R C1 =R C2 =R C3 , (R line1 +R C1 ) / / (R line2 +R C2 ) / / (R line3 +R C3) = 50Ω, where R line1 R line2 R line3 These represent the output impedances of the corresponding analog delay circuit U3.

[0045] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0046] 1. The composite pulse train shaping circuit S1 of this invention receives a fast pulse P1 at its input terminal. The input fast pulse P1 is first spun out and then delayed separately, finally composited into a pulse train P2. Each pulse in the generated pulse train P2 maintains the same waveform as the fast pulse P1, achieving multiple replications of the fast pulse P1. Simultaneously, different attenuation circuits U2 can be added to the spun-out circuits to form pulses with different gains. Therefore, the formed pulse train P2 is not only a multiple replication of the fast pulse P1 waveform but also consists of multiple pulses with different gains. The pulse train P2 output by the composite pulse train shaping circuit S1 is connected to the radio frequency drive unit circuit of the data acquisition unit S2. The data acquisition unit S2 digitizes the waveform of the pulse train P2. Since the pulse train P2 replicates multiple pulse waveforms of the fast pulse P1 with different gains, the data acquisition unit S2 can achieve multiple samplings of the input fast pulse P1. The data acquisition unit S2 uploads the digitized waveform to the acquisition and restoration unit S3 of the host computer. The host computer uses the acquisition software to extract the sampling results of multiple fast pulses P1 from the digitized waveform data, and obtains sampling waveforms of different ranges according to the pre-calibrated vertical sensitivity and delay time, thereby realizing the large dynamic range acquisition of fast pulses P1 of a single input signal.

[0047] 2. This invention utilizes a single channel composed of a composite pulse train shaping circuit S1 and a data acquisition unit S2 to achieve multiple samplings of a single input signal fast pulse P1 signal, which can significantly reduce the size of the sampling system.

[0048] 3. The main feature of this invention is the addition of a composite pulse train forming circuit S1 at the front end. The composite pulse train forming circuit S1 consists of a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4. The back end of the composite pulse train forming circuit S1 uses a data acquisition unit S2. The bias circuit (bias unit), RF drive unit circuit, and analog-to-digital converter of the data acquisition unit S2 all use the same circuit (i.e., the same channel). Therefore, the results of multiple samplings have good consistency and can avoid the channel differences introduced by multi-channel parallel sampling.

[0049] 4. The power divider circuit U1 divides the fast pulse P1 into N outputs. The N outputs of the power divider circuit U1 are connected to the input of the attenuation circuit U2. The attenuation coefficient of each output can be adjusted independently by the attenuation circuit U2. When any attenuation circuit does not need attenuation, the power divider output of that output can bypass the attenuation circuit U2 and be directly connected to the back-end analog delay circuit U3, so as to realize the phase separation of the N pulse signals.

[0050] 5. This invention is applicable to most high-speed data acquisition systems based on conventional architectures. It only requires adding a composite pulse train forming circuit S1 with splitting, delaying and compositing functions to the signal input terminal. It does not require extensive hardware modifications to analog conditioning circuits, analog-to-digital converters, high-precision clock circuits, digital processing circuits, etc., and has strong applicability.

[0051] 6. The attenuation circuit U2 can be implemented using an integrated attenuator or discrete resistors. When using an integrated attenuator, it can be directly soldered onto the circuit board, offering advantages such as small size, high precision, and high reliability. When using a discrete resistor network, different attenuation factors can be determined by adjusting the values ​​of resistors R5, R6, and R7. For example, when the attenuation value is 20dB, R7 = 24.7Ω, and R5 = R6 = 61.1Ω. Alternatively, resistors R5, R6, and R7 can preferably be high-precision thick-film high-frequency resistors with a 0.1% accuracy.

[0052] 7. The analog delay circuit U3 preferably integrates a surface-mount analog delay line device. Its different output pins T1-T20 represent different delay times. The phase-separated pulse delay time gradually reaches the maximum delay time of the analog delay line device through T1 to T20; this allows the analog delay circuit U3 to better add a signal delay time T to each pulse signal with different gains. D1 To T Dn .

[0053] 8. The composite circuit U4 combines N phase-separated pulses into a pulse train, realizing the synthesis of multiple signals into a single signal for acquisition.

[0054] 9. The limiting protection circuit U5 is applied to the output of the composite circuit U4. Since the input signal range of the analog-to-digital converter is generally several hundred millivolts to several volts, in order to avoid the influence of the high-gain pulse in the pulse train P2 on the sampling of the subsequent analog-to-digital converter, the limiting protection circuit U5 can be used to clamp the high-gain pulse within the limiting voltage range. Attached Figure Description

[0055] Figure 1 This is a block diagram illustrating the principle of the single-channel wide dynamic range single-shot fast pulse signal acquisition system of the present invention.

[0056] Figure 2 This is a schematic diagram of the composite pulse train shaping circuit S1 of the present invention;

[0057] Figure 3 This is a schematic diagram of the data acquisition unit of the present invention;

[0058] Figure 4 This is a schematic diagram of the three-part circuit of the present invention;

[0059] Figure 5 This is a schematic diagram of the π-shaped resistor attenuation network of the present invention;

[0060] Figure 6 This is a schematic diagram of the integrated delay line device of the present invention;

[0061] Figure 7 This is a schematic diagram of the signal composition method based on adders according to the present invention;

[0062] Figure 8 This is a schematic diagram of the limiting protection circuit U5 of the present invention;

[0063] Figure 9 This is a schematic diagram of the fast pulse P1 of the present invention;

[0064] Figure 10 This is a schematic diagram of the pulse train P2 of the present invention;

[0065] Figure 11 This is a waveform timing diagram of the present invention, where Trig: trigger signal, P1: fast pulse, P2: pulse train, I1: first branch attenuation pulse, I2: second branch delay pulse, I3: second branch delay pulse, tw: complete duration of a single pulse, ΔtD1: delay time of I2 compared to I1, ΔtD2: delay time of I3 compared to I1, W1: waveform window one, W2: waveform window two, W3: waveform window three, A1: vertical sensitivity of waveform window one, A2: vertical sensitivity of waveform window two, A3: vertical sensitivity of waveform window three, T0: waveform trigger point. Detailed Implementation

[0066] This invention provides a single-channel wide dynamic range single fast pulse signal acquisition system, including a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3; the composite pulse train shaping circuit S1 includes a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4, where N is an integer greater than 1;

[0067] The input terminal of the power divider circuit U1 is used to receive the input fast pulse P1 and divide the input fast pulse P1 into N pulse signals, which are then input into N attenuation circuits U2 respectively.

[0068] N attenuation circuits U2 adjust the gain of N pulse signals respectively, forming N pulses with different gains, which are then input into the corresponding N analog delay circuits U3.

[0069] N analog delay circuits U3 will delay N signals by time T. D1 ... T DN N pulses with different gains are added respectively to generate N phase-separated pulses, which are then input to the input terminals of the composite circuit U4.

[0070] The composite circuit U4 combines N phase-separated pulses into a pulse train P2 and inputs it to the input terminal of the data acquisition unit S2;

[0071] The data acquisition unit S2 is used to digitize the waveform of the pulse train P2 to obtain waveform data; the data acquisition unit S2 and the acquisition and reconstruction unit S3 are interconnected.

[0072] The acquisition and restoration unit S3 is used to extract the sampling results of multiple fast pulses P1 from the digitized waveform data, and obtain sampling waveforms of different ranges according to the calibrated vertical sensitivity and delay time, thereby realizing the large dynamic range acquisition of a single input fast pulse P1.

[0073] Among them, the power divider circuit U1 is a discrete resistor circuit; the attenuation circuit U2 uses an integrated attenuator or a discrete resistor; the analog delay circuit U3 is an analog delay line device; and the composite circuit U4 is a composite pulse train shaper based on the adder principle.

[0074] The power divider circuit U1 includes resistor R1 and resistor R 01 Resistance R 02 ..., resistance R 0N One end of resistor R1 is connected to the fast pulse P1, and the other end is connected to resistor R. 01 Resistance R 02 ..., resistance R 0N One end; resistor R 01 Resistance R 02 ..., resistance R 0N The other end is connected to the input terminals of N attenuation circuits U2 respectively.

[0075] Then, the attenuation circuit U2 includes resistors R5, R6, and R7; one end of resistor R7 is connected to one end of resistor R5, and the other end of resistor R7 is connected to one end of resistor R6; the other end of resistor R5 is grounded, and the other end of resistor R6 is grounded; the ends of resistors R7 and R5 in the N attenuation circuits U2 are respectively connected to resistor R... 01 Resistance R 02 ..., resistance R 0N The other end is connected; the ends of the resistors R7 and R6 of the N attenuation circuits U2 are connected to the input terminals of the N analog delay circuits U3 respectively.

[0076] Next, the analog delay circuit U3 (integrated delay line device) includes resistor R, resistor Rin, resistor Rout, and the analog delay line device; one end of resistor Rin is connected to one end of resistor R, the other end of resistor Rin is connected to the input terminal of the analog delay line device, and the output terminal of the analog delay line device is connected to one end of resistor Rout; the other end of resistor R is grounded, and the other end of resistor Rout is grounded; the end of resistor Rin connected to resistor R is connected to the end of resistor R7 and resistor R6 of the corresponding attenuation circuit U2; the output terminals of the analog delay line devices of N analog delay circuits U3 are respectively connected to the input terminal of the composite circuit U4.

[0077] Finally, the composite circuit U4 includes resistor R C1 Resistance R C2 ..., resistance R CN Resistance R C1 One end, resistor R C2 One end, ..., resistor R CN One end of the resistor is connected to the output of the corresponding analog delay unit; resistor R C1 The other end, resistor R C2 The other end, ..., resistor R CN The other end is connected to serve as the output of the composite circuit U4, and is also connected to the input of the data acquisition unit S2.

[0078] The data acquisition unit S2 in this invention includes a radio frequency (RF) driver, an analog-to-digital converter (ADC), a processor unit, a clock synchronization unit, a storage unit, a trigger unit, an interface unit, and a bias unit. The input terminal of the RF driver is connected to the output terminal of the composite circuit U4. The output terminal of the RF driver is connected to the input terminal of the ADC, and the output terminal of the ADC is connected to the input terminal of the processor unit. The output terminal of the processor unit is connected to the input terminals of both the RF driver and the ADC. The processor unit is communicatively connected to the storage unit and the interface unit. The output terminal of the clock synchronization unit is connected to the ADC, the processor unit, and the storage unit to provide a clock signal. The input terminal of the trigger unit receives an external trigger unit signal (Trig), and its output terminal is connected to the trigger unit input terminal of the processor unit. The output terminal of the bias unit is connected to the input terminal of the RF driver. The interface unit is communicatively connected to the acquisition and restoration unit S3.

[0079] In addition, the composite pulse train shaping circuit S1 also includes a limiting protection circuit U5; the limiting protection circuit U5 includes diodes Q1 and Q2; the anode of diode Q1 and the cathode of diode Q2 are connected to the output terminal of the composite circuit U4; the cathode of diode Q1 is connected to the positive power supply V+, and the anode of diode Q2 is connected to the negative power supply V-.

[0080] The specific implementation method of the present invention will be further described in detail below with reference to the accompanying drawings.

[0081] like Figure 1 The diagram shown is a schematic of the system of the present invention. The system can be divided into three functional parts: a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3. In this embodiment, the acquisition and restoration unit S3 uses host computer acquisition software. The input terminal of the composite pulse train shaping circuit S1 receives a fast pulse P1. The input fast pulse P1 is first spun out and then delayed separately, finally spun into a pulse train P2. Each pulse in the generated pulse train P2 maintains the same waveform as the fast pulse P1, achieving multiple copies of the fast pulse P1 (with consistent waveform shape). Simultaneously, different attenuation circuits U2 can be added to the spun-out circuits to form spun-out pulses with different gains. Therefore, the formed pulse train P2 is not only a multiple waveform copy of the input fast pulse P1 but also consists of multiple pulses with different gains (with consistent waveform shape). The output pulse train P2 of the composite pulse train shaping circuit S1 is connected to the data acquisition unit S2, and is connected to the input terminal of the RF drive unit in the data acquisition unit S2. The data acquisition unit S2 digitizes the waveform of the pulse train P2. Since the pulse train P2 replicates multiple waveforms of the fast pulse P1 with different gains, the data acquisition unit S2 can sample the input fast pulse P1 multiple times. The data acquisition unit S2 uploads the digital waveform to the host computer. The host computer uses acquisition software to extract the sampling results of the multiple fast pulses P1 from the digitized waveform data, and obtains sampling waveforms of different ranges according to the pre-calibrated vertical sensitivity and delay time.

[0082] like Figure 2 As shown, the composite pulse train shaping circuit S1 of the present invention mainly consists of a power divider circuit U1, an attenuation circuit U2, an analog delay circuit U3, a composite circuit U4, and a limiting protection circuit U5. A fast pulse P1 signal is input to the power divider circuit U1, which divides the fast pulse P1 into N outputs. Optionally, the N outputs of the power divider circuit U1 are connected to the inputs (U2-1 to U2-N) of the attenuation circuit U2, and the attenuation coefficient of each output can be independently adjusted by the attenuation circuit U2 (U2-1 to U2-N). Optionally, as shown in the attached diagram... Figure 2 As shown by the dashed lines, when any attenuation circuit U2 does not require attenuation, the power divider output of that path bypasses the attenuation circuit U2 and is directly connected to the downstream analog delay circuit U3. The inputs of the analog delay circuits U3 (U3-1 to U3-N) are connected to the outputs of the attenuation circuits U2 (U2-1 to U2-N), adding a signal delay time (T) to the output signal of each attenuation circuit U2. D1 To T DN Thus, N pulse signals are phase-separated; optionally, as shown in the appendix Figure 2As shown by the dashed line, when the output signal of any attenuation circuit U2 does not require delay, that is, the output signal of that path bypasses the analog delay circuit U3 and is directly connected to the downstream composite circuit U4; the input of the composite circuit U4 is connected to the output of the analog delay circuits U3 (U3-1 to U3-N), which combines N phase-separated pulses into a pulse train P2, and its output is connected to the input terminal of the RF driver of the data acquisition unit S2; optionally, some embodiments also include a limiting protection circuit U5, which is loaded at the output terminal of the composite circuit U4. Since the input signal range of the analog-to-digital converter (ADC) is generally several hundred millivolts to several volts, in order to avoid the influence of high-gain pulses in the pulse train P2 on the sampling of the subsequent ADC, the limiting protection circuit U5 can be used to clamp the high-gain pulses within the limiting voltage range.

[0083] In this embodiment, the power divider circuit U1 divides the input fast pulse P1 signal into N (N≥2) pulse signals. This can be achieved using discrete resistors, or by using an equal-division circuit or an unequal-division circuit. Optionally, a power divider circuit with an impedance of 50Ω is used.

[0084] like Figure 4 The diagram shows an embodiment of a three-way circuit, consisting of resistors R1, R2, R3, and R4; wherein R1 = R2 = R3 = R4 = 24.9Ω, the input resistance and output impedance of the three-way circuit are both 50Ω, one end of resistor R1 is connected to the fast pulse P1 input, the other end of resistor R1 is connected to one end of resistors R2, R3, and R4, and the other end of resistors R2, R3, and R4 serves as the branch output.

[0085] In this embodiment, the attenuation circuit U2 in the branch circuit adjusts the gain of the N pulse signals. The attenuation circuit U2 can be implemented using an integrated attenuator or discrete resistors. An integrated attenuator is preferred, as it can be directly soldered onto the circuit board and has the advantages of small size, high precision, and high reliability. For discrete resistors, a π-shaped network can be used to construct the attenuation circuit U2. Figure 5 As shown, this is an attenuation circuit U2 composed of discrete resistors. Figure 5 As can be seen, one end of resistors R5 and R6 is grounded, and the other ends of resistors R5 and R6 are each connected to one end of resistor R7. The end of resistor R7 connected to resistor R5 can be used as a signal input terminal, and the end of resistor R7 connected to resistor R6 can be used as a signal output terminal. Different attenuation factors can be determined by adjusting the resistance values ​​of resistors R5, R6, and R7. For example, when the attenuation value is 20dB, R7 = 24.7Ω, and R5 = R6 = 61.1Ω. High-precision thick-film high-frequency resistors with a strength of 0.1% are preferred.

[0086] In this embodiment, the analog delay circuit U3 (U3-1 to U3-N) adds a signal delay time (T) to each signal.D1 To T DN ), preferably integrated surface-mount analog delay line devices. For example... Figure 6 As shown, this is an analog delay line device. Figure 6 As can be seen, pin IN is the device input terminal, with resistor Rin and a 50Ω input resistor connected to its front end respectively. Pins T1-T20 are different output terminals of the analog delay line device, representing outputs with different delay times. The delay time gradually reaches the maximum delay time of the analog delay line device from T1 to T20. To achieve signal matching, a resistor Rout is connected between the signal output terminal and ground, where resistor Rin = Rout = Z. line Z line To simulate the impedance of delay line devices. Preferably, Z line =50Ω.

[0087] In this embodiment, the signal delay time t of each branch is... Dn (n is the nth branch, N≥n≥1) The complete duration t of the input fast pulse P1 is given. w Decision. Total duration t w This is the time from when the signal begins to appear and form until it completely disappears into the substrate. To ensure phase separation of the pulses from each branch, a signal delay time t is required for each branch. Dn ≥(n-1)×t w , and t D(n+1) -t Dn ≥t w .

[0088] In this embodiment, the composite circuit U4 combines N phase-separated pulses into a pulse train P2, and its output is connected to the input terminal of the RF driver of the data acquisition unit S2. The acquisition of the fast pulse P1 signal is preferably performed using a GSPS high-speed ADC for analog-to-digital conversion. To obtain a waveform with high dynamic range, a differential amplifier CMRR with high common-mode rejection ratio is preferred as the RF driver. Figure 7 The diagram shows the connection method between the signal composite circuit U4 and the RF driver. From... Figure 7 It can be seen that the differential amplifier CMRR operates in DC-coupled, single-ended input mode. Vocm is the input common-mode voltage, and R... g1 R g2 R is the gain resistor of the differential amplifier. f1 R f2 R is the feedback resistor of the differential amplifier. T1 R T2 RinL is the termination resistor for the differential amplifier, and it is the balancing resistor. To achieve optimal performance of the RF driver, the input needs to be balanced, the transmission line termination matched, and the feedback coefficient matched. Therefore, RinL can be... g1 =R g2R f1 =R f2 R T1 =R T2 The resistance RinL = 50Ω.

[0089] Optional, Figure 7 Chinese R linen R is the output impedance of the shunt analog delay line device. Cn R is the matching compensation resistor in the composite circuit. Cn One end is connected to the preamplifier branch, and the other end is connected to the non-inverting input of the RF driver unit. R can be determined in the following way. Cn Resistance value: To achieve input balance, transmission line termination matching (50Ω signal matching), and reduce signal noise, the resistance value can be adjusted (R... line1 +R C1 ) / / (R line2 +R C2 ) / / … / / (R linen +R Cn )… / / (R linen +R Cn ) = 50Ω, R C1 =R C2 =…=R Cn =…=R CN Therefore, when R linen Once the value is determined, R can be calculated. Cn The resistance value.

[0090] Optionally, the limiting protection circuit U5 clamps the high-gain pulse within the limiting voltage range. See Appendix Figure 8 The limiting protection circuit U5 consists of two diodes, Q1 and Q2. The anode of diode Q1 and the cathode of diode Q2 are connected to the signal link. The cathode of diode Q1 is connected to the positive limiting voltage V+, and the cathode of diode Q2 is connected to the positive limiting voltage V-. When the amplitude of the positive pulse signal exceeds V+, diode Q1 conducts, and the positive pulse voltage is clamped to the positive limiting voltage V+. When the amplitude of the negative pulse signal is lower than V-, diode Q2 conducts, and the negative pulse voltage is clamped to the negative limiting voltage V-.

[0091] In this embodiment, the data acquisition unit S2 digitizes the waveform of the pulse train P2. For example... Figure 3 As shown, the data acquisition unit S2 is similar to the common data acquisition unit system architecture, mainly based on the analog-to-digital converter + processor architecture. The data acquisition unit S2 includes an RF driver unit, an analog-to-digital converter, a processor unit, a clock synchronization unit, a storage unit, a trigger unit, an interface unit, and a bias unit. In this embodiment, the analog-to-digital converter is an analog-to-digital converter.

[0092] The input terminal of the RF driver unit and resistor R C1The other end, resistor R C2 The other end, ..., resistor R CN The other end is connected to the other end; the output of the RF drive unit is connected to the input of the analog-to-digital converter, and the output of the analog-to-digital converter is connected to the input of the processor unit; the output of the processor unit is connected to the input of the RF drive unit and the input of the analog-to-digital converter respectively; the processor unit is interconnected with the storage unit and the interface unit respectively; the output of the clock synchronization unit is connected to the analog-to-digital converter, the processor unit and the storage unit respectively; the input of the trigger unit is used to receive the external trigger unit signal Trig, and its output is connected to the input of the processor unit; the input of the bias unit is connected to the input of the RF drive unit; the interface unit is interconnected with the acquisition and restoration unit S3.

[0093] This embodiment is mainly for single fast pulse P1 applications; therefore, an ADC with a speed of GSPS or higher is preferred. To meet the high-precision quantization requirements, an analog-to-digital converter with a vertical resolution of 12 bits or higher is preferred. In addition, to meet the requirements of high-speed analog-to-digital converter output data processing, a high-performance programmable logic device FPGA of 28nm or higher is preferred as the core processor unit to realize data processing and synchronous control functions. To reduce noise interference, a differential amplifier CMRR with a high common-mode rejection ratio is preferred. To extend the bandwidth to DC, DC coupling and single-ended input are preferred as the connection method between the input signal and the RF drive unit.

[0094] In this embodiment, the host computer's acquisition software extracts multiple fast pulse P1 sampling results from the digitized waveform data and obtains sampling waveforms of different ranges based on the pre-calibrated vertical sensitivity and delay time. This step mainly includes three steps: calibration, waveform acquisition, and waveform extraction. Figure 9 , Figure 10 , Figure 11 The image shows a waveform timing diagram for a single channel with three samples. The workflow of the acquisition software is summarized as follows:

[0095] (1) Calibration. This mainly involves calibrating the vertical sensitivity and delay time of different branch paths. A standard pulse waveform and trigger signal can be output using a standard signal source. The system of this invention directly acquires the waveform to obtain a set of pulse trains corresponding to the branch path pulses. Based on the quantization value of the analog-to-digital converter and the amplitude of the input signal, the vertical sensitivities A1, A2, ..., An, ..., A of different branch paths are obtained. N Then, the same waveform feature point was selected on each pulse train, and the delay time Δt of different branches was measured. Dn (The delay time of the (n+1)th branch compared to the 1st branch), see appendix. Figure 11 .

[0096] (2) Waveform acquisition. A set of pulse train waveform data corresponding to the branch pulses is obtained according to the normal data acquisition unit mode. The waveform recording time needs to be able to cover the entire pulse train.

[0097] (3) Waveform Extraction. This mainly involves extracting the pulses from each branch of the pulse train waveform and saving multiple pulse waveforms based on the calibrated vertical sensitivity and delay time of different branches. The point where the pulse train signal begins is taken as the starting point of the output pulse waveform of the first branch, and its window time W1 = Δt. D1 The window time W2 of the second branch pulse waveform is Δt. D2 -△t D1 The window time W3 of the third branch pulse waveform is Δt. D3 -△t D2 And so on, see appendix. Figure 11 .

[0098] Unlike common high-speed data acquisition unit systems, this invention adds a multi-threshold composite pulse train shaping circuit to the front end of the data acquisition unit. It mainly consists of a power divider circuit U1, an attenuation circuit U2, an analog delay circuit U3, a composite circuit U4, and a limiting protection circuit U5. It can achieve multiple samplings of different ranges in a single channel based on the characteristics of a single fast pulse P1, thereby expanding the system's range coverage and dynamic range.

[0099] Unlike common high-speed data acquisition unit systems, the acquisition software of this invention first operates in normal working mode, acquires pulse trains, and then extracts sampling waveforms of different ranges according to the pre-calibrated vertical sensitivity and delay time.

[0100] Using the method of this invention, a prototype system with a dynamic range of 100dB (2mV-200V) was developed using a 4GSPS, 12-bit vertical resolution high-speed analog-to-digital converter, and three channels (N=3).

Claims

1. A single-channel wide dynamic range single-shot fast pulse signal acquisition system, characterized in that: It includes a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3; The composite pulse train shaping circuit S1 includes a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4, where N is an integer greater than 1. The input terminal of the power divider circuit U1 is used to receive the input fast pulse P1 and divide the input fast pulse P1 into N pulse signals, which are then input into N attenuation circuits U2 respectively. The N attenuation circuits U2 respectively adjust the gain of the N pulse signals to form N pulses with different gains, which are then input into the corresponding N analog delay circuits U3. The N analog delay circuits U3 will delay N signals by time T. D1 ... T DN N pulses with different gains are added to generate N phase-separated pulses, which are then input to the input terminal of the composite circuit U4. The composite circuit U4 combines the N phase-separated pulses into a pulse train P2, which is then input to the input terminal of the data acquisition unit S2. The data acquisition unit S2 is used to digitize the waveform of the pulse train P2 to obtain waveform data; Data acquisition unit S2 and acquisition and reconstruction unit S3 are interconnected. The acquisition and restoration unit S3 is used to extract the sampling results of multiple fast pulses P1 from the digitized waveform data, and obtain sampling waveforms of different ranges according to the calibrated vertical sensitivity and delay time, thereby realizing the acquisition of a large dynamic range of a single input fast pulse P1.

2. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 1, characterized in that: The power divider circuit U1 is a discrete resistor circuit; the attenuation circuit U2 uses an integrated attenuator or a discrete resistor; the analog delay circuit U3 is an analog delay line device; and the composite circuit U4 is a composite pulse train shaper based on the adder principle.

3. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 1 or 2, characterized in that: The power divider circuit U1 includes resistor R1 and resistor R. 01 Resistance R 02 ..., resistance R 0N ; One end of resistor R1 is connected to the fast pulse P1, and the other end is connected to resistor R. 01 Resistance R 02 ..., resistance R 0N One end; The resistor R 01 Resistance R 02 ..., resistance R 0N The other end is connected to the input terminals of N attenuation circuits U2 respectively.

4. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 3, characterized in that: The attenuation circuit U2 includes resistors R5, R6, and R7. One end of resistor R7 is connected to one end of resistor R5, and the other end of resistor R7 is connected to one end of resistor R6; the other end of resistor R5 is grounded, and the other end of resistor R6 is grounded. One end of each of the N attenuation circuits U2 connected to resistors R7 and R5 is respectively connected to resistor R 01 Resistance R 02 ..., resistance R 0N The other end is connected; One end of the resistors R7 and R6 of the N attenuation circuits U2 is connected to the input of the N analog delay circuits U3.

5. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 4, characterized in that: The analog delay circuit U3 includes resistors R, Rin, and Rout, as well as analog delay line devices. One end of resistor Rin is connected to one end of resistor R, the other end of resistor Rin is connected to the input terminal of analog delay line device, and the output terminal of analog delay line device is connected to one end of resistor Rout. The other end of resistor R is grounded, and the other end of resistor Rout is grounded; The end of resistor Rin connected to resistor R is connected to the end of resistor R7 and resistor R6 of the corresponding attenuation circuit U2. The output terminals of the analog delay line devices of the N analog delay circuits U3 are respectively connected to the input terminal of the composite circuit U4.

6. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 5, characterized in that: The composite circuit U4 includes a resistor R C1 Resistance R C2 ..., resistance R CN ; The resistor R C1 One end, resistor R C2 One end, ..., resistor R CN One end of each is connected to the output of the corresponding analog delay unit; The resistor R C1 The other end, resistor R C2 The other end, ..., resistor R CN The other end is connected to serve as the output of the composite circuit U4, and is also connected to the input of the data acquisition unit S2.

7. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 6, characterized in that: The data acquisition unit S2 includes an RF drive unit, an analog-to-digital converter, a processor unit, a clock synchronization unit, a storage unit, a trigger unit, an interface unit, and a bias unit. The input terminal of the radio frequency driving unit is connected to the output terminal of the composite circuit U4; the output terminal of the radio frequency driving unit is connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is connected to the input terminal of the processor unit. The output terminal of the processor unit is connected to the control input terminal of the radio frequency drive unit and the analog-to-digital converter, respectively; the processor unit is also communicatively connected to the storage unit and the interface unit, respectively. The output of the clock synchronization unit is connected to the analog-to-digital converter, the processor unit, and the storage unit, respectively, to provide clock signals. The input terminal of the trigger unit is used to receive the external trigger unit signal Trig, and its output terminal is connected to the trigger unit input terminal of the processor unit. The output of the bias unit is connected to the input of the radio frequency drive unit; The interface unit and the acquisition and restoration unit S3 are interconnected.

8. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 7, characterized in that: The composite pulse train shaping circuit S1 also includes a limiting protection circuit U5; The limiting protection circuit U5 includes diodes Q1 and Q2; the positive terminal of diode Q1 and the negative terminal of diode Q2 are connected and connected to the output terminal of the composite circuit U4. The negative terminal of diode Q1 is connected to the positive power supply V+, and the positive terminal of diode Q2 is connected to the negative power supply V-.

9. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 8, characterized in that: The value of N is 3.

10. The single-channel wide dynamic range single-shot fast pulse signal acquisition system according to claim 9, characterized in that: The impedance of the power divider circuit U1 is 50Ω, and R1 = 24.9Ω; R5=R6=61.1Ω, R7=24.7Ω; The resistor R is 50Ω, and Rin=Rout=Z. line =50Ω, where Z line To simulate the impedance of the delayer; The R C1 =R C2 =R C3 , (R line1 +R C1 ) / / (R line2 +R C2 ) / / (R line3 +R C3 ) = 50Ω, where R line1 R line2 R line3 These represent the output impedances of the corresponding analog delay circuit U3.

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