Gate level snubber circuit based on sic power devices

Abstract

The application relates to a semiconductor device application technology and discloses a gate buffer circuit based on a SiC power device, which comprises a driving unit and a push-pull circuit unit; the push-pull circuit unit is used for buffering the driving current of the driving unit; the push-pull circuit unit comprises a first stabilizer Z1, a second stabilizer Z2, a third stabilizer Z3, a fourth stabilizer Z4, a first triode T1, a second triode T2, a first transistor Q1 and a second transistor Q2. The first stabilizer Z1 and the second stabilizer Z2 are arranged, so that the push-pull (upper P and lower N) through is effectively avoided; thus, excessively high current is not caused; the third stabilizer Z3 and the fourth stabilizer Z4 are designed to adjust the MOSFET gate driving voltage; and the first transistor Q1 and the second transistor Q2 of different current voltage grades are selected to realize the peak current driving capacity of different current grades.

Description

Technical Field

[0001] This invention relates to semiconductor device application technology, and more particularly to gate-level buffer circuits based on SiC power devices. Background Technology

[0002] New energy vehicle motor drivers have a rated power of 200KW or more, requiring modules with a rated current of 400A or more, or a single-transistor parallel scheme for driving. Regardless of the scheme, the driver chip needs to provide extremely strong peak current output capability, generally requiring a peak current capability of 30A or more. However, the current output capability of conventional driver chips on the market is generally within 10A, thus necessitating the construction of external circuitry to achieve the required driving capability.

[0003] For example, application number CN201510431779.7 discloses a circuit using a push-pull output. Existing solutions use push-pull outputs, driven by MOSFETs or transistors with either a P-type upper transistor and an N-type lower transistor, or vice versa. The output signal is in phase with the input signal; that is, a high input level results in a high output level. Analysis shows that when the input is high, the output is Vin - Vth, where Vin is the input PWM signal voltage and Vth is the turn-on voltage of the N-type MOSFET. When the input is low, the output is Vin - Vth, where Vin is the input PWM signal voltage and Vth is the turn-on voltage of the P-type MOSFET. It can be seen that the N-type upper transistor cannot output a full-amplitude voltage. If the input signal voltage amplitude is not high enough, it will lead to excessive Vds voltage in the upper transistor, causing severe overheating. Summary of the Invention

[0004] This invention addresses the problem in existing technologies where insufficient voltage amplitude leads to excessive Vds voltage and severe overheating in the upper transistor, by providing a gate-level buffer circuit based on SiC power devices.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] The gate-level buffer circuit based on SiC power devices includes a driving unit and a push-pull circuit unit. The push-pull circuit unit is used to buffer the driving current of the driving unit. The push-pull circuit unit includes a first voltage regulator Z1, a second voltage regulator Z2, a third voltage regulator Z3 and a fourth voltage regulator Z4, a first transistor T1, a second transistor T2, a first transistor Q1 and a second transistor Q2.

[0007] The base of the first transistor T1 is connected to the reverse terminal of the first voltage regulator Z1; the emitter of the first transistor T1 is connected to the driving forward voltage VDD; the collector of the first transistor T1 is connected to the forward terminal of the third voltage regulator Z3.

[0008] The base of the second transistor T2 is connected to the positive terminal of the first voltage regulator Z2; the emitter of the second transistor T2 is connected to the driving negative voltage VEE; the collector of the second transistor T2 is connected to the reverse terminal of the third voltage regulator Z4.

[0009] The gate of the first transistor Q1 is connected to the reverse terminal of the third regulator Z3, the source of the first transistor Q1 is connected to the driving positive voltage VDD, and the drain of the first transistor Q1 is connected to the SiC power device.

[0010] The gate of the second transistor Q2 is connected to the positive terminal of the third regulator Z4, the source of the second transistor Q2 is connected to the driving negative voltage VEE, and the drain of the second transistor Q2 is connected to the SiC power device.

[0011] Preferably, the push-pull circuit unit further includes a current-limiting resistor R1; one end of the current-limiting resistor R1 is connected to the collector of the first transistor T1 and the positive terminal of the third voltage regulator Z3, and the other end is connected to the collector of the second transistor T2 and the reverse terminal of the third voltage regulator Z4.

[0012] Preferably, the device also includes a drive-on resistor and a drive-off resistor. One end of the drive-on resistor is connected to the drain of the first transistor Q1 and the other end is connected to the SiC power device. One end of the drive-off resistor is connected to the drain of the second transistor Q2 and the other end is connected to the SiC power device.

[0013] Preferably, the voltage regulation value of the first voltage regulator is V. Z1 The voltage regulation value of the second voltage regulator is V. Z2 The voltage regulation value of the third voltage regulator is V. Z3 The voltage regulation value of the fourth voltage regulator is V. Z4 Among them, V Z1 V Z2 V Z3 and V Z4 Both are less than VDD-VEE; and V Z1 -V Z2 and V Z3 -V Z4 Both are greater than VDD-VEE.

[0014] Preferably, a third transistor Q3 is also included; the drain of the third transistor Q3 is connected to the driving unit, the gate of the third transistor Q3 is connected to the collector of the second transistor T2 and the reverse terminal of the third voltage regulator Z4, and the source of the third transistor Q3 is grounded.

[0015] Preferably, the first transistor T1 is a PNP transistor; the second transistor T2 is an NPN transistor.

[0016] Preferably, the first transistor Q1 is a PNP MOSFET and the second transistor Q2 is an NPN MOSFET.

[0017] This invention, by adopting the above technical solutions, has significant technical effects:

[0018] The present invention effectively avoids push-pull (P on top, N on bottom) shoot-through by setting up the first voltage regulator Z1 and the second voltage regulator Z2; thus, it will not lead to excessive current.

[0019] This invention uses the design of a third regulator Z3 and a fourth regulator Z4 to regulate the MOSFET gate drive voltage;

[0020] This invention achieves peak current driving capability at different current levels by selecting a first transistor Q1 and a second transistor Q2 with different current and voltage levels.

[0021] This invention enhances the anti-interference capability of Desat protection by adding a third transistor Q3. Attached Figure Description

[0022] Figure 1 This is the buffer circuit diagram of the present invention;

[0023] Figure 2 This is a circuit diagram of Embodiment 2 of the present invention;

[0024] Figure 3 This is a circuit diagram of Embodiment 3 of the present invention;

[0025] Figure 4 This is a circuit diagram of Embodiment 3 of the present invention;

[0026] Figure 5 This is the upper P and lower N driving circuit diagram of Example 1;

[0027] Figure 6 This is the upper N and lower P driving circuit diagram of Example 1. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0029] Example 1

[0030] This embodiment is illustrated by... Figure 5The MOSFET or transistor driver circuit with P-type upper and N-type lower configuration, as shown in the diagram, has the output signal in phase with the input signal; that is, a high input level results in a high output level. Analysis reveals that when the input is high, the output is Vin - Vth, where Vin is the input PWM signal voltage and Vth is the turn-on voltage of the N-type MOSFET. When the input is low, the output is also Vin - Vth, where Vin is the input PWM signal voltage and Vth is the turn-on voltage of the P-type MOSFET. It can be seen that the N-type upper and P-type lower configuration cannot output a full-amplitude voltage. If the input signal voltage amplitude is not high enough, it will lead to excessively high Vds voltage in the upper MOSFET, causing severe overheating.

[0031] Figure 6 This is a MOSFET or transistor driver circuit with an upper N-phase and lower P-phase input. The output signal is out of phase with the input signal; that is, when the input signal is high, the output is low. When the input signal is between VDD and VEE levels, both the upper and lower transistors may be turned on, causing the transistors to overheat. Therefore, it is necessary to strictly control the amplitude of the input signal and the slew rate.

[0032] Example 2

[0033] Unlike Embodiment 1, this embodiment is a gate-level buffer circuit based on SiC power devices, including a driving unit and a push-pull circuit unit; the push-pull circuit unit is used to buffer the driving current of the driving unit; its push-pull circuit unit includes a first voltage regulator Z1, a second voltage regulator Z2, a third voltage regulator Z3 and a fourth voltage regulator Z4, a first transistor T1, a second transistor T2, a first transistor Q1 and a second transistor Q2;

[0034] The base of the first transistor T1 is connected to the reverse terminal of the first voltage regulator Z1; the emitter of the first transistor T1 is connected to the driving forward voltage VDD; the collector of the first transistor T1 is connected to the forward terminal of the third voltage regulator Z3.

[0035] The base of the second transistor T2 is connected to the positive terminal of the first voltage regulator Z2; the emitter of the second transistor T2 is connected to the driving negative voltage VEE; the collector of the second transistor T2 is connected to the reverse terminal of the third voltage regulator Z4.

[0036] The gate of the first transistor Q1 is connected to the reverse terminal of the third regulator Z3, the source of the first transistor Q1 is connected to the driving positive voltage VDD, and the drain of the first transistor Q1 is connected to the SiC power device.

[0037] The gate of the second transistor Q2 is connected to the positive terminal of the third regulator Z4, the source of the second transistor Q2 is connected to the driving negative voltage VEE, and the drain of the second transistor Q2 is connected to the SiC power device.

[0038] The push-pull circuit unit also includes a current-limiting resistor R1; one end of the current-limiting resistor R1 is connected to the collector of the first transistor T1 and the positive terminal of the third voltage regulator Z3, and the other end is connected to the collector of the second transistor T2 and the reverse terminal of the third voltage regulator Z4.

[0039] The voltage regulation value of the first voltage regulator is V. Z1 The voltage regulation value of the second voltage regulator is V. Z2 The voltage regulation value of the third voltage regulator is V. Z3 The voltage regulation value of the fourth voltage regulator is V. Z4 Among them, V Z1 V Z2 V Z3 and V Z4 Both are less than VDD-VEE; and V Z1 -V Z2 and V Z3 -V Z4 Both are greater than VDD-VEE.

[0040] The first transistor T1 is a PNP transistor; the second transistor T2 is an NPN transistor.

[0041] The first transistor Q1 is a PNP MOSFET, and the second transistor Q2 is an NPN MOSFET.

[0042] pass Figure 1 It can be seen that when PWM_IN is high, the second transistor T2 will be turned on. The corresponding current flows sequentially through the driving positive voltage VDD, the first transistor Q1, the fourth regulator Z3, the current limiting resistor R1, and the second transistor T2, thus turning on the first transistor Q1.

[0043] When PWM_IN is low, the first transistor T1 is turned on, and the corresponding current flows sequentially through the driving positive voltage VDD, the first transistor T1, the current limiting resistor R1, the fourth regulator Z4, and the second transistor Q2. Then the second transistor Q2 is turned on.

[0044] The voltage regulation values ​​of the first regulator Z1 and the second regulator Z2 need to be greater than VDD-VEE. This ensures that the first transistor T1 and the second transistor T2 are both in the off state when there is no input signal. Adjusting the voltage regulation values ​​of the third regulator Z3 and the fourth regulator Z4 can adjust the Vgs voltage of the first transistor Q1 and the second transistor Q2. The current limiting resistor R1 can adjust the switching speed of the first transistor Q1 and the second transistor Q2. The smaller the value of the current limiting resistor R1, the faster the first transistor Q1 and the second transistor Q2 turn on.

[0045] The circuit designed by this invention provides a definite level for the gate (G) and source (S) of the first transistor Q1 and the second transistor Q2, which facilitates driving. Moreover, the positive logic driving is achieved when the input is high and the output is also high.

[0046] Example 2

[0047] Based on Embodiment 1, this embodiment further includes a drive turn-on resistor and a drive turn-off resistor. One end of the drive turn-on resistor is connected to the drain of the first transistor Q1 and the other end is connected to the SiC power device. One end of the drive turn-off resistor is connected to the drain of the second transistor Q2 and the other end is connected to the SiC power device.

[0048] Example 3

[0049] Based on the above embodiments, this embodiment also includes a third transistor Q3; the drain of the third transistor Q3 is connected to the driving unit, the gate of the third transistor Q3 is connected to the collector of the second transistor T2 and the reverse terminal of the third voltage regulator Z4, and the source of the third transistor Q3 is grounded.

[0050] Most driver ICs have a Desat protection function, which means that when the device is in the on state, if the Vds voltage of the MOSFET exceeds the preset value inside the chip, it is considered that the MOSFET has an overcurrent or short circuit, and the PWM wave is immediately turned off to prevent the MOSFET from breaking down.

[0051] Normally, when the input PWM_IN is a shutdown signal, the Desat function does not perform detection. However, because the circuit operates in a complex electromagnetic environment, it is easily interfered with, leading to false triggering and affecting the normal operation of the system. Therefore, a third transistor Q3 is added to this circuit so that the first transistor T1 is turned on when the input signal PWM_IN is low.

[0052] The corresponding current flows sequentially through the driving positive voltage VDD, the first transistor T1, the current-limiting resistor R1, and the third transistor Q3, thus turning on the third transistor Q3; forcibly pulling the Desat pin down to the COM level, enhancing anti-interference capability.

Claims

1. A gate-level buffer circuit based on SiC power devices, comprising a driving unit and a push-pull circuit unit; the push-pull circuit unit is used to buffer the driving current of the driving unit; characterized in that, The push-pull circuit unit includes a first voltage regulator Z1, a second voltage regulator Z2, a third voltage regulator Z3 and a fourth voltage regulator Z4, a first transistor T1, a second transistor T2, a first transistor Q1 and a second transistor Q2; The base of the first transistor T1 is connected to the reverse terminal of the first voltage regulator Z1, and the forward terminal of the first voltage regulator Z1 is connected to the driving unit; the emitter of the first transistor T1 is connected to the driving forward voltage VDD; the collector of the first transistor T1 is connected to the forward terminal of the third voltage regulator Z3 and the reverse terminal of the fourth voltage regulator Z4. The base of the second transistor T2 is connected to the positive terminal of the second voltage regulator Z2, and the reverse terminal of the second voltage regulator Z2 is connected to the driving unit; the emitter of the second transistor T2 is connected to the driving negative voltage VEE; the collector of the second transistor T2 is connected to the reverse terminal of the fourth voltage regulator Z4 and the positive terminal of the third voltage regulator Z3. The gate of the first transistor Q1 is connected to the reverse terminal of the third regulator Z3, the source of the first transistor Q1 is connected to the driving positive voltage VDD, and the drain of the first transistor Q1 is connected to the SiC power device. The gate of the second transistor Q2 is connected to the positive terminal of the fourth regulator Z4, the source of the second transistor Q2 is connected to drive the negative voltage VEE, and the drain of the second transistor Q2 is connected to the SiC power device. It also includes a third transistor Q3; the drain of the third transistor Q3 is connected to the driving unit, the gate of the third transistor Q3 is connected to the collector of the second transistor T2 and the reverse terminal of the fourth voltage regulator Z4, and the source of the third transistor Q3 is grounded.

2. The gate-level buffer circuit based on SiC power devices according to claim 1, characterized in that, The push-pull circuit unit also includes a current-limiting resistor R1; one end of the current-limiting resistor R1 is connected to the collector of the first transistor T1 and the positive terminal of the third voltage regulator Z3, and the other end is connected to the collector of the second transistor T2 and the reverse terminal of the fourth voltage regulator Z4.

3. The gate-level buffer circuit based on SiC power devices according to claim 1, characterized in that, It also includes a drive-on resistor and a drive-off resistor. One end of the drive-on resistor is connected to the drain of the first transistor Q1 and the other end is connected to the SiC power device. One end of the drive-off resistor is connected to the drain of the second transistor Q2 and the other end is connected to the SiC power device.

4. The gate-level buffer circuit based on SiC power devices according to claim 1, characterized in that, The voltage regulation value of the first voltage regulator is V. Z1 The voltage regulation value of the second voltage regulator is V. Z2 The voltage regulation value of the third voltage regulator is V. Z3 The voltage regulation value of the fourth voltage regulator is V. Z4 ; Among them, V Z1 V Z2 V Z3 and V Z4 Both are less than VDD-VEE; and V Z1 -V Z2 and V Z3 -V Z4 Both are greater than VDD-VEE.

5. The gate-level buffer circuit based on SiC power devices according to claim 1, characterized in that, The first transistor T1 is a PNP transistor; the second transistor T2 is an NPN transistor.

6. The gate-level buffer circuit based on SiC power devices according to claim 1, characterized in that, The first transistor Q1 is a PNP MOSFET, and the second transistor Q2 is an NPN MOSFET.

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