Display panel and manufacturing method thereof, and display device

Abstract

The present application discloses a display panel and a manufacturing method thereof, and a display device, and belongs to the field of display technology. Since any first fan-out lead in the display panel is located between two adjacent second fan-out leads, and the area where the plurality of second fan-out leads are located can also be called a fan-out area, therefore, the first fan-out leads are also located in the fan-out area, and the power connection bus in the display panel can be electrically connected to the driver chip through the plurality of first fan-out leads located in the fan-out area. In this way, the current borne by the power connection bus becomes smaller, thereby reducing the width of the power connection bus, and then reducing the width of the non-display area in the display panel, so that the width of the frame of the display panel is reduced, the screen-to-body ratio of the display device prepared using the display panel is improved, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technology, display devices are used more and more widely. Commonly used display devices include smart phones, tablet computers, televisions, monitors, etc.

[0003] The display device may generally include a display panel and a driver chip. The display panel has a display area and a non-display area, and the display panel includes: a plurality of sub-pixels located in the display area, signal lines electrically connected to the plurality of sub-pixels; and leads located in the non-display area. The leads may be electrically connected to the plurality of signal lines and the driver chip, respectively. In this way, the driver chip may control the plurality of sub-pixels through the leads and the plurality of signal lines, so that the display panel can display images.

[0004] However, the width of the non-display area in the current display panel is relatively large, resulting in a low screen-to-body ratio of the display device, which affects the display effect of the display device. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a manufacturing method thereof, and a display device. The display device in the prior art can solve the problem that the screen-to-body ratio of the display device is low, which affects the display effect of the display device. The technical solution is as follows:

[0006] In a first aspect, a display panel is provided, the display panel comprising:

[0007] A substrate, the substrate having a display area and a non-display area located outside the display area;

[0008] a plurality of first power signal lines and a plurality of driving signal lines located in the display area;

[0009] and, a power connection bus, a plurality of first fan-out leads, and a plurality of second fan-out leads located in the non-display area;

[0010] Among them, the power connection bus is electrically connected to the first power signal line and the first fan-out lead respectively, the multiple second fan-out leads are electrically connected to the multiple drive signal lines one by one, one first fan-out lead is located between two adjacent second fan-out leads, and the multiple first fan-out leads and the multiple second fan-out leads are both configured to be electrically connected to the drive chip.

[0011] Optionally, one of the first fan-out leads corresponds to n of the first power signal lines, and the first fan-out lead is configured to apply a first power signal to the corresponding n of the first power signal lines through the power connection bus, where n is an integer greater than or equal to 1.

[0012] Optionally, the number of second connection points distributed on both sides of the first connection point on the power connection bus is the same, wherein the first connection point is the connection point between the first fan-out lead and the power connection bus, and the second connection point is the connection point between the first power signal line corresponding to the first fan-out lead and the power connection bus.

[0013] Optionally, n is equal to 4.

[0014] Optionally, a ratio of a width of the power connection bus to a maximum width of the first fan-out lead ranges from 0.7 to 1.3.

[0015] Optionally, the first power signal line and the power connection bus are set at different layers, and the first fan-out lead includes: a first sub-lead, and a second sub-lead electrically connected to the first sub-lead, the first sub-lead and the first power signal line are set at the same layer, and the second sub-lead and the power connection bus are set at the same layer.

[0016] Optionally, the orthographic projection of the first sub-lead on the substrate is located within the orthographic projection of the second sub-lead on the substrate.

[0017] Optionally, two adjacent second fan-out leads are arranged in different layers, and the orthographic projections of the two adjacent second fan-out leads arranged in different layers on the substrate are staggered.

[0018] Optionally, the plurality of second fan-out leads include: a plurality of third sub-leads arranged in the same layer as the plurality of drive signal lines, and a plurality of fourth sub-leads arranged in a different layer from the plurality of drive signal lines, and the plurality of third sub-leads and the plurality of fourth sub-leads are arranged in an alternating manner.

[0019] Optionally, the display panel further includes: an anti-static structure located in the non-display area, and the anti-static structure is located on a side of the display area away from the power connection bus.

[0020] Optionally, the display panel further comprises: a plurality of columns of pixels located in the display area, one column of the pixels comprising at least two columns of sub-pixels, the plurality of columns of pixels corresponding one-to-one to the plurality of first power signal lines, and the first power signal line being electrically connected to the plurality of sub-pixels in the corresponding column of pixels;

[0021] The multiple driving signal lines include: a plurality of data signal lines corresponding one-to-one to the multiple columns of sub-pixels in the display panel, and a plurality of sensing signal lines corresponding one-to-one to the multiple columns of pixels, the data signal lines are electrically connected to the multiple sub-pixels in a corresponding column of sub-pixels, and the sensing signal lines are electrically connected to the multiple sub-pixels in a corresponding column of pixels.

[0022] Optionally, the display panel also includes: a first connecting line and a second connecting line located in the display area, the first connecting line and the first power signal line are arranged in a different layer, the second connecting line and the sensing signal line are arranged in a different layer, the first power signal line is electrically connected to the plurality of sub-pixels in a corresponding column of pixels through the first connecting line, and the sensing signal line is electrically connected to the plurality of sub-pixels in a corresponding column of pixels through the second connecting line.

[0023] Optionally, the display panel further includes: a second power signal line located in the non-display area, and the second power signal line is located on a side of the display area close to the power connection bus, and the second power signal line is configured to be electrically connected to the driving chip.

[0024] Optionally, the plurality of data signal lines include a plurality of groups of data signal lines, a group of the data signal lines includes two adjacent data signal lines, and one of the first power signal lines or one of the sensing signal lines is arranged between any two adjacent groups of data signal lines.

[0025] Optionally, the drive signal line and the power connection bus are arranged in different layers, and the drive signal line includes: a drive signal line body and a jumper signal line that are connected to each other, the orthographic projection of the jumper signal line on the substrate and the orthographic projection of the power connection bus on the substrate have an overlapping area, and the width of the jumper signal line is greater than the width of the drive signal line body.

[0026] Optionally, an extension direction of the first power signal line is parallel to an extension direction of the drive signal line, and is perpendicular to an extension direction of the power connection bus.

[0027] In a second aspect, a method for manufacturing a display panel is provided, the method comprising:

[0028] Providing a substrate, the substrate having a display area and a non-display area located outside the display area;

[0029] Forming a plurality of first power signal lines and a plurality of driving signal lines in the display area, and forming a power connection bus, a plurality of first fan-out leads and a plurality of second fan-out leads in the non-display area;

[0030] Among them, the power connection bus is electrically connected to the first power signal line and the first fan-out lead respectively, the multiple second fan-out leads are electrically connected to the multiple drive signal lines one by one, one first fan-out lead is located between two adjacent second fan-out leads, and the multiple first fan-out leads and the multiple second fan-out leads are both configured to be electrically connected to the drive chip.

[0031] In a third aspect, a display device is provided, the display device comprising:

[0032] Display panel and driver chip;

[0033] The display panel comprises: the above-mentioned display panel;

[0034] Wherein, the driving chip is electrically connected to a plurality of first fan-out leads and a plurality of second fan-out leads in the display panel.

[0035] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0036] The display panel includes: a substrate, a plurality of first power signal lines, a plurality of drive signal lines, a power connection bus, a plurality of first fan-out leads, and a plurality of second fan-out leads. Since any first fan-out lead in the display panel is located between two adjacent second fan-out leads, and the area where the plurality of second fan-out leads are located can also be called a fan-out area, therefore, the first fan-out leads are also located in the fan-out area, and the power connection bus in the display panel can be electrically connected to the drive chip through the plurality of first fan-out leads located in the fan-out area. In this way, the current borne by the power connection bus becomes smaller, thereby reducing the width of the power connection bus, and then reducing the width of the non-display area in the display panel, so that the width of the frame of the display panel is reduced, the screen-to-body ratio of the display device prepared using the display panel is improved, and the display effect of the display device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a structural schematic diagram of a display device provided by the related technology;

[0039] Figure 2 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0040] Figure 3 yes Figure 2 A partial enlarged view of the display panel at position A is shown;

[0041] Figure 4 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0042] Figure 5 yes Figure 4 A partial enlarged view of the display panel at position B is shown;

[0043] Figure 6 yes Figure 4 A schematic diagram of the film structure of a display panel is shown;

[0044] Figure 7 yes Figure 4 A partial enlarged view of the display panel at position C is shown;

[0045] Figure 8 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0046] Fig. 9 It is a structural schematic diagram of an anti-static structure provided in an embodiment of the present application;

[0047] Fig.10 yes Figure 5 A partial enlarged view of the display panel at position D is shown;

[0048] Fig.11 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0049] Fig.12 It is a rendering of a display device 020 provided by the related art;

[0050] Fig.13 is a rendering of a display device provided in an embodiment of the present application;

[0051] Fig.14 It is a rendering of a spliced ​​screen provided by the relevant technology;

[0052] Fig.15 This is a rendering of a spliced ​​screen provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0054] In related art, please refer to Figure 1 , Figure 11 is a schematic diagram of a display device provided by the related art. The display device may include: a display panel 00 and a driving chip 10. The display panel 00 has a display area 00a and a non-display area 00b. The display panel 00 may include:

[0055] A plurality of sub-pixels (not shown in the figure) located in the display area 00a, a plurality of power signal lines 01 (thick solid lines in the figure) and a plurality of driving signal lines (not shown in the figure) connected to the plurality of sub-pixels.

[0056] Also, a power connection bus 02, two first lead lines 03 and a plurality of second lead lines (not shown in the figure) located in the non-display area 00b.

[0057] The plurality of second leads are electrically connected to the plurality of drive signal lines in a one-to-one correspondence, and the region where the plurality of second leads are located can also be referred to as a fan-out region 00c, and the plurality of second leads are electrically connected to the drive chip 10. The power connection bus 02 is electrically connected to the power signal line 01 and the first lead 03, respectively. The two first leads 03 are located on both sides of the fan-out region 00c, respectively, and the two first leads 03 are electrically connected to the drive chip 10. In this way, the drive chip 10 can apply power signals to the plurality of power signal lines 01 through the two first leads 03 and the power connection bus 02, and apply drive signals to the plurality of drive signal lines through the plurality of second leads, thereby controlling the sub-pixels connected to the plurality of power signal lines 01 and the plurality of drive signal lines, so that the display panel can display.

[0058] In the related art, since the power connection bus 02 is electrically connected to the driving chip 10 only through two first leads 03, the power connection bus 02 needs to bear a large current. As a result, the width of the power connection bus 02 is large, resulting in a large width of the non-display area 00b in the display panel 00, which in turn results in a large border width of the display panel 00. The screen-to-body ratio of the display device prepared using the display panel 00 is low, affecting the display effect of the display device.

[0059] Please refer to Figure 2 , Figure 21 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. The display panel 000 may be an organic electroluminescent (English: Organic Light Emitting Display; referred to as: OELD) display panel, an active matrix organic light emitting diode (English: Active Matrix / Organic Light Emitting Diode; referred to as: AM-OLED) display panel or a liquid crystal display panel. When the display panel 000 is an OELD display panel or an AM-OLED display panel, the display panel 000 may be a top emission display panel or a bottom emission display panel.

[0060] The display panel 000 may include a substrate 100, wherein the substrate 100 has a display area 100a and a non-display area 100b located outside the display area 100a. To more clearly see the structure of the non-display area 100b, please refer to Figure 3 , Figure 3 yes Figure 2 A partial enlarged view of the display panel at point A is shown.

[0061] The display panel 000 may also include: a plurality of first power signal lines 200 (thick solid lines in the figure) and a plurality of drive signal lines 300 (thick dotted lines in the figure) located in the display area 100a, and a power connection bus 400, a plurality of first fan-out leads 500 (thin solid lines in the figure) and a plurality of second fan-out leads 600 (thin dotted lines in the figure) located in the non-display area 100b.

[0062] The power connection bus 400 is electrically connected to the first power signal line 200 and the first fan-out lead 500 respectively, the plurality of second fan-out leads 600 are electrically connected to the plurality of drive signal lines 300 in a one-to-one correspondence, and any first fan-out lead 500 among the plurality of first fan-out leads 500 is located between two adjacent second fan-out leads 600. The plurality of first fan-out leads 500 and the plurality of second fan-out leads 600 are both configured to be electrically connected to the drive chip.

[0063] It should be noted that the number of the first fan-out leads 500 and the second fan-out leads 600 in the display panel 000 is usually several hundred or several thousand, and the number of the second fan-out leads 600 between two adjacent first fan-out leads 500 may be multiple.

[0064] In the present application, since any one of the first fan-out leads 500 is located between two adjacent second fan-out leads 600, and the area where the plurality of second fan-out leads 600 are located can also be referred to as a fan-out area 100c. Therefore, the plurality of first fan-out leads 500 are also located in the fan-out area 100c. The power connection bus 400 in the display panel 000 can be electrically connected to the driver chip through the plurality of first fan-out leads 500 located in the fan-out area 100c. In this way, the current borne by the power connection bus 400 becomes smaller, thereby reducing the width of the power connection bus 400, and then reducing the width of the non-display area 000b in the display panel 000, so that the width of the frame of the display panel 000 is reduced, the screen ratio of the display device prepared using the display panel 000 is improved, and the display effect of the display device is improved.

[0065] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of first power signal lines, a plurality of drive signal lines, a power connection bus, a plurality of first fan-out leads, and a plurality of second fan-out leads. Since any one of the first fan-out leads in the display panel is located between two adjacent second fan-out leads, and the area where the plurality of second fan-out leads are located can also be called a fan-out area, therefore, the first fan-out leads are also located in the fan-out area, and the power connection bus in the display panel can be electrically connected to the drive chip through the plurality of first fan-out leads located in the fan-out area. In this way, the current borne by the power connection bus becomes smaller, thereby reducing the width of the power connection bus, and then reducing the width of the non-display area in the display panel, so that the width of the frame of the display panel is reduced, thereby improving the screen-to-body ratio of the display device prepared using the display panel, and improving the display effect of the display device.

[0066] In the examples of this application, please refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application, Figure 5 yes Figure 4 A partial enlarged view of the display panel at B is shown. In the display panel 000, a first fan-out lead 500 may correspond to n first power signal lines 200, where n is an integer greater than or equal to 1, and the first fan-out lead 500 may be configured to apply a first power signal to the corresponding n first power signal lines 200 through the power connection bus 400. In this way, the number of first fan-out leads 500 located in the non-display area 100b is less than the number of first power signal lines 200 located in the display area 100a, which effectively reduces the number of first fan-out leads 500 located in the non-display area 100b, further reduces the width of the non-display area 100b in the display panel 000, and improves the screen-to-body ratio of the display device prepared using the display panel 000.

[0067] Optionally, for each first fan-out lead 500, the connection point between the first fan-out lead 500 and the power connection bus 400 is a first connection point 400a, and the connection point between the first power signal line 200 corresponding to the first fan-out lead 500 and the power connection bus 400 is a second connection point 400b. The number of second connection points 400b distributed on both sides of each first connection lead 400a on the power connection bus 400 is the same. In this way, the n first power signal lines 200 corresponding to each first fan-out lead 500 are evenly distributed on both sides of the first fan-out lead 500, so that the first power signal applied by the first fan-out lead 500 to the corresponding n first power signal lines 200 through the power connection bus 400 has better uniformity.

[0068] For example, n may be equal to 4, that is, one first fan-out lead 500 corresponds to four first power signal lines 200 .

[0069] In related technologies, such as Figure 1 As shown, since the power connection bus 02 is electrically connected to the driving chip 10 only through two first leads 03 , the power connection bus 02 needs to bear a larger current, and the width of the power connection bus 02 is much larger than the width of the first leads 03 .

[0070] In the present application, since the power connection bus 400 can be electrically connected to the driving chip through a plurality of first fan-out leads 500 in the display panel 000, the current borne by the power connection bus 400 and the first fan-out lead 500 is equal, the width of the power connection bus 400 and the first fan-out lead 500 is approximately equal, and the ratio of the width of the power connection bus 400 to the maximum width of the first fan-out lead 500 is in the range of 0.7 to 1.3. That is, the width of the power connection bus 400 in the present application is smaller than the width of the power connection bus 02 in the related art.

[0071] In the present application, in the fan-out region in the non-display region 000 b of the display panel 000 , the number of second fan-out lead lines 600 between any two adjacent first fan-out lead lines 500 is the same.

[0072] In the examples of this application, please refer to Figure 4 and Figure 6 , Figure 6 yes Figure 4The schematic diagram of the film layer structure of the display panel is shown. In the display panel 000, the first power signal line 200 and the power connection bus 400 are arranged in different layers. The first fan-out lead 500 in the display panel 000 may include: a first sub-lead 501, and a second sub-lead 502 electrically connected to the first sub-lead 501. The first sub-lead 501 and the first power signal line 200 are arranged in the same layer, and the second sub-lead 501 and the power connection bus 400 are arranged in the same layer. In this way, by setting the first sub-lead 501 and the second sub-lead 502 in different layers and connecting to each other, the cross-sectional area of ​​the first fan-out lead 500 can be increased, so that the first fan-out lead 500 has a higher ability to bear current.

[0073] For example, the first sub-lead 501 and the first power signal line 200 are made of the same material, so that the first sub-lead 501 and the first power signal line 200 can be formed by the same patterning process; the second sub-lead 501 and the power connection bus are made of the same material, so that the second sub-lead 501 and the power connection bus 400 can also be formed by the same patterning process. Figure 6 As shown, the display panel 000 may further include: a first conductive layer 101, an insulating layer 102, and a second conductive layer 103 located on the substrate 100 and stacked in a direction vertically and away from the substrate 100. The first conductive layer 101 may include: a second sub-lead 502; the second conductive layer 103 may include: a first sub-lead 501. The insulating layer 102 has a via a, so that the first sub-lead 501 in the first conductive layer 101 can be electrically connected to the second sub-lead 502 in the second conductive layer 102 through the via a.

[0074] Optional, such as Figure 6 As shown, the orthographic projection of the first sub-lead 501 on the substrate 100 is located within the orthographic projection of the second sub-lead 502 on the substrate 100. In this way, the width of the first fan-out lead 500 is reduced, and the width of the non-display area 100b in the display panel 000 is further reduced, thereby improving the screen-to-body ratio of the display device manufactured using the display panel 000.

[0075] In the embodiment of the present application, among the plurality of second fan-out leads 600, any two adjacent second fan-out leads 600 are arranged in different layers, and the orthographic projections of any two adjacent second fan-out leads 600 arranged in different layers on the substrate 100 are staggered. In this way, the distance between the second fan-out leads 600 located in the non-display area 100b can be reduced, and the width of the non-display area 100b in the display panel 000 is further reduced, and when the distance between the second fan-out leads 600 increases, the manufacturing difficulty of the second fan-out routing 600 is reduced. At the same time, since the orthographic projections of the two adjacent second fan-out leads 600 arranged in different layers on the substrate 100 are staggered, the overlap between the two adjacent second fan-out leads 600 is avoided, thereby reducing the capacitance value of the parasitic capacitance generated between the two adjacent second fan-out leads 600, and reducing the degree of influence of the parasitic capacitance on the display effect of the display panel 000.

[0076] Optional, such as Figure 6 As shown, the second fan-out lead 600 in the display panel 000 may include: a plurality of third sub-leads 601 arranged in the same layer as the plurality of drive signal lines 300, and a plurality of fourth sub-leads 602 arranged in different layers from the plurality of drive signal lines 300, and the plurality of third sub-leads 601 and the plurality of fourth sub-leads 602 are arranged in a staggered manner. In this way, any two adjacent second fan-out leads 600 located in the non-display area 100b can be arranged in different layers. For example, the third sub-lead 601 is made of the same material as the first sub-lead 501 and the first power signal line 200, so that the third sub-lead 601, the first sub-lead 501 and the first power signal line 200 can be formed by the same patterning process; the fourth sub-lead 602 is made of the same material as the second sub-lead 502 and the power connection bus 400, so that the fourth sub-lead 602, the second sub-lead 502 and the power connection bus 400 can be formed by the same patterning process. For example, the first conductive layer 101 may further include: a fourth sub-lead 601 ; the second conductive layer 103 may further include: a third sub-lead 601 .

[0077] In this application, if Figure 7 As shown, Figure 7 yes Figure 4A partial enlarged view of the display panel at C is shown. The display panel 000 may also include: a plurality of columns of pixels 800 located in the display area 100a. Since each pixel 800 is composed of at least two sub-pixels 801 arranged in succession, each column of pixels 800 may include at least two columns of sub-pixels 801. The plurality of columns of pixels 800 correspond one-to-one to a plurality of first power signal lines 200, and the first power signal lines 200 are electrically connected to a plurality of sub-pixels 801 in a corresponding column of pixels 800. For example, the plurality of sub-pixels 801 in each pixel 800 may include: at least two of a red sub-pixel, a blue sub-pixel, a green sub-pixel or a white sub-pixel. The embodiment of the present application is schematically illustrated by taking each pixel 800 including a red sub-pixel, a blue sub-pixel, a green sub-pixel and a white sub-pixel as an example.

[0078] The plurality of driving signal lines 300 in the display panel 100 may include: a plurality of data signal lines 301 corresponding one-to-one to the plurality of columns of sub-pixels 801 in the display panel 100, and a plurality of sensing signal lines 302 corresponding one-to-one to the plurality of columns of pixels 800. The data signal lines 301 are electrically connected to the plurality of sub-pixels 801 in the corresponding column of sub-pixels 801. The sensing signal lines 302 are electrically connected to the plurality of sub-pixels 801 in the corresponding column of pixels 800.

[0079] For example, Figure 4 and Figure 7 As shown, the plurality of data signal lines 301 may include a plurality of groups of data signal lines 301 , a group of data signal lines 301 may include two adjacent data signal lines 301 , and a first power signal line 200 or a sensing signal line 302 may be arranged between any two adjacent groups of data signal lines 301 .

[0080] In the examples of this application, please refer to Figure 4 , the display panel 000 may further include: a second power signal line 1100 located in the non-display area 100b, and the second power signal line 1100 is located on the side of the display area 100a close to the power connection bus 400, and the second power signal line 1100 is configured to be electrically connected to the driver chip. In this way, the second power signal line 1100 can be connected to the same driver chip as the first fan-out lead 500 and the second fan-out lead 600, so that there is no need to set another driver chip in other areas of the display panel 000, thereby reducing the width of other non-display areas around the display panel 000 and reducing the width of the overall frame of the display panel 000.

[0081] For example, the second power signal line 1100 can be disposed in the same layer as the power connection bus 400. For example, the power connection bus 400 is made of the same material, so that the second power signal line 1100 and the power connection bus 400 can also be formed by the same patterning process.

[0082] In the embodiment of the present application, each sub-pixel 801 in the display panel 000 may include: a pixel driving circuit and a light-emitting device. For example, the light-emitting device may be an OLED light-emitting device. The OLED light-emitting device may include: an anode, a light-emitting layer, and a cathode arranged in a stacked manner. Figure 8 As shown, Figure 8 Schematic diagram of a pixel driving circuit provided by an embodiment of the present application. The pixel driving circuit may include: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3 and a storage capacitor Cst.

[0083] The pixel driving circuit has: an input terminal D, a first gate scanning input terminal G1, a second gate scanning input terminal G2, a first power terminal VDD, a second power terminal VSS and a sensing signal terminal Sense. The input terminal D is electrically connected to the data signal line 301; the first gate scanning input terminal G1 and the second gate scanning input terminal G2 are electrically connected to two gate lines in the display panel respectively; the first power terminal VDD is electrically connected to the first power signal line 200; the second power terminal VSS is electrically connected to the second power signal line 1100; the sensing signal terminal Sense is electrically connected to the sensing signal line 302.

[0084] Each thin film transistor may include: a first electrode, a second electrode and a gate electrode. The first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of a source electrode and a drain electrode. The first electrode of the first thin film transistor T1 is electrically connected to the first power supply terminal VDD; the second electrode of the first thin film transistor T1 is electrically connected to the anode of the OLED light emitting device L; the gate electrode of the first thin film transistor T1 is electrically connected to the first electrode of the second thin film transistor T2; the second electrode of the second thin film transistor T2 is electrically connected to the input terminal D; the gate electrode of the second thin film transistor T2 is electrically connected to the first gate scanning input terminal G1; the first electrode of the third thin film transistor T3 is electrically connected to the anode of the OLED light emitting device L; the second electrode of the third thin film transistor T3 is electrically connected to the sensing signal terminal Sense; the gate electrode of the third thin film transistor T3 is electrically connected to the second gate scanning input terminal G2; one end of the storage capacitor Cst is electrically connected to the first electrode of the second thin film transistor T2, and the other end is electrically connected to the anode of the OLED light emitting device L; the cathode of the OLED light emitting device L is electrically connected to the second power supply terminal VSS.

[0085] Optionally, the thin film transistor in each pixel driving circuit can be a top gate thin film transistor, a bottom gate thin film transistor, a back channel etched (BCE) thin film transistor or an etch stop layer (ESL) thin film transistor.

[0086] In the embodiment of the present application, the thin film transistor in the pixel driving circuit needs to be shielded by a conductive light-shielding layer to prevent the active layer in the thin film transistor from shifting the voltage threshold when exposed to light.

[0087] Optionally, the material of the conductive light-shielding layer may include: metal materials such as metal aluminum, metal silver, metal molybdenum or alloys.

[0088] In this application, if Figure 7 As shown, the display panel 000 may further include: a first connection line 900 and a second connection line 1000 located in the display area 100a. The first connection line 900 is disposed in a different layer from the first power signal line 200, and the second connection line 1000 is disposed in a different layer from the sensing signal line 302. The first power signal line 200 may be electrically connected to a plurality of sub-pixels 801 in a corresponding column of pixels 800 through the first connection line 900, and the sensing signal line 302 may be electrically connected to a plurality of sub-pixels 801 in a corresponding column of pixels 800 through the second connection line 1000.

[0089] For example, the first connection line 900 is disposed in the same layer as the power connection bus 400, and the second connection line 1000 is disposed in the same layer as the conductive light shielding layer. For example, the first connection line 900 can be made of the same material as the power connection bus 400, so that the first connection line 900 and the power connection bus 400 can also be formed by the same patterning process; the second connection line 1000 can be made of the same material as the conductive light shielding layer, so that the second connection line 1000 and the conductive light shielding layer can be formed by the same patterning process.

[0090] In the examples of this application, please refer to Figure 4 , the display panel 000 may further include: an antistatic structure 700 located in the non-display area 100b, and the antistatic structure 700 is located in the display area 100a away from the power connection bus 400. In this way, the antistatic structure 700 and the power connection bus 400 are respectively located on both sides of the display area 100a in the display panel 000, further reducing the width of the non-display area 100b on one side of the power connection bus 400, thereby reducing the width of the frame of the display panel 000 on the side of the power connection bus 400.

[0091] For example, Fig. 9 As shown, Fig. 9: It is a structural schematic diagram of an anti-static structure provided in an embodiment of the present application. The anti-static structure 700 can be an electrostatic discharge (English: Electro-Static discharg; abbreviated: ESD) diode. The anti-static structure 700 may include: a plurality of ESD diodes corresponding to multiple columns of sub-pixels 801, and each ESD diode 700 may include: a first pole 701, a second pole 702, an active layer 703 and a third pole 704. Among them, the first pole 702 and the second pole 702 are arranged in the same layer, and the first pole 701 and the active layer 703 are arranged in different layers, and the active layer 703 and the third pole 704 are arranged in different layers. The first pole 701 is electrically connected to the data signal line 301 corresponding to the corresponding column of sub-pixels 801, the second pole 702 is electrically connected to the second electrode signal line 1100, and the first pole 701 and the second pole 702 are both electrically connected to the active layer 703.

[0092] When the display panel 000 generates static electricity during use, the static electricity charge is transmitted to the first pole 701 in the ESD diode 700 through the data signal line 301, so that a coupling capacitance is generated between the first pole 701 and the third pole 704. When the charge on the third pole 701 accumulates to the conduction current value of the ESD diode, the third pole 704 can turn on the active layer 703 and release the accumulated static electricity charge to the second power signal line 1100 through the second pole 702, thereby releasing the static electricity generated in the display panel 000 and protecting the display panel 000.

[0093] For example, the first electrode 701 and the second electrode 702 are arranged in the same layer as the driving signal line 300, and the third electrode 704 is arranged in the same layer as the second power signal line 1100. For example, the first electrode 701 and the second electrode 702 are made of the same material as the driving signal line 300, so that the first electrode 701 and the second electrode 702 and the driving signal line 300 can be formed by the same patterning process; the third electrode 704 is made of the same material as the second power signal line 1100, so that the third electrode 704 and the second power signal line 1100 can be formed by the same patterning process.

[0094] In the examples of this application, please refer to Fig.10 , Fig.10 yes Figure 5A partial enlarged view of the display panel at D is shown. The drive signal line 300 and the power connection bus 400 are arranged in different layers, and the drive signal line 300 may include: a drive signal line body 300a and a jumper signal line 300b that are connected to each other. The orthographic projection of the jumper signal line 300b on the substrate 100 has an overlapping area with the orthographic projection of the power connection bus 400 on the substrate 100, and the width of the jumper signal line 300b is greater than the width of the drive signal line body 300a. In this way, when the width of the jumper signal line 300b in the drive signal line 300 that overlaps with the power connection bus 400 is large, the risk of the drive signal line 300 being broken at the overlap with the power connection bus 400 can be effectively reduced.

[0095] Optional, please refer to Figure 5 , the extension direction of the first power signal line 200 in the display panel 000 is parallel to the extension direction of the drive signal line 300, and is perpendicular to the extension direction of the power connection bus 400. In this way, the design and manufacture of the display panel 000 can be facilitated, and the short circuit between the first power signal line 200 and the drive signal line 300 can be avoided. At the same time, the first power signal line 200 can be easily electrically connected to the power connection bus 400.

[0096] It should be noted that a single patterning process in the above embodiment may include: photoresist coating, exposure, development, etching and photoresist stripping.

[0097] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of first power signal lines, a plurality of drive signal lines, a power connection bus, a plurality of first fan-out leads, and a plurality of second fan-out leads. Since any one of the first fan-out leads in the display panel is located between two adjacent second fan-out leads, and the area where the plurality of second fan-out leads are located can also be called a fan-out area, therefore, the first fan-out leads are also located in the fan-out area, and the power connection bus in the display panel can be electrically connected to the drive chip through the plurality of first fan-out leads located in the fan-out area. In this way, the current borne by the power connection bus becomes smaller, thereby reducing the width of the power connection bus, and then reducing the width of the non-display area in the display panel, so that the width of the frame of the display panel is reduced, thereby improving the screen-to-body ratio of the display device prepared using the display panel, and improving the display effect of the display device.

[0098] The present application also provides a method for manufacturing a display panel. The method for manufacturing a display panel is used to manufacture Figure 2 The display panel shown. The manufacturing method of the display panel may include:

[0099] Step A1: providing a substrate, wherein the substrate has a display area and a non-display area located outside the display area.

[0100] Step A2: forming a plurality of first power signal lines and a plurality of driving signal lines in the display area, and forming a power connection bus, a plurality of first fan-out leads and a plurality of second fan-out leads in the non-display area.

[0101] Among them, the power connection bus is electrically connected to the first power signal line and the first fan-out lead respectively, multiple second fan-out leads are electrically connected to multiple drive signal lines one by one, any first fan-out lead is located between two adjacent second fan-out leads, and multiple first fan-out leads and multiple second fan-out leads are configured to be electrically connected to the drive chip.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific principles of the display panel described above can refer to the corresponding contents in the aforementioned embodiment of the structure of the array substrate, and will not be repeated here.

[0103] In summary, the manufacturing method of the display panel provided by the embodiment of the present application, since any one of the first fan-out leads in the display panel is located between two adjacent second fan-out leads, and the area where the multiple second fan-out leads are located can also be called a fan-out area, therefore, the first fan-out leads are also located in the fan-out area, and the power connection bus in the display panel can be electrically connected to the driver chip through the multiple first fan-out leads located in the fan-out area. In this way, the current borne by the power connection bus becomes smaller, thereby reducing the width of the power connection bus, and then reducing the width of the non-display area in the display panel, so that the width of the frame of the display panel is reduced, the screen-to-body ratio of the display device prepared using the display panel is improved, and the display effect of the display device is improved.

[0104] The present application also provides a display device, which can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Fig.11 As stated, Fig.11 010 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device 010 may include: a driver chip 001 and a display panel 000. The display panel 000 may be the display panel in the above embodiment. The driver chip 001 is electrically connected to a plurality of first fan-out leads and a plurality of second fan-out leads in the display panel 000. The driver chip 001 may also be electrically connected to a second power signal line. In the display device 010 provided in the embodiment of the present application, the number of driver chips 001 is two. In other possible implementations, the number of driver chips 001 may be one or more, which is not limited in the embodiment of the present application.

[0105] When the display device is a TV, please refer to Fig.12 and Fig.13 , Fig.12 is a rendering of a display device 020 provided by the related art. Fig.13 010 is a rendering of a display device provided in an embodiment of the present application. Compared with the related art, the frame width of the display device 010 provided in the embodiment of the present application is smaller. In the related art, the frame width of the display device 020 is 10 mm. In the embodiment of the present application, the frame width of the display device 010 is 5 mm. Compared with the related art, the frame width of the display device 010 provided in the embodiment of the present application is reduced by 50%, which effectively improves the display effect of the display device 010.

[0106] The present application also provides a spliced ​​screen, which may include: a plurality of Fig.11 The display device 010 shown. For example, please refer to Fig.14 and Fig.15 , Fig.14 This is a rendering of a splicing screen provided by related technology. Fig.15 This is a rendering of a spliced ​​screen provided in an embodiment of the present application. Since the spliced ​​screen provided in the embodiment of the present application is composed of multiple Fig.10 The display device 010 shown is composed of a small frame width. Therefore, compared with the related art, the width of the splicing seam between any two adjacent display devices of the splicing screen provided by the embodiment of the present application is small, thereby improving the display effect of the splicing screen.

[0107] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0108] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0109] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A substrate, the substrate having a display area and a non-display area located outside the display area; a plurality of first power signal lines and a plurality of driving signal lines located in the display area; and, a power connection bus, a plurality of first fan-out leads, and a plurality of second fan-out leads located in the non-display area; The power connection bus is electrically connected to the first power signal line and the first fan-out lead respectively, the plurality of second fan-out leads are electrically connected to the plurality of drive signal lines in a one-to-one correspondence, one of the first fan-out leads is located between two adjacent second fan-out leads, and the plurality of first fan-out leads and the plurality of second fan-out leads are both configured to: be electrically connected to a drive chip; An extending direction of the first power signal line is parallel to an extending direction of the driving signal line, and is perpendicular to an extending direction of the power connection bus.

2. The display panel according to claim 1, characterized in that: One of the first fan-out leads corresponds to n of the first power signal lines, and the first fan-out lead is configured to apply a first power signal to the corresponding n of the first power signal lines through the power connection bus, where n is an integer greater than or equal to 1.

3. The display panel according to claim 2, characterized in that: The number of second connection points distributed on both sides of the first connection point on the power connection bus is the same, wherein the first connection point is the connection point between the first fan-out lead and the power connection bus, and the second connection point is the connection point between the first power signal line corresponding to the first fan-out lead and the power connection bus.

4. The display panel according to claim 3, characterized in that: Said n is equal to 4.

5. The display panel according to claim 1, characterized in that: A ratio of a width of the power connection bus to a maximum width of the first fan-out lead ranges from 0.7 to 1.

3.

6. The display panel according to claim 1, characterized in that: The first power signal line and the power connection bus are arranged at different layers, the first fan-out lead includes: a first sub-lead, and a second sub-lead electrically connected to the first sub-lead, the first sub-lead and the first power signal line are arranged at the same layer, and the second sub-lead and the power connection bus are arranged at the same layer.

7. The display panel according to claim 6, characterized in that: The orthographic projection of the first sub-lead on the substrate is located within the orthographic projection of the second sub-lead on the substrate.

8. The display panel according to claim 1, characterized in that: Two adjacent second fan-out leads are arranged in different layers, and the orthographic projections of the two adjacent second fan-out leads arranged in different layers on the substrate are staggered.

9. The display panel according to claim 8, characterized in that: The plurality of second fan-out leads include: a plurality of third sub-leads arranged in the same layer as the plurality of drive signal lines, and a plurality of fourth sub-leads arranged in different layers from the plurality of drive signal lines, and the plurality of third sub-leads and the plurality of fourth sub-leads are arranged in an alternating manner.

10. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further includes: an anti-static structure located in the non-display area, and the anti-static structure is located on a side of the display area away from the power connection bus.

11. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further comprises: a plurality of columns of pixels located in the display area, one column of the pixels comprising at least two columns of sub-pixels, the plurality of columns of pixels corresponding to the plurality of first power signal lines one by one, and the first power signal line being electrically connected to the plurality of sub-pixels in the corresponding column of pixels; The multiple driving signal lines include: a plurality of data signal lines corresponding one-to-one to the multiple columns of sub-pixels in the display panel, and a plurality of sensing signal lines corresponding one-to-one to the multiple columns of pixels, the data signal lines are electrically connected to the multiple sub-pixels in a corresponding column of sub-pixels, and the sensing signal lines are electrically connected to the multiple sub-pixels in a corresponding column of pixels.

12. The display panel according to claim 11, characterized in that: The display panel also includes: a first connecting line and a second connecting line located in the display area, the first connecting line and the first power signal line are arranged in a different layer, the second connecting line and the sensing signal line are arranged in a different layer, the first power signal line is electrically connected to the plurality of sub-pixels in a corresponding column of pixels through the first connecting line, and the sensing signal line is electrically connected to the plurality of sub-pixels in a corresponding column of pixels through the second connecting line.

13. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further includes: a second power signal line located in the non-display area, and the second power signal line is located on a side of the display area close to the power connection bus, and the second power signal line is configured to be electrically connected to the driving chip.

14. The display panel according to claim 11, characterized in that: The plurality of data signal lines include a plurality of groups of data signal lines, a group of the data signal lines includes two adjacent data signal lines, and one of the first power signal lines or one of the sensing signal lines is arranged between any two adjacent groups of data signal lines.

15. The display panel according to any one of claims 1 to 9, characterized in that: The driving signal line and the power connection bus are arranged in different layers, and the driving signal line includes: a driving signal line body and a jumper signal line that are connected to each other, and the orthographic projection of the jumper signal line on the substrate and the orthographic projection of the power connection bus on the substrate have an overlapping area, and the width of the jumper signal line is greater than the width of the driving signal line body.

16. A method for manufacturing a display panel, characterized in that: include: Providing a substrate, the substrate having a display area and a non-display area located outside the display area; Forming a plurality of first power signal lines and a plurality of driving signal lines in the display area, and forming a power connection bus, a plurality of first fan-out leads and a plurality of second fan-out leads in the non-display area; The power connection bus is electrically connected to the first power signal line and the first fan-out lead respectively, the plurality of second fan-out leads are electrically connected to the plurality of drive signal lines in a one-to-one correspondence, one of the first fan-out leads is located between two adjacent second fan-out leads, and the plurality of first fan-out leads and the plurality of second fan-out leads are both configured to: be electrically connected to a drive chip; An extending direction of the first power signal line is parallel to an extending direction of the driving signal line, and is perpendicular to an extending direction of the power connection bus.

17. A display device, characterized in that: include: Display panel and driver chip; The display panel comprises: the display panel according to any one of claims 1 to 15; Wherein, the driving chip is electrically connected to a plurality of first fan-out leads and a plurality of second fan-out leads in the display panel.

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