Multi-gate high electron mobility transistor (HEMT) using a tuned recess depth gate to obtain improved device linearity

Abstract

The multi-gate HEMT includes at least two gates (202, 204), wherein at least one gate (204) is recessed by the same depth or a deeper depth in the barrier layer (206) compared to at least one other gate (202). Recessing the gate reduces the thickness of the barrier layer (206) under the gate, which reduces the density of high-mobility carriers in the two-dimensional electron gas layer (2DEG) conduction channel formed at the heterojunction of the barrier layer (206) and the buffer layer (210) under the recessed gate (204). The recessed gate can increase the gate control of the 2DEG conduction channel. The multi-gate HEMT has at least one gate that is recessed by the same depth or a deeper depth into the buffer layer compared to another gate, which forms at least two different turn-on voltages for the different gates. This can achieve an improvement in transconductance linearity and a positive shift in the threshold voltage.

Description

[0001] Priority Claim

[0002] This patent application claims priority to U.S. Non - Provisional Application No. 16 / 844,479, filed on April 9, 2020, entitled "MULTI - GATE HIGH ELECTRON MOBILITY TRANSISTORS (HEMTs) EMPLOYING TUNED RECESS DEPTH GATES FOR IMPROVED DEVICE LINEARITY", which is assigned to the assignee of this application and is hereby incorporated by reference in its entirety. Field of the Invention

[0003] The field of the present disclosure relates to electronic circuits for wireless devices, and more particularly, to high electron mobility transistors (HEMTs) for use in circuit applications such as radio frequency (RF) circuits. Background of the Invention

[0004] High electron mobility transistors (HEMTs) play a crucial role in advanced radio frequency (RF) and microwave applications, including 5G networks, due to their high power and high frequency capabilities. Compared to metal - oxide - semiconductor (MOS) field - effect transistors (FETs) (MOSFETs) in which a conductive channel is formed in a doped region, the conductive channel in a HEMT is formed at the intersection of two materials with different bandgaps arranged in contact with each other. The barrier layer is a wide - bandgap donor - supply layer arranged in contact above the narrow - bandgap channel layer ("buffer layer"). A heterojunction is created at the intersection of the barrier layer and the buffer layer. The conductive channel in a HEMT can be gated to form a two - dimensional electron gas (2DEG) layer, which is a very thin layer with a very high concentration of high - mobility conductive electrons formed at the heterojunction. In the absence of dopant impurities, the 2DEG layer in a HEMT is used to support high - mobility electrons. A HEMT includes a source and a drain having ohmic contacts with opposite ends of the 2DEG conductive channel. Depending on the voltage applied to the gate terminal on the barrier layer of the HEMT, the source and the drain can be conductively coupled to each other via the 2DEG.

[0005] Gallium nitride (GaN) is a commonly used material in HEMTs because GaN offers excellent properties such as high power density, power - added efficiency (PAE), gain, and easy impedance matching, which improve the overall efficiency in RF chains (e.g., RF circuits in wireless devices). Linearity is an important factor in RF amplifiers. Ideally, a FET device would have a constant (linear) transconductance (g m)). To alleviate the burden of 5G amplifier linearization techniques (i.e., methods for making 5G amplifiers operate linearly), at the device level, alternative methods for obtaining improved linearity are provided in HEMTs. Methods for increasing transconductance linearity in conventional GaN HEMTs have included: increasing the gate-to-channel distance, using atomic layer deposition (ALD) to form an aluminum oxide (Al2O3) gate insulator for a metal-insulator-semiconductor HEMT (MISHEMT), and inserting a delta-doped layer in the GaN buffer layer. These methods result in either a reduced range of operation where the transconductance remains approximately linear or a shift of the threshold voltage (V th ) of the HEMT to a more negative voltage, causing the HEMT to operate in depletion mode rather than in the preferred enhancement mode (e-mode). In depletion mode, the 2DEG conductive channel conducts unless conduction is interrupted by gate control. Thus, in depletion mode, the HEMT is typically on, which is a major drawback for safety and circuit design.

[0006] In this regard, Figure 1 FIG. 1 shows a conventional recessed-gate aluminum gallium nitride (AlGaN) / GaN HEMT 100 ("HEMT100"), which operates in e-mode, meaning the transistor is normally off without an applied gate voltage. HEMT 100 includes a barrier layer 102 of AlGaN and a buffer layer 104 of GaN to form a 2DEG conductive channel 106 ("2DEG 106") at the heterojunction 108 where the barrier layer 102 and the buffer layer 104 intersect. The heterojunction 108 and the 2DEG 106 extend in the X-axis direction. The buffer layer 104 is formed on a silicon carbide (SiC) substrate 110. Source 112S and drain 112D are electrically coupled to the 2DEG 106 at opposite ends of the barrier layer 102 in the X-axis direction. Gate 114 is recessed into the barrier layer 102 in the Y-axis direction, and a passivation layer 116 is formed on the surface of the barrier layer 102. Recessing the gate 114 into the barrier layer 102 reduces the thickness of the barrier layer 102 below the gate 114 in the Y-axis direction, causing the Fermi level at the AlGaN / GaN heterojunction 108 to drop below the minimum conduction band of the barrier layer 102. This depletes the 2DEG 106 of high-mobility carriers, creating an opening 118 in the 2DEG 106. The length Lg of the gate 114 in the X-axis direction between the source 112S and the drain 112D determines the size of the opening 118. Recessing the gate 114 shifts the threshold voltage positively, which shifts the operation of the HEMT 100 towards normally-off operation (e-mode). In response to a positive voltage above the threshold voltage being applied to the gate 114, high-mobility carriers are restored to the opening 118, and the depleted 2DEG106 becomes conductive. However, it is difficult to improve Figure 1The linearity of the transconductance of the recessed-gate HEMT 100 therein is negatively affected because the intentionally very small gate-to-channel distance to achieve a more positive threshold voltage reduces the carrier concentration in the 2DEG 106, thus negatively affecting the transconductance linearity. SUMMARY

[0007] Aspects disclosed herein include multi-gate high electron mobility transistors (HEMTs) that employ a tuned recessed depth gate to obtain improved device linearity. In an exemplary aspect, a multi-gate HEMT is provided that includes at least two gates, where at least one of the gates is recessed to the same depth or a greater depth in the barrier layer compared to at least one other gate. Recessing the gate into the barrier layer of the HEMT reduces the thickness of the barrier layer under the gate, thereby reducing the density of high-mobility carriers in the two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of the barrier layer and the buffer layer under the recessed gate. This can shift the threshold voltage of the HEMT, moving the HEMT towards enhancement-mode (e-mode or normally-off) operation. The recessed gate closer to the 2DEG conductive channel can also increase the gate control over the 2DEG conductive channel. In an exemplary aspect disclosed herein, the multi-gate HEMT has at least one gate that is recessed to the same depth or a greater depth into the buffer layer compared to another gate, which, compared to all gates being recessed (e.g., to a smaller depth), allows a smaller barrier layer region to be reduced in thickness. This can achieve a forward shift of the threshold voltage with less (if any) negative impact on the transconductance linearity range in the multi-gate HEMT. The increased transconductance linearity in the multi-gate HEMT means that the transconductance remains closer to the transconductance peak level of the multi-gate HEMT over a larger input voltage range. This is in contrast to a conventional HEMT that includes a single larger recessed gate, where a positive threshold voltage is obtained at the expense of a reduced linear transconductance range.

[0008] The multi-gate HEMT can also include additional gates that are not recessed into the barrier layer. Additionally, the recessed depth of the gates of the multi-gate HEMT can also be tuned for a desired combination of transconductance linearity and forward shift of the threshold voltage. Additionally, the distance between the corresponding gates in the multi-gate HEMT can be adjusted to further tune the threshold voltage and transconductance linearity (GVS). GVS is a measure of the linearity of the transconductance over the gate-source voltage Vg range, which is defined as the voltage range over which the transconductance of the HEMT remains at 80% or higher of the peak transconductance.

[0009] In this regard, in one exemplary aspect, a HEMT is disclosed. The HEMT includes a buffer layer on a substrate, a barrier layer on the buffer layer, and a 2DEG conductive channel at a heterojunction between the lower surface of the barrier layer and the buffer layer. The HEMT further includes a source and a drain each electrically coupled to the 2DEG conductive channel, a first gate including a lower surface directly contacting the barrier layer between the source and the drain, and a second gate between the first gate and the drain, where the second gate includes a second lower surface of the second gate that directly contacts the barrier layer and is recessed into the barrier layer by a certain depth below the lower surface of the first gate. The length of the first gate extends in a direction from the source to the drain, and the length of the second gate extends in this direction.

[0010] In another exemplary aspect, a HEMT is disclosed. The HEMT includes a buffer layer on a substrate, a barrier layer on the buffer layer, and a 2DEG conductive channel at a heterojunction between the lower surface of the barrier layer and the buffer layer. The HEMT further includes a source and a drain each electrically coupled to the 2DEG conductive channel. The HEMT further includes a first gate and a first gate insulator between the lower surface of the first gate and the barrier layer, the first gate including a lower surface on the barrier layer between the source and the drain. The HEMT further includes a second gate between the first gate and the drain, the second gate including a second lower surface that is recessed into the barrier layer to a greater depth than the lower surface of the first gate, and the HEMT further includes a second gate insulator between the second lower surface of the second gate and the barrier layer. The length of the first gate extends in a direction from the source to the drain, and the length of the second gate extends in this direction.

[0011] In another exemplary aspect, a HEMT is disclosed. The HEMT includes a buffer layer above a substrate, a barrier layer above the buffer layer, and a 2DEG conductive channel at a heterojunction between the lower surface of the barrier layer and the buffer layer. The HEMT further includes a source and a drain each electrically coupled to the 2DEG conductive channel. The HEMT further includes a first gate, a second gate, and a third gate, the first gate including a lower surface directly contacting the barrier layer between the source and the drain, the second gate being between the first gate and the drain, the second gate including a second lower surface that directly contacts the barrier layer and is recessed into the barrier layer to a greater depth than the lower surface of the first gate, the third gate being between the second gate and the drain, the third gate including a third lower surface of the third gate that directly contacts the barrier layer and is recessed into the barrier layer to the same or a greater depth as the second lower surface of the second gate in the barrier layer. The length of the first gate extends in a direction from the source to the drain, the length of the second gate extends in this direction, and the length of the third gate extends in this direction.

[0012] In another exemplary aspect, a method of fabricating a HEMT is disclosed. The method includes forming a buffer layer over a substrate. The method further includes disposing a barrier layer over the buffer layer to form a 2DEG conductive channel. The method further includes removing a portion of the barrier layer from the buffer layer at each end of the 2DEG conductive channel. The method further includes forming a source and a drain on the buffer layer at the respective ends of the 2DEG conductive channel from which the portion of the barrier layer has been removed. The method further includes recessing the barrier layer to form a recessed gate location. The method further includes forming a first gate in a first gate location on the barrier layer. The method further includes forming a second gate in the recessed gate location on the barrier layer. The method further includes depositing a passivation layer on the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional side view of a conventional high electron mobility transistor (HEMT) having a single recessed gate for enhancement mode (e-mode) operation;

[0014] Figure 2 is a cross-sectional side view of an exemplary multi-gate HEMT having a tuned recess depth gate, where the multi-gate HEMT includes a first Schottky gate that is recessed into the barrier layer to the same depth or a greater depth compared to a second Schottky gate to increase the linearity of the transconductance of the HEMT and shift the threshold voltage positively;

[0015] Figure 3A and Figure 3B are graphs respectively illustrating simulated drain current and transconductance over a gate voltage range for Figure 1 a conventional HEMT with a single recessed gate in Figure 2 compared to a multi-gate HEMT with two (2) gates having different recess depths (with a first gate-to-gate distance) and another multi-gate HEMT (such as the one in Figure 2 having a second gate-to-gate distance);

[0016] Figure 4A and Figure 4B are graphs respectively illustrating simulated drain current and transconductance over a gate voltage range for three (3) examples of a conventional HEMT and a multi-gate HEMT, each multi-gate HEMT employing two (2) gates, where in this example the second gate has a different gate length;

[0017] Figure 5is a cross-sectional side view of an exemplary multi-gate HEMT that includes a first gate recessed into a barrier layer to the same depth or a greater depth than a second gate, wherein both the first gate and the second gate have an insulating contact with the barrier layer to increase the linearity of the transconductance of the HEMT and shift the threshold voltage positively;

[0018] Figure 6 is a flowchart of an exemplary method for manufacturing a multi-gate HEMT having a tuned recessed depth gate, including Figure 2 and Figure 5 the exemplary multi-gate HEMT in;

[0019] Figures 7A - 7G is a cross-sectional side view of the multi-gate HEMT having a tuned recessed depth gate at various exemplary manufacturing stages of manufacturing according to the manufacturing method in Figure 6 ;

[0020] Figure 8 is a cross-sectional side view of an exemplary triple-gate HEMT having a tuned recessed depth gate, the triple-gate HEMT including three (3) gates, including a first Schottky gate recessed into a barrier layer to the same depth or a greater depth than a second Schottky gate, and a third gate recessed the same depth or a greater depth than the first Schottky gate to increase the linearity of the transconductance of the HEMT and shift the threshold voltage positively;

[0021] Figures 9A - 9B is a graph depicting simulated drain current and transconductance over a gate voltage range for Figure 1 a conventional HEMT in Figure 2 a multi-gate HEMT in (a triple-gate HEMT in which the first gate and the third gate are recessed into its barrier layer to the same depth), and a triple-gate HEMT having a third gate recessed deeper into its barrier layer than the first gate;

[0022] Figure 10 is a block diagram of an exemplary processor-based system that may include a multi-gate HEMT having a tuned recessed depth gate to increase the linearity of the transconductance of the HEMT and shift the threshold voltage positively, including but not limited to Figure 2 , Figure 5 and Figure 8 any multi-gate HEMT in; and

[0023] Figure 11is a block diagram of an exemplary wireless communication device that includes a radio frequency (RF) component formed by an integrated circuit (IC), the integrated circuit including a multi-gate HEMT having a tuned recess depth gate to increase the linearity of the transconductance of the HEMT and shift the threshold voltage positively, including but not limited to Figure 2 , Figure 5 and Figure 8 any of the multi-gate HEMTs in DETAILED DESCRIPTION

[0024] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Aspects disclosed herein include multi-gate high electron mobility transistors (HEMTs) that employ tuned recess depth gates to obtain improved device linearity. In an exemplary aspect, a multi-gate HEMT is provided that includes at least two gates, where at least one of the gates is recessed the same depth or a greater depth in a barrier layer compared to at least one other gate. Recessing a gate into the barrier layer of a HEMT reduces the thickness of the barrier layer under the gate, thereby reducing the density of high-mobility carriers in the two-dimensional electron gas layer (2DEG) conduction channel formed at the heterojunction of the barrier layer and the buffer layer under the recessed gate. This can shift the threshold voltage of the HEMT, moving the HEMT toward enhancement-mode (e-mode or normally-off) operation. The recessed gate closer to the 2DEG conduction channel can also increase the gate control of the 2DEG conduction channel. In the exemplary aspects disclosed herein, the multi-gate HEMT has at least one gate that is recessed the same depth or a greater depth into a buffer layer compared to another gate, which allows a smaller barrier layer region to be reduced in thickness compared to all gates being recessed to a smaller depth. This can achieve a positive shift in the threshold voltage with less (if any) negative impact on the range of transconductance linearity in the multi-gate HEMT. The increased transconductance linearity in the multi-gate HEMT means that the transconductance remains closer to the peak transconductance level of the multi-gate HEMT over a larger input voltage range. This is in contrast to conventional HEMTs that include a single large recessed gate, where a positive threshold voltage is obtained at the expense of a reduced linear transconductance range.

[0026] The multi-gate HEMT may also include additional gates that are not recessed into the barrier layer. Additionally, the recess depth of the gates of the multi-gate HEMT can also be tuned for a desired combination of transconductance linearity and forward shift of the threshold voltage. Further, the distance between the respective gates in the multi-gate HEMT can be adjusted to further tune the threshold voltage and transconductance linearity (GVS). GVS is a measure of the linearity of the transconductance over the gate-source voltage Vg range, which is defined as the voltage range over which the transconductance of the HEMT remains at 80% or higher of the peak transconductance.

[0027] Return reference Figure 1 In the HEMT 100 in, a single gate 114 extends a length Lg in the X-axis direction between the source 112S and the drain 112D, and the gate-source voltage applied to the gate 114 asserts the effect on the 2DEG 106 over the length Lg. Compared with the HEMT 100, in Figure 2 An exemplary HEMT200 including a first gate 202 and a second gate 204 is illustrated in cross-section. The HEMT 200 has two separate gates 202, 204 on the barrier layer 206. The multi-gate structure of the HEMT 200 includes a second gate 204, and the second gate 204 includes a lower surface 204 that is recessed deeper in the Y-axis direction than the lower surface 202 of the first gate 202 BOT deeper lower surface 204 BOT to shift the threshold voltage positively and improve the transconductance linearity of the HEMT 200. With certain recess depths of the combination of the first gate 202 and the second gate 204, the HEMT 200 can achieve enhancement mode (e-mode or normally-off) operation. The length Lg1 of the first gate 202 and the length Lg2 of the second gate 204 are also measured in the X-axis direction between the source 208S and the drain 208D of the HEMT 200, as shown in the cross-section in Figure 2 In the example of the HEMT 200, the length Lg1 of the first gate 202 is equal to the length Lg2 of the second gate 204 (i.e., Lg1 = Lg2), and the total combined length of the first gate 202 and the second gate 204 (i.e., Lg1 + Lg2) is equal to Figure 1 the length Lg of the gate 114 of the HEMT 100 in. In other examples, the length Lg1 of the first gate 202 may not be equal to the length Lg2 of the second gate 204, and the total combined length (Lg1 + Lg2) may be greater than or less than the length of the gate in a single recessed gate HEMT.

[0028] The second gate 204 is recessed into the barrier layer 206 to a second gate depth Lg2_rs such that the lower surface 204 of the second gate 204 BOT is lower than the lower surface 202 of the first gate 202BOT (i.e., more recessed than the lower surface 202 of the first gate 202 BOT . The first gate depth Lg1_rs and the second gate depth Lg2_rs are distances from the upper surface 206 of the barrier layer 206 in the Y-axis direction TOP to the lower surface 202 BOT and 204 BOT respectively. The first gate 202 can be recessed to the first gate depth Lg1_rs below the upper surface 206 of the barrier layer 206, but in the example of TOP , the first gate 202 is not recessed (i.e., Lg1_rs = 0). By adjusting (“tuning”) the first gate depth Lg1_rs and the second gate depth Lg2_rs, a positive shift in the threshold voltage can be achieved. Additionally, by tuning the second gate depth Lg2_rs to a different depth greater than the first gate depth Lg1_rs, the HEMT 200 has a larger linear range of transconductance than the HEMT 100, making the HEMT 200 more attractive for RF applications. Figure 2 Another aspect of tuning the first gate 202 and the second gate 204 refers to the distance Lg12_dist in the X-axis direction between the first gate 202 and the second gate 204 in the direction between the source 208S and the drain 208D. In one example, the distance Lg12_dist can range from 0 micrometers (μm) to 2.0 μm. At the minimum of this range, the first gate 202 and the second gate 204 are in contact with each other and can be connected together, but have different depths Lg1_rs and Lg2_rs. By adjusting the distance Lg12_dist, in combination with tuning the first gate depth Lg1_rs and the second gate depth Lg2_rs, the positive shift in the threshold voltage and the linearity range of the transconductance of the HEMT 200 can be varied.

[0029] Additional details of the first gate 202 and the second gate 204 are presented in the context of the HEMT 200. The first gate 202 and the second gate 204 are each formed of a conductive metal or a metal stack. The lower surface 202

[0030] of the first gate 202 BOT and the lower surface 204 BOTBoth are in direct contact with the barrier layer 206, which is a semiconductor material of aluminum gallium nitride (AlGaN) in the multi-gate HEMT 200. That is, a Schottky contact is formed between the first gate 202 and the barrier layer 206 without any intermediate material. Similarly, a Schottky contact is also formed between the second gate 204 and the barrier layer 206. The Schottky contact (which is a direct metal-semiconductor contact) affects the threshold voltage, leakage current, breakdown voltage, and contact resistance of the HEMT 200. As an example of the composition of the barrier layer 206, the AlGaN barrier layer 206 may have an aluminum (Al) alloy percentage in the range of 20% to 30%.

[0031] The upper surface 206 of the barrier layer 206 TOP and the lower surface 206 BOT extend in the X-axis direction.

[0032] The barrier layer 206 is disposed on a buffer layer 210 of gallium nitride (GaN). As described above, a two-dimensional electron gas layer (2DEG) conductive channel 212 (“2DEG 212”) is formed at a heterojunction 214 where the barrier layer 206 and the buffer layer 210 intersect. The heterojunction 214 is an interface between two layers of dissimilar crystalline semiconductors (i.e., the buffer layer 210 and the barrier layer 206). The barrier layer 206 is a wide-bandgap donor supply layer, and the buffer layer 210 is a narrow-bandgap channel layer. The 2DEG 212 is a very thin layer of highly mobile conductive electrons collected at a high concentration at the heterojunction 214. Below the second gate 204 recessed to the second gate depth Lg2_rs, the thickness T of the barrier layer 206 in the Y-axis direction 204 is thinner than the thickness T of the barrier layer 206 without a gate 206 present. In addition to thinning the barrier layer 206, the recessed second gate 204 closer to the 2DEG 212 increases the control of the second gate 204 over the 2DEG 212. Since the barrier layer 206 is thinner under the second gate 204, the concentration of high-mobility carriers in the 2DEG 212 under the second gate 204 is depleted, thereby creating an opening 216 or gap in the conductivity of the 2DEG 212. The opening 216 causes the HEMT200 to have a normally off state (i.e., non-conductive even when there is a voltage between the source 208S and the drain 208D). However, the opening 216 is wider in the X-axis direction than Figure 1The opening 118 in the 2DEG 106 of the HEMT 100 is small because the length Lg2 of the second gate 204 in the X-axis direction is less than the length Lg of the gate 114. Thus, when a gate-source voltage is applied to the first gate 202 and the second gate 204, they together increase the conductance of the 2DEG 212, which restores the high-mobility carriers to the opening 216 and turns on the HEMT 200. The multi-gate HEMT 200 has a second gate 204 that is recessed into the barrier layer 206 to the same depth or deeper compared to the first gate 202, causing less of the barrier layer 206 to be reduced in thickness, which achieves a positive shift in the threshold voltage without Figure 1 a reduction in the transconductance linearity range (GVS) caused in the HEMT 100. Under the combined action of the first gate 202 and the second gate 204, the linearity of the transconductance of the HEMT 200 increases compared to the transconductance of the HEMT 100 having a single larger recessed gate 114.

[0033] The HEMT 200 remains in the off state unless a gate-source voltage greater than or equal to the threshold voltage is applied. In the HEMT 200, the same gate-source voltage is applied between the first gate 202 and the source 208S as is applied between the second gate 204 and the source 208S. In other examples, different gate-source voltages can be applied to the first gate 202 and the second gate 204. In Figure 2 the HEMT 200, applying the same gate-source voltage to the first gate 202 and the second gate 204 restores the high-mobility carriers to the opening 216 in the 2DEG 212, which forms a conductive channel between the source 208S and the drain 208D and turns on the HEMT 200.

[0034] The buffer layer 210 in the HEMT 200 is GaN to correspond to the AlGaN in the barrier layer 206. The buffer layer 210 is formed on a substrate 218 of silicon carbide (SiC). The HEMT 200 also includes a passivation layer 220 on the upper surface 206 TOP of the barrier layer 206. The term "upper surface" of a layer or structure in the present drawings means the highest surface in the Y-axis direction in the figure, and the "lower surface" means the lowest surface in the Y-axis direction in the figure. The upper surface 206 TOP of the barrier layer 206 extends over most of the barrier layer in the X-axis direction that does not have a gate in the barrier layer 206. The upper surface 200 TOP of the HEMT 200 is planarized (reduced in the Y-axis direction) such that the upper surfaces of the source 208S, the drain 208D, the first gate 202, the second gate 204, and the passivation layer 220 form the upper surface 200 of the HEMT 200TOP .

[0035] Figure 2 An example of the HEMT 200 in [[]] has the following dimensions. Figure 2 The buffer layer 210 in [[]] is approximately 2.0 micrometers (μm) thick. In this document, the term "approximately" with respect to a numerical value indicates a value within a range of plus or minus 10% of that numerical value. Figure 2 The barrier layer 206 in [[]] has a thickness T of approximately 20 nanometers (nm) 206 , but can be anywhere in the range of 15 nm to 40 nm thickness. The lengths Lg1 and Lg2 and the distance Lg12_dist between the first gate 202 and the second gate 204 are all 0.2 μm. However, the distance Lg12_dist can be in the range between 0 μm and 2.0 μm. In another variant discussed below, the lengths Lg1 and Lg2 can each be tuned in the range of approximately 30 nm to approximately 2.0 μm, and the opening 216 will have corresponding dimensions.

[0036] Referring further to the HEMT 200, the first gate 202 is separated from the source 208S by a distance Lgs of 1.0 μm in the X-axis direction and from the drain 208D by a distance Lgd of 2.0 μm in the X-axis direction. However, the distance Lgs can be in the range from one (1) μm to three (3) μm, and the distance Lgd can be in the range from one (1) μm to ten (10) μm. Each of the source 208S and the drain 208D has a width of 0.5 μm in the X-axis direction. As described above, Figure 2 the first gate depth Lg1_rs in [[]] is 0 nm, and the second gate depth Lg2 is 15 nm. The depth Lg1_rs of the first gate 202 can be in the range from 0 nm to the depth Lg2_rs of the second gate 204. The depth Lg2_rs of the second gate 204 can be in the range from a depth greater than the depth Lg1_rs of the first gate 202 to a depth corresponding to the thickness T 206 of [[]]. That is, 0 ≤ Lg1_rs < Lg2_rs ≤ T206.

[0037] Therefore, the lower surface 204 of the second gate 204 BOT can be recessed into the barrier layer 206 by a certain depth such that the lower surface 204 of the second gate 204 BOT is recessed into the barrier layer by a depth that is a certain distance below the upper surface 206 of the barrier layer 206 TOP and this distance is in the range of 5% to 100% of the thickness T of the barrier layer 206 206 For example, if the thickness T of the barrier layer 206 206 is 20 nm, then the lower surface 204 of the second gate 204BOT On the upper surface 206 of the barrier layer 206 TOP The depth of the depression below is in the range of 1.0 nm to 20 nm. Figure 2 The thickness T of the passivation layer 220 in PASS (i.e., from the upper surface 206 of the barrier layer 206 TOP to the upper surface T of the HEMT 200 200 ) is from 50 nm to several micrometers.

[0038] Other material combinations of the barrier layer 206 and the buffer layer 210 of the HEMT 200 include indium aluminum gallium nitride (InAlGaN) / GaN, InAlN / GaN, AlN / GaN, etc.

[0039] Figure 3A is a diagram showing the results of simulations of the HEMT shown, the HEMT including Figure 1 the HEMT 100 in Figure 2 the HEMT 200 in, and the HEMT 200A, the HEMT 200A being the HEMT 200 modified to have a distance Lg12_dist of 0.8 μm between the first gate 202 and the second gate 204. Figure 3A The diagram in shows that the HEMT 200 and the HEMT 200A have a drain current I similar to that of the single-depression gate HEMT 100 in Figure 1 over the range of gate-source voltage Vg. d . Figure 3B The diagram shows the transconductance (g m ) of the HEMT 100, the HEMT 200, and the HEMT 200A, and shows the GVS values (i.e., GVS1, GVS2, and GVS3, respectively) of each of the HEMT 100, the HEMT 200, and the HEMT 200A. GVS is a measure of the transconductance linearity over the range of gate-source voltage Vg. GVS is the voltage range over which the transconductance of the HEMT remains at 80% or more of the peak transconductance of that HEMT. A higher GVS is achieved by a nearly peak-consistent transconductance over a longer range of gate-source voltage Vg, as illustrated by the longer flatter curves in Figure 3B . As shown, the transconductance of the HEMT 200 and the HEMT 200A remains relatively constant over a larger range of gate-source voltage Vg compared to the HEMT 100. In particular, GVS2 of the HEMT 200 is 23% longer than GVS1 of the HEMT 100, and GVS3 of the HEMT 200A is 42% longer than GVS1. That is, in the case of a positive shift in the threshold voltage, the GVS of the multi-gate HEMT 200A is higher than that of Figure 1The HEMT 100 in [the relevant context] is as high as 42%. Therefore, Figure 3A It shows that each of the multi-gate HEMT 200 and HEMT 200A achieves a similar forward shift in the threshold voltage as the single recessed-gate HEMT 100, but Figure 3B It shows that, compared with the HEMT 100, the HEMT 200 and HEMT 200A have a larger transconductance linearity range.

[0040] Figure 4A and Figure 4B is to compare Figure 1 the HEMT 100 in [the relevant context], Figure 2 the multi-gate HEMT 200 in [the relevant context], and the graphs of the simulation results of the dual-gate HEMT200B and 200C. In the HEMT 200, the length Lg2 of the second gate 204 is 0.2 μm. Except for the length Lg2 of the second gate 204, the simulated multi-gate HEMT 200B and 200C are the same as the HEMT 200. In the HEMT 200B, the length Lg2 = 0.5 μm, and in the HEMT 200C, the length Lg2 = 1.0 μm. As Figure 4A and Figure 4B the results in [the relevant context] show, compared with the HEMT 100, the current I d responding to the gate-source voltage Vg of the HEMT 200, 200B, and 200C decreases slightly, but the linear region GVS of the transconductance of the HEMT 200 and HEMT 200B is 23% longer than that of the HEMT 100. The change in GVS in the simulated HEMT 200C is not as significant as the improvement in the HEMT 200B, but it provides data helpful for tuning Figure 2 the various dimensions of the HEMT 200 in [the relevant context].

[0041] Figure 5 is a cross-sectional view of an exemplary HEMT 500 similar to the HEMT 200 in Figure 2 [the relevant context]. The HEMT 500 includes a first gate 502 and a second gate 504. The second gate 504 includes a lower surface 504 BOT , the lower surface 504 BOT is recessed into the barrier layer 506 in the Y-axis direction to a depth that is deeper than the lower surface 502 of the first gate 502 BOTDeeper. The HEMT 500 includes a barrier layer 506, a source 508S, a drain 508D, and a buffer layer 510. As described above, the barrier layer 506 is a wide-bandgap donor supply layer, and the buffer layer 510 is a narrow-bandgap channel layer. A 2DEG conductive channel 512 (“2DEG 512”) is formed at a heterojunction 514 of the barrier layer 506 and the buffer layer 510 that extends in the X-axis direction between the source 508S and the drain 508D. The heterojunction 514 is an interface between the crystal structure of the wide-bandgap barrier layer 506 and the crystal structure of the narrow-bandgap buffer layer 210. An opening 516 is created in the 2DEG 512 under the second gate 504, where the barrier layer 506 is thinner in the Y-axis direction under the second gate 504. When high-mobility carriers return to the opening 516 in response to the gate-source voltages applied to the first gate 502 and the second gate 504, the source 508S and the drain 508D are conductively coupled to each other via the 2DEG 512. In the HEMT 500 (where the second gate 504 is recessed into the buffer layer 506 to the same depth or a greater depth (i.e., in the Y-axis direction) compared to the first gate 502), in the X-axis direction, at a length shorter than Figure 1 the length Lg of the gate 114 of the HEMT 100 in 506 the thickness of the barrier layer 506 decreases, for example, from a thickness T 504 to a thickness T Figure 1 . This achieves a forward shift of the threshold voltage and a relatively smaller (if any) reduction in the range of the transconductance linearity (GVS) compared to the HEMT 100 in

[0042] Compared with Figure 2 the HEMT 200 in TOP the HEMT 500 includes an insulating layer 522 formed on the barrier layer 506 before forming the first gate 502 and the second gate 504. A passivation layer 520 is formed on the insulating layer 522 on the upper surface 506 BOT of the insulating layer 522 on the barrier layer 506. The insulating layer 522 can be formed of one or more of a variety of electrically insulating materials, which can include dielectric materials such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O3), titanium dioxide (TiO2), etc. The insulating layer 522 provides a first gate insulator 524 disposed between the lower surface 502 BOT of the first gate 502 and the barrier layer 506, and provides a second gate insulator 526 disposed between the lower surface 504 Figure 2 of the second gate 504 and the barrier layer 506. Similar to the second gate 204 that is recessed into the barrier layer 206 to a certain depth in Figure 2 the second gate 504 includes a depth of recess into the barrier layer 506 that is deeper than the lower surface 502 of the first gate 502BOT Deep lower surface 504 BOT However, an insulating layer 522 is formed over the barrier layer 506, and the first gate 502 and the second gate 504 are formed over the insulating layer 522. Accordingly, the second gate 504 does not directly contact the barrier layer 506 and thus does not have a Schottky contact with the barrier layer 506. In the case of adding the first gate insulator 524 and the second gate insulator 526, the effect of the voltage applied to the first gate 502 and the second gate 504 on the 2DEG 512 is different from Figure 2 that of the first gate 202 and the second gate 204 in the HEMT 200 in

[0043] Compared with the first gate 502 and the first gate insulator 524, the second gate 504 and the second gate insulator 526 are recessed into the barrier layer 506 to the same depth or a deeper depth. The first gate insulator 524 may be recessed into the barrier layer 506 below the upper surface 506 TOP of the barrier layer 506. However, in the example of Figure 5 , the first gate 502 and the first gate insulator 524 are not recessed into the barrier layer 506. Instead, the first gate insulator 524 is disposed on the upper surface 506 TOP of the barrier layer 506. Since the first gate 502 is formed over the insulating layer 522, the first gate 502 does not directly contact the barrier layer 506 and does not have a Schottky contact with the barrier layer 506. Compared with a similar gate having a Schottky contact, the insulating layer 522 changes the effect asserted by the first gate 502 and the second gate 504 on the 2DEG 512. As described with respect to the HEMT 200 in Figure 2 , by tuning the depth to which the first gate 502 and the second gate 504 are recessed into the barrier layer 506, tuning the distance Lg12_dist between the first gate 502 and the second gate 504, and tuning the lengths Lg1 of the first gate 502 and Lg2 of the second gate 504 in the direction between the source 508S and the drain 508D, the threshold voltage of the HEMT 500 can be shifted to a more positive voltage, and compared with the HEMT 100 having a single recessed gate in Figure 1 , the range over which the transconductance is linear is increased.

[0044] The second gate insulator 526 is recessed in the barrier layer 506 such that the second lower surface 504 of the second gate 504 BOT is recessed into the barrier layer 506 by a distance that is in the range of 5% to 100% of the thickness T BOT of the barrier layer 506 below the upper surface 506 506 of the barrier layer 506.

[0045] Compared withFigure 2 Similar to the HEMT 200 in , in the HEMT 500, the same gate - source voltage is applied between the first gate 502 and the source 208S as is applied between the second gate 504 and the source 508S. In other examples, a gate - source voltage different from that of the second gate 504 can be applied to the first gate 502. The dimensions of the features of the HEMT 500 are the same as or within the same range as those of the HEMT 200 described above. For example, the dimensions of the first gate 502 and the second gate 504 in the HEMT 500 correspond to those of the first gate 202 and the second gate 204 in the HEMT 200. In Figure 5 an example, the length Lg2 of the second gate 504 in the direction from the source 508S to the drain 508D is equal to the length Lg1 of the first gate 502 in this direction. The distance Lg12_dist between the first gate 502 and the second gate 504 in this direction (i.e., from the source 508S to the drain 508D) is equal to the length Lg1 of the first gate 502 in the same direction. Alternatively, the distance Lg12_dist in this direction (from the source 508S to the drain 508D) can be in the range from 0 μm to 2.0 μm. In Figure 5 a non - limiting example, Lg1 = 0.2 μm, Lg2 = 0.2 μm, and Lg12_dist is in the range from 0.2 μm to 0.8 μm. Alternatively, the length Lg2 can be in the range from 0.2 μm to 1.0 μm.

[0046] Figure 6 is a flowchart of a method 600 for manufacturing Figure 2 the HEMT 200 in and Figure 5 the HEMT 500 in . The method 600 will be described below with reference to Figures 7A - 7G the manufacturing stages illustrated in .

[0047] Figure 7A shows a first manufacturing stage 700 for manufacturing the HEMT 200 and the HEMT 500. In the manufacturing stage 700, the method 600 includes forming a buffer layer 210 / 510 (e.g., GaN) extending in the X - axis direction above a substrate 218 / 518 (e.g., SiC), and disposing a barrier layer 206 / 506 above the buffer layer 210 / 510 (i.e., in the Y - axis direction) to form a 2DEG 212 / 512 (block 602).

[0048] Figure 7B illustrates a manufacturing stage 702, including removing a portion of the barrier layer 206 / 506 from the buffer layer 210 / 510 at each end of the 2DEG 212 / 512 (i.e., in the X - axis direction) (block 604).

[0049] Figure 7C Illustrated is manufacturing stage 704, which includes forming source 208S / 508S and drain 208D / 508D (block 606) on buffer layer 210 / 510 at respective ends of the 2DEG 212 / 512 where a portion of the barrier layer 206 / 506 has been removed.

[0050] Figure 7D Illustrated is manufacturing stage 706, which includes recessing the barrier layer 206 / 506 to form a recessed gate location LOC2 (block 608). The gate location LOC1 for the first gate 202 / 502 may or may not be recessed, and the recessed gate location LOC2 is for the second gate 204 / 504. In this regard, recessing the barrier layer 206 / 506 includes thinning the barrier layer 206 / 506 to a thickness T in the Y-axis direction of the barrier layer 206 / 506 206 / T 506 between 0% and 95%. In manufacturing stage 706, if the first gate 202 / 502 is not recessed (e.g., Lg1_rs = 0), the barrier layer 206 / 506 may be recessed in only one gate location LOC2 for the second gate 204 / 504. Alternatively, the barrier layer 206 / 506 may be recessed in a first location for the first gate 202 / 502 (e.g., Lg1_rs > 0), and in a second location deeper than the first location for the second gate 204 / 504 (e.g., Lg2_rs > Lg1_rs). In this regard, the barrier layer 206 / 506 is recessed the same or deeper for the second gate 204 / 504 compared to the first gate 202 / 502. Recessing the barrier layer 206 / 506 in manufacturing stage 706 also determines the length Lg1 of the first gate 202 / 502 and the length Lg2 of the second gate 204 / 504 in the direction between the source 208S / 508S and the drain 208D / 508D.

[0051] Figure 7E Illustrated is an optional manufacturing stage 708, which is included in the manufacture of the HEMT 500 in Figure 5 but not included in the manufacture of the HEMT 200 in Figure 2 Manufacturing stage 708 includes forming an insulating layer 522 on the barrier layer 506 (block 610). The insulating layer 522 is formed on the upper surface 506 of the barrier layer 506 TOPabove and formed in gate positions LOC1, LOC2 that are recessed for the first gate 502 and the second gate 504. If the optional manufacturing stage 708 is performed to form the HEMT 500, taking into account the thickness T of the insulating layer 522 deposited on the horizontal (X-axis direction) and vertical (Y-axis direction) surfaces of the positions LOC1, LOC2 during the manufacturing stage 708 INS , the amount of material removed from the gate positions LOC1, LOC2 during the manufacturing stage 706 increases in both the X-axis direction and the Y-axis direction. In other words, the depth of the recessed positions LOC1, LOC2 during the manufacturing stage 706 for the HEMT 200 only includes the recess required for the gate to be in direct contact with the barrier layer 206 (i.e., having a Schottky contact), but the depth of the recessed positions LOC1, LOC2 for the HEMT 500 includes the thickness T of the insulating layer 522 in addition to the recesses for the first gate 502 and the second gate 504 INS .

[0052] Figure 7F Illustrates the manufacturing stage 710. The manufacturing stage 710 includes forming the first gate 202 / 502 in the first gate position LOC1 on the barrier layer 206 / 506, and forming the second gate 204 / 504 in the recessed gate position on the barrier layer 206 / 506 (block 612). When manufacturing the HEMT 200, the manufacturing stage 710 includes forming the first gate 202 directly on the upper surface 206 TOP of the barrier layer 206 or directly on the barrier layer 206 in the first etching position LOC1. At this point, the manufacturing stage 710 will include forming the second gate 204 directly on the barrier layer 206 in the deeper recessed position LOC2. When manufacturing the HEMT 500, the manufacturing stage 710 may include forming the first gate 502 on the first gate insulator 524 on the upper surface 506 TOP of the barrier layer 506 or where the gate position LOC1 is recessed (not shown). At this point, the manufacturing stage 710 will also include forming the second gate 504 on the second gate insulator 526 in the deeper recessed position LOC2 in the barrier layer 506 (see Figure 5 ).

[0053] Figure 7G Illustrates the manufacturing stage 712. The manufacturing stage 712 includes depositing a passivation layer 220 / 520 on the barrier layer 206 / 506 (block 614). The passivation layer 220 / 520 protects the upper surface 206 TOP / 506 TOPInitially, the thickness of the passivation layer 220 / 520 may cover the first gate 202 / 502 and the second gate 204 / 504. Subsequently, the passivation layer 220 / 520 may be planarized (i.e., reduced in the Y-axis direction) to expose the source 208S / 508S, the drain 208D / 508D, the first gate 202 / 502, and the second gate 204 / 504 for connection to a circuit.

[0054] Figure 8 is similar to Figure 2 FIG. 800 is a cross-sectional view of an exemplary HEMT 800 similar to the HEMT 200 in FIG. 200, the HEMT 800 including a first gate 802 and a second gate 804, the second gate 804 including a lower surface 804 that is recessed into the barrier layer 806 to a depth deeper than the lower surface of the first gate 802 BOT However, the HEMT 800 further includes a third gate 808 that is recessed into the barrier layer 806 to the same depth as or deeper than the depth of the lower surface of the second gate 804. In the HEMT 800, the second gate 804 and the third gate 808 are recessed such that the barrier layer 806 has a thickness T below the second gate 804 804 and has a thickness T below the third gate 808 808 The thickness T 804 and T 808 are thinner in the Y-axis direction than the thickness T of the barrier layer 806 806 The thinner barrier layer 806 below the second gate 804 and the third gate 808 depletes the high-mobility carriers in the 2DEG conductive channel 810, creating openings 812A and 812B. By applying a gate-source voltage higher than the voltage threshold to the first gate 802, the second gate 804, and the third gate 808, a 2DEG conductive channel 810 is formed between the source 814S and the drain 814D. According to the voltage difference between the source 814S and the drain 814D, when a gate-source voltage higher than the threshold voltage is applied to the HEMT 800, current will flow in the 2DEG conductive channel 810.

[0055] Regarding additional structural features of the HEMT 800, the barrier layer 806 is disposed on the buffer layer 816, and the buffer layer 816 is disposed on the substrate 818. A passivation layer 820 is formed on the upper surface 806 of the barrier layer 806 TOP on. As compared with Figure 2 the HEMT 200 in FIG. 200 and Figure 5Similar to the HEMT 500 in [reference], the distance between the first gate 802 and the second gate 804 is Lg12_dist. The dimensions of the features of the HEMT 800 correspond to those of the similar features in the HEMT 200 and the HEMT 500. In the HEMT 800, the distance Lg23_dist between the second gate 804 and the third gate 808 is equal to Lg12_dist. In Figure 8 the example of [reference], the distance Lg12_dist is equal to the distance Lg23_dist and both are at 0.2μm or approximately 0.2μm. However, the distance Lg12_dist and the distance Lg23_dist are not limited to being equal, and each can be in the range of 0μm to 2.0μm. The distance Lgs between the first gate 802 and the source 814S is in the range of one (1)μm to three (3)μm, and the distance Lgd between the first gate 802 and the drain 814D is in the range of one (1)μm to ten (10)μm. The length Lg2 of the second gate 804 in the direction between the source 814S and the drain 814D is equal to the length Lg1 of the first gate 802 in this direction, and the length Lg3 of the third gate 808 in this direction is equal to the length Lg2. The lengths Lg1, Lg2, and Lg3 are each at 0.2μm or approximately 0.2μm, but each can be tuned to any length in the range from 300nm to 2.0μm to obtain the desired threshold voltage shift and transconductance linearity. Additionally, the depths Lg1_rs, Lg2_rs, and Lg3_rs to which the lower surfaces of the first gate 802, the second gate 804, and the third gate 808 are recessed below the upper surface of the barrier layer 806 can be in the range up to a depth equal to the thickness T 806 of the barrier layer 806.

[0056] In Figure 8 the example of [reference], the lower surface 802 BOT of the first gate 802 TOP is in direct contact with the upper surface 806 BOT of the barrier layer 806, but the lower surface 802 TOP of the first gate 802 806 can be recessed into the barrier layer 806 to a certain depth below the upper surface 806 PASS of the barrier layer 806. In one example, in the barrier layer 806 with a thickness T Figure 2 of 20nm, Lg2_rs can be up to 16nm, Lg3_rs can be up to 18nm, and Lg1_rs is less than Lg2_rs. In this example, the buffer layer 816 has a thickness of 2.0μm, and the passivation layer 820 has a thickness T PASS ranging from 50nm to several microns. The composition of the barrier layer 806 can vary as described for the barrier layer 206 in Figure 2 [reference].

[0057] The HEMT 800 includes a buffer layer 816 on a substrate 818, a barrier layer 806 on the buffer layer 816, and a 2DEG conductive channel 810 at a heterojunction 822 between the buffer layer 816 and a lower surface 806 of the barrier layer 806. The HEMT 800 includes a source 814S and a drain 814D each electrically coupled to the 2DEG conductive channel 810. The HEMT 800 includes a first gate 802, a second gate 804, and a third gate 808. The first gate 802 includes a bottom surface 802 in direct contact with the barrier layer 806 between the source 814S and the drain 814D. BOT The second gate 804 is between the first gate 802 and the drain 814D, and a lower surface 804 of the second gate 804 BOT is in direct contact with the barrier layer 806 and is recessed into the barrier layer 806 by a certain depth below a lower surface 802 of the first gate 802. BOT The third gate 808 is in direct contact with the barrier layer 806 between the second gate 804 and the drain 814D, and a lower surface 808 of the third gate 808 BOT is recessed into the barrier layer 806 by a certain depth, which is the same as or deeper than a depth of the lower surface 804 of the second gate 804 BOT in the barrier layer 806. BOT The second lower surface 804 of the second gate 804

[0058] and the third lower surface 808 of the third gate 808 BOT are recessed into the barrier layer 806 by a certain distance below an upper surface 806, and each distance has a range of 5% to 100% of a thickness T of the barrier layer 806. BOT In TOP and 806 the simulation results of the HEMT 800 with Lg2_rs = Lg3_rs = 15 nm and the simulation results of another HEMT 800A with Lg2_rs = 15 nm and Lg3_rs = 18 nm are illustrated together with the simulation results of the single recessed gate HEMT 100 in

[0059] and the simulation results of the HEMT 200 in Figure 9A and Figure 9B . The dimensions of other features of the HEMT 800 and the HEMT 800A correspond to the same features in the HEMT 200 in Figure 1 . Figure 2 As shown in Figure 2 , although the current output I of the simulation of the HEMT 800A at any input voltage Vg

[0060] is not the current I of the other simulations Figure 9A . d ​d So high, but compared with other examples, the simulation of HEMT 800A has a significantly more positive threshold voltage. However, Figure 9B It is shown that the transconductance linear range of HEMT 800A is only 14% longer than that of the Figure 1 depleted-gate HEMT 100 in

[0061] In contrast, HEMT 800 has approximately the same threshold voltage as HEMT 100, but has a 37% longer GVS. The dimensions of the HEMT 800 discussed above can all be varied to tune the HEMT 800 to the desired combination of a positive threshold voltage shift and a linear transconductance range. The multi-gate HEMT with a gradually deeper depleted gate has a significant advantage in improving device linearity without negatively affecting the threshold voltage. Like the Figure 2 and Figure 5 multi-gate HEMT 200 and multi-gate HEMT 500 in Figure 8 the three-gate HEMT 800 in m has a flatter transconductance (g m ) over a wider gate-source voltage range compared with the single depleted-gate HEMT, Figure 1

[0062] As in Figure 2 , Figure 5 and Figure 8 to allow a high output current over a larger input voltage range. Simulations have shown up to a 42% improvement in transconductance linearity (i.e., GVS) compared with the Figure 1 HEMT 100 in Moreover, the transconductance flatness and the threshold voltage are tunable by using multiple gates with an increasing depleted depth from the source-side gate to the drain-side gate, which provides great freedom for various circuit design purposes (such as different threshold voltage or operating frequency requirements) in designing high-linearity GaN HEMTs.A HEMT as shown in any of and according to any aspect disclosed herein can be provided in or integrated into any processor-based device. The HEMT includes a multi-gate structure, wherein at least one gate is recessed a different depth in the barrier layer compared to another gate to move the threshold voltage positively and improve the linearity of the transconductance of the HEMT over a gate-source voltage range. Examples include but are not limited to: set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer displays, televisions, tuners, radio transceivers, satellite broadcasts, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-axis aircraft.

[0063] In this regard, Figure 10 FIG. illustrates an example of a processor-based system 1000, where the system 1000 includes a HEMT as shown in any of Figure 2 , Figure 5 and Figure 8 and according to any aspect disclosed herein. The HEMT includes a multi-gate structure, wherein at least one gate is recessed a different depth in the barrier layer compared to another gate to move the threshold voltage positively and improve the linearity of the transconductance of the HEMT over a gate-source voltage range. In this example, the processor-based system 1000 includes one or more central processing units (CPUs) 1002. The central processing unit can also be referred to as a CPU or a processor core. Each CPU or processor core includes one or more processors 1004. The CPU 1002 can have a cache memory 1006, and the cache memory 1006 is coupled to the processor 1004 for fast access to temporarily stored data. As an example, the processor 1004 can include such as Figure 2 , Figure 5 and Figure 8A HEMT as shown in any of the foregoing and according to any aspect disclosed herein, the HEMT includes a multi-gate structure in which at least one gate is recessed to a different depth in the barrier layer than another gate to shift the threshold voltage positively and improve the linearity of the transconductance of the HEMT over the gate-source voltage range. The CPU 1002 is coupled to the system bus 1008 and can couple the master devices and slave devices included in the processor-based system 1000 to each other. As is well known, the CPU 1002 communicates with these other devices by exchanging address information, control information, and data information on the system bus 1008. For example, the CPU 1002 can transmit a bus transaction request to the memory controller 1010, which is an example of a slave device. Although Figure 10 Although not shown in the figure, multiple system buses 1008 may be provided, each of which constitutes a different structure.

[0064] Other master devices and slave devices may be connected to the system bus 1008. Figure 10 As shown in , as an example, these devices may include a memory system 1012 (the memory system 1012 includes a memory controller 1010 and a memory array 1014), one or more input devices 1016, one or more output devices 1018, one or more network interface devices 1020, and one or more display controllers 1022. Each of the memory system 1012, one or more input devices 1016, one or more output devices 1018, one or more network interface devices 1020, and one or more display controllers 1022 may include the following: Figure 2 , Figure 5 and Figure 8 A HEMT as shown in any of the above and according to any aspect disclosed herein, the HEMT includes a multi-gate structure in which at least one gate is recessed in the barrier layer to a different depth than another gate to shift the threshold voltage positively and improve the linearity of the transconductance of the HEMT over the gate-source voltage range. The input device 1016 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 1018 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 1020 may be any device configured to allow data to be exchanged to and from the network 1024. The network 1024 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM Networks and the Internet. The network interface device 1020 may be configured to support any type of communication protocol desired.

[0065] The CPU 1002 can also be configured to access the display controller 1022 via the system bus 1008 to control the information sent to one or more displays 1026. The display controller 1022 sends information to the displays 1026 for display via one or more video processors 1028, and the video processors 1028 process the information to be displayed into a format suitable for the displays 1026. The displays 1026 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light emitting diode (LED) display, etc. The display controller 1022, the displays 1026, and / or the video processors 1028 can include HEMTs as shown in any one of Figure 2 , Figure 5 and Figure 8 and according to any aspect disclosed herein. The HEMT includes a multi-gate structure, wherein at least one gate is recessed to a different depth in the barrier layer compared to another gate to shift the threshold voltage positively and improve the linearity of the transconductance of the HEMT over a gate-source voltage range.

[0066] Figure 11 An exemplary wireless communication device 1100 including a radio frequency (RF) component formed by an integrated circuit (IC) 1102 is illustrated, wherein any component in the wireless communication device 1100 can include HEMTs as shown in any one of Figure 2 , Figure 5 and Figure 8 and according to any aspect disclosed herein. The HEMT includes a multi-gate structure, wherein at least one gate is recessed to a different depth in the barrier layer compared to another gate to shift the threshold voltage positively and improve the linearity of the transconductance of the HEMT over a gate-source voltage range. As an example, the wireless communication device 1100 can include any of the above devices or be provided in any of the above devices. As shown in Figure 11 , the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 can include a memory for storing data and program code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 that support two-way communication. Generally, the wireless communication device 1100 can include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the transceiver 1104 can be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0067] The transmitter 1108 or the receiver 1110 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted in multiple stages between RF and baseband. For example, for the receiver 1110, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. The superheterodyne conversion architecture and the direct conversion architecture can use different circuit blocks and / or have different requirements. In Figure 11 the wireless communication device 1100, the transmitter 1108 and the receiver 1110 are implemented using a direct conversion architecture.

[0068] In the transmit path, the data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1112(1), 1112(2) for converting the digital signals generated by the data processor 1106 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0069] Within the transmitter 1108, low-pass filters 1114(1), 1114(2) filter the I and Q analog output signals respectively to remove the unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from the low-pass filters 1114(1), 1114(2) respectively and provide I and Q baseband signals. The upconverter 1118 upconverts the I and Q baseband signals by mixers 1120(1), 1120(2) using the I and Q transmit (TX) local oscillator (LO) signals from the TX LO signal generator 1122 to provide an upconverted signal 1124. The filter 1126 filters the upconverted signal 1124 to remove the unwanted signals caused by the frequency upconversion and the noise in the receive band. The power amplifier (PA) 1128 amplifies the upconverted signal 1124 from the filter 1126 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1130 and transmitted via the antenna 1132.

[0070] In the receive path, antenna 1132 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1130 and provided to low noise amplifier (LNA) 1134. The duplexer or switch 1130 is designed to operate at a specific receive (RX) to TX duplexer frequency separation to isolate the RX signal from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Downconversion mixers 1138(1), 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 1142(1), 1142(2) and further filtered by low pass filters 1144(1), 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) for converting the analog input signals into digital signals for further processing by data processor 1106.

[0071] In Figure 11 wireless communication device 1100, TX LO signal generator 1122 generates I and Q TX LO signals for frequency upconversion, while RX LO signal generator 1140 generates I and Q RX LO signals for frequency downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. TX phase locked loop (PLL) circuit 1148 receives timing information from data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from TX LO signal generator 1122. Similarly, RX PLL circuit 1150 receives timing information from data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from RX LO signal generator 1140.

[0072] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithmic steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or other computer-readable medium and executed by a processor or other processing device, or combinations of both. By way of example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0073] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0074] Aspects disclosed herein can be embodied in hardware and instructions stored in hardware, and can reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0075] It should also be noted that the operational steps described in any of the exemplary aspects herein are provided for example and discussion. The described operations may be performed in many different orders other than the illustrated order. Additionally, the operations described in a single operational step may actually be performed in many different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications to the operational steps illustrated in the flowcharts will be apparent to those skilled in the art. Those skilled in the art will also understand that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0076] The foregoing description of the disclosure is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0077] In the following, additional examples of the disclosure are provided:

[0078] 1. A high electron mobility transistor (HEMT) comprising:

[0079] A buffer layer above a substrate;

[0080] A barrier layer above the buffer layer;

[0081] A two-dimensional electron gas layer (2DEG) conductive channel at a heterojunction between a lower surface of the barrier layer and the buffer layer;

[0082] A source and a drain, each electrically coupled to the 2DEG conductive channel;

[0083] A first gate including a lower surface in direct contact with the barrier layer between the source and the drain, the length of the first gate extending in a direction from the source to the drain; and

[0084] A second gate between the first gate and the drain, the second gate including a second lower surface in direct contact with the barrier layer and recessed into the barrier layer to a greater depth than the lower surface of the first gate, and the length of the second gate extending in the direction.

[0085] 2. The HEMT according to example 1, wherein the barrier layer includes an upper surface.

[0086] 3. The HEMT according to Example 2, wherein the lower surface of the first gate is in direct contact with the upper surface of the barrier layer.

[0087] 4. The HEMT according to Examples 2-3, wherein the lower surface of the first gate is recessed into the barrier layer below the upper surface of the barrier layer.

[0088] 5. The HEMT according to any one of Examples 2-4, wherein:

[0089] the thickness of the barrier layer is the distance between the upper surface of the barrier layer and the lower surface of the barrier layer; and

[0090] the depth to which the second lower surface of the second gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer.

[0091] 6. The HEMT according to any one of Examples 1-5, wherein the length of the second gate is equal to the length of the first gate.

[0092] 7. The HEMT according to any one of Examples 1-6, wherein the length of the first gate and the length of the second gate are each in the range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

[0093] 8. The HEMT according to any one of Examples 1-7, wherein in the direction, the distance from the first gate to the second gate is equal to the length of the first gate.

[0094] 9. The HEMT according to any one of Examples 1-8, wherein in the direction, the distance between the first gate and the second gate is in the range between 0 μm and 2.0 μm.

[0095] 10. The HEMT according to Example 6, wherein:

[0096] the length of the first gate and the length of the second gate are each approximately 0.2 micrometers (μm); and

[0097] in the direction, the distance between the first gate and the second gate is in the range from 0.2 μm to 0.8 μm.

[0098] 11. The HEMT according to Example 1, wherein the barrier layer comprises aluminum gallium nitride (AlGaN), and the buffer layer comprises gallium nitride (GaN).

[0099] 12. The HEMT according to any one of Examples 1-11, wherein the HEMT is integrated in an integrated circuit (IC).

[0100] 13. The HEMT according to any one of Examples 1-12, wherein the HEMT is integrated into a device selected from the group consisting of: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a tablet computer, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer display, a television, a tuner, a radio transceiver, a satellite broadcast, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, a drone, and a multi-axis aircraft.

[0101] 14. A high electron mobility transistor (HEMT) comprising:

[0102] A buffer layer above a substrate;

[0103] A barrier layer above the buffer layer;

[0104] A two-dimensional electron gas layer (2DEG) conductive channel at a heterojunction between a lower surface of the barrier layer and the buffer layer;

[0105] A source and a drain, each electrically coupled to the 2DEG conductive channel;

[0106] A first gate including a lower surface on the barrier layer between the source and the drain;

[0107] A first gate insulator between the lower surface of the first gate and the barrier layer, and the length of the first gate extends in a direction from the source to the drain;

[0108] A second gate between the first gate and the drain, the second gate including a second lower surface that is recessed deeper into the barrier layer than the lower surface of the first gate, and the length of the second gate extends in the direction; and

[0109] A second gate insulator between the second lower surface of the second gate and the barrier layer.

[0110] 15. The HEMT according to Example 14, wherein the barrier layer includes an upper surface.

[0111] 16. The HEMT according to Example 15, wherein the first gate insulator is disposed on the upper surface of the barrier layer.

[0112] 17. The HEMT according to any one of Examples 15-16, wherein the first gate insulator is recessed into the barrier layer below the upper surface of the barrier layer.

[0113] 18. The HEMT according to any one of Examples 15-17, wherein:

[0114] The thickness of the barrier layer is the distance between the upper surface and the lower surface of the barrier layer; and

[0115] The depth to which the second lower surface of the second gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer.

[0116] 19. The HEMT according to any one of Examples 14-18, wherein the length of the second gate is equal to the length of the first gate.

[0117] 20. The HEMT according to any one of Examples 14-19, wherein the length of the first gate and the length of the second gate are each in the range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

[0118] 21. The HEMT according to any one of Examples 14-20, wherein in the direction, the distance from the first gate to the second gate is equal to the length of the first gate.

[0119] 22. The HEMT according to any one of Examples 19-21, wherein in the direction, the distance from the first gate to the second gate is in the range between 0 micrometers (μm) and 2.0 μm.

[0120] 23. The HEMT according to any one of Examples 19-22, wherein:

[0121] The length of the first gate and the length of the second gate are both approximately 0.2 micrometers (μm); and

[0122] The distance from the first gate to the second gate is in the range from approximately 0.2 μm to approximately 0.8 μm.

[0123] 24. The HEMT according to Example 14, wherein the barrier layer comprises aluminum gallium nitride (AlGaN), and the buffer layer comprises gallium nitride (GaN).

[0124] 25. A high electron mobility transistor (HEMT) comprising:

[0125] A buffer layer above a substrate;

[0126] A barrier layer above the buffer layer;

[0127] A two-dimensional electron gas layer (2DEG) conductive channel at a heterojunction between a lower surface of the barrier layer and the buffer layer;

[0128] A source and a drain, each electrically coupled to the 2DEG conductive channel;

[0129] A first gate comprising a lower surface in direct contact with the barrier layer between the source and the drain, and a length of the first gate extending in a direction from the source to the drain;

[0130] A second gate between the first gate and the drain, the second gate comprising a second lower surface that is in direct contact with the barrier layer and recessed into the barrier layer to a greater depth than the lower surface of the first gate, and a length of the second gate extending in the direction; and

[0131] A third gate between the second gate and the drain, the third gate comprising a third lower surface that is in direct contact with the barrier layer and recessed into the barrier layer to a depth equal to or greater than the depth of the second lower surface of the second gate in the barrier layer, and a length of the third gate extending in the direction.

[0132] 26. The HEMT according to Example 25, wherein the barrier layer comprises an upper surface.

[0133] 27. The HEMT according to Example 26, wherein the lower surface of the first gate is in direct contact with the upper surface of the barrier layer.

[0134] 28. The HEMT according to any one of Examples 26-27, wherein the lower surface of the first gate is recessed into the barrier layer below the upper surface of the barrier layer.

[0135] 29. The HEMT according to any one of Examples 26-28, wherein:

[0136] The thickness of the barrier layer is a distance between the upper surface of the barrier layer and the lower surface of the barrier layer;

[0137] The depth to which the second lower surface of the second gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer; and

[0138] The depth to which the third lower surface of the third gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer.

[0139] 30. The HEMT according to any one of Examples 25 - 29, wherein:

[0140] The length of the second gate is equal to the length of the first gate; and

[0141] The length of the third gate is equal to the length of the second gate.

[0142] 31. The HEMT according to any one of Examples 25 - 30, wherein the length of the first gate, the length of the second gate, and the length of the third gate are each in the range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

[0143] 32. The HEMT according to any one of Examples 25 - 31, wherein:

[0144] In the direction, the distance between the first gate and the second gate is equal to the length of the first gate; and

[0145] In the direction, the distance between the second gate and the third gate is equal to the length of the first gate.

[0146] 33. The HEMT according to any one of Examples 25 - 32, wherein the distance from the first gate to the second gate in the direction and the distance from the second gate to the third gate in the direction are each in the range from approximately 0 μm to approximately 2.0 μm.

[0147] 34. The HEMT according to any one of Examples 25 - 33, wherein the buffer layer comprises aluminum gallium nitride (AlGaN), and the barrier layer comprises gallium nitride (GaN).

[0148] 35. A method of manufacturing a HEMT, the method comprising:

[0149] Forming a buffer layer over a substrate;

[0150] A barrier layer is disposed above the buffer layer to form a two-dimensional electron gas layer (2DEG) conductive channel;

[0151] At each end of the 2DEG conductive channel, a part of the barrier layer is removed from the buffer layer;

[0152] At the corresponding ends of the 2DEG conductive channel where the part of the barrier layer has been removed, a source electrode and a drain electrode are formed on the buffer layer;

[0153] The barrier layer is recessed to form a recessed gate position;

[0154] A first gate is formed in a first gate position on the barrier layer;

[0155] A second gate is formed in the recessed gate position on the barrier layer; and

[0156] A passivation layer is deposited on the barrier layer.

Claims

1. A high electron mobility transistor (HEMT) comprising: A buffer layer above a substrate; A barrier layer above the buffer layer; A two-dimensional electron gas (2DEG) conductive channel at a heterojunction between a lower surface of the barrier layer and the buffer layer; A source and a drain, each electrically coupled to the 2DEG conductive channel; A first gate including a lower surface in direct contact with the barrier layer between the source and the drain, and a length of the first gate extending in a direction from the source to the drain; And A second gate between the first gate and the drain, the second gate including a second lower surface in direct contact with the barrier layer and recessed into the barrier layer to a depth deeper than the lower surface of the first gate, and a length of the second gate extending in the direction.

2. The HEMT according to claim 1, wherein the lower surface of the first gate is in direct contact with an upper surface of the barrier layer.

3. The HEMT according to claim 1, wherein the lower surface of the first gate is recessed into the barrier layer below the upper surface of the barrier layer.

4. The HEMT according to claim 1, wherein: The barrier layer includes an upper surface, and a thickness of the barrier layer is a distance between the upper surface of the barrier layer and a lower surface of the barrier layer; and The depth to which the second lower surface of the second gate is recessed into the barrier layer is a distance in a range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer.

5. The HEMT according to claim 1, wherein in the direction, a length of the second gate is equal to a length of the first gate.

6. The HEMT according to claim 1, wherein the length of the first gate and the length of the second gate are each in a range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

7. The HEMT according to claim 1, wherein in the direction, a distance between the first gate and the second gate is equal to the length of the first gate.

8. The HEMT according to claim 5, wherein in the direction, a distance from the first gate to the second gate is in a range between 0 μm and 2.0 μm.

9. The HEMT according to claim 5, wherein: The length of the first gate and the length of the second gate are each in a range that is 10% more or 10% less than 0.2 micrometers (μm); and In the direction, a distance from the first gate to the second gate is in a range from 0.2 μm to 0.8 μm.

10. The HEMT according to claim 1, wherein the barrier layer includes aluminum gallium nitride (AlGaN), and the buffer layer includes gallium nitride (GaN).

11. The HEMT according to claim 1, wherein the HEMT is integrated in an integrated circuit (IC).

12. The HEMT according to claim 1, wherein the HEMT is integrated into a device selected from the group consisting of: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a tablet computer, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer display, a television, a tuner, a radio transceiver, a satellite broadcast, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, a drone, and a multi-axis aircraft.

13. A high electron mobility transistor (HEMT) comprising: a buffer layer on a substrate, the buffer layer including an upper surface; a source and a drain, the source and the drain being directly adjacent to the buffer layer; a barrier layer directly adjacent to the source and the drain and extending from the source to the drain directly adjacent to the upper surface of the buffer layer, the barrier layer including a lower surface that is in the same horizontal plane as the lower surface of each of the source and the drain; a two-dimensional electron gas (2DEG) conductive channel at a heterojunction between the lower surface of the barrier layer and the buffer layer, the heterojunction extending from the source to the drain; a first gate including a lower surface that is on an upper surface of an insulating layer and above an upper surface of the barrier layer between the source and the drain, and a length of the first gate extending in a first direction from the source to the drain; and a second gate between the first gate and the drain, the second gate including a second lower surface, wherein: the second lower surface is recessed into the barrier layer; a thickness of the barrier layer between the second gate and the buffer layer is less than a thickness of the barrier layer between the first gate and the buffer layer; a length of the second gate extends in the first direction; and wherein the insulating layer includes a first gate insulator between the lower surface of the first gate and the barrier layer and a second gate insulator between the second lower surface of the second gate and the barrier layer, and a first distance between the first gate and the source is less than a second distance between the first gate and the drain.

14. The HEMT according to claim 13, wherein the first gate insulator is disposed on the upper surface of the barrier layer.

15. The HEMT according to claim 13, wherein the second gate insulator is recessed below the upper surface of the barrier layer.

16. The HEMT according to claim 13, wherein the length of the second gate is equal to the length of the first gate.

17. The HEMT according to claim 13, wherein the length of the first gate and the length of the second gate are each in the range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

18. The HEMT according to claim 13, wherein in the first direction, the distance from the first gate to the second gate is equal to the length of the first gate.

19. The HEMT according to claim 16, wherein in the first direction, the distance between the first gate and the second gate is in the range between 0 micrometers (μm) and 2.0 μm.

20. The HEMT according to claim 16, wherein: the length of the first gate and the length of the second gate are each in the range that is 10% more or 10% less than 0.2 micrometers (μm); and in the direction, the distance from the first gate to the second gate is in the range from 0.2 μm to 0.8 μm.

21. The HEMT according to claim 13, wherein the barrier layer comprises aluminum gallium nitride (AlGaN), and the buffer layer comprises gallium nitride (GaN).

22. A high electron mobility transistor (HEMT) comprising: a buffer layer above a substrate; a barrier layer above the buffer layer; a two-dimensional electron gas (2DEG) conductive channel at a heterojunction between a lower surface of the barrier layer and the buffer layer; a source and a drain, each electrically coupled to the 2DEG conductive channel; a first gate comprising a lower surface in direct contact with the barrier layer between the source and the drain, and the length of the first gate extends in a direction from the source to the drain; a second gate between the first gate and the drain, the second gate comprising a second lower surface in direct contact with the barrier layer and recessed deeper into the barrier layer than the lower surface of the first gate, and the length of the second gate extends in the direction; and a third gate between the second gate and the drain, the third gate comprising a third lower surface in direct contact with the barrier layer and recessed into the barrier layer to a depth equal to or deeper than the depth of the second lower surface of the second gate in the barrier layer, and the length of the third gate extends in the direction.

23. The HEMT according to claim 22, wherein the lower surface of the first gate is in direct contact with the upper surface of the barrier layer.

24. The HEMT according to claim 22, wherein the lower surface of the first gate is recessed into the barrier layer below the upper surface of the barrier layer.

25. The HEMT according to claim 22, wherein: the barrier layer comprises an upper surface, and the thickness of the barrier layer is the distance between the upper surface of the barrier layer and the lower surface of the barrier layer; The depth to which the second lower surface of the second gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer; and The depth to which the third lower surface of the third gate is recessed into the barrier layer is a distance in the range of 5% to 100% of the thickness of the barrier layer below the upper surface of the barrier layer.

26. The HEMT according to claim 22, wherein: The length of the second gate is equal to the length of the first gate; and The length of the third gate is equal to the length of the second gate.

27. The HEMT according to claim 22, wherein the lengths of the first gate, the second gate, and the third gate are each in the range from 0.03 micrometers (μm) to 2.0 micrometers (μm).

28. The HEMT according to claim 22, wherein: In the direction, the distance from the first gate to the second gate is equal to the length of the first gate; and In the direction, the distance from the second gate to the third gate is equal to the length of the first gate.

29. The HEMT according to claim 22, wherein the distance from the first gate to the second gate in the direction and the distance from the second gate to the third gate in the direction are each in the range from 0 μm to 2.0 μm.

30. The HEMT according to claim 22, wherein the buffer layer comprises aluminum gallium nitride (AlGaN), and the barrier layer comprises gallium nitride (GaN).

31. A method of manufacturing a HEMT, the method comprising: Forming a buffer layer over a substrate; Disposing a barrier layer over the buffer layer to form a two-dimensional electron gas (2DEG) conductive channel; Removing a portion of the barrier layer from the buffer layer at each end of the 2DEG conductive channel; Forming a source and a drain on the buffer layer at the respective ends of the 2DEG conductive channel from which the portion of the barrier layer has been removed; Recessing the barrier layer to form a recessed gate position; Forming a first gate in a first gate position on the barrier layer; Forming a second gate in the recessed gate position on the barrier layer; And Depositing a passivation layer on the barrier layer.

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