High-frequency power supply device and output control method thereof

Abstract

The present application provides a high-frequency power supply device and an output control method thereof, which can make the phase of output high-frequency pulses consistent even if a configuration for generating a synchronization pulse and a clock pulse separately. A high-frequency power supply device and an output control method thereof, the high-frequency power supply device outputs high-frequency pulses to an object device based on a synchronization pulse and a clock pulse, the output control method of the high-frequency power supply device generates a cycle reference signal according to output timing information of the synchronization pulse, generates an output level signal according to output level information, counts output stop time based on the cycle reference signal, and generates an output stop signal, receives the cycle reference signal, the output level signal, and the clock pulse, and stops transmission of the output level signal during a period when the output stop signal is received when high-frequency pulses are formed based on these signals.

Description

TECHNICAL FIELD

[0001] The present application relates to a high-frequency power supply device suitable for a plasma generating device or the like, and particularly to a high-frequency power supply device that outputs a high-frequency pulse to a target device based on a synchronization pulse and a clock pulse, and an output control method thereof. BACKGROUND

[0002] A high-frequency power supply device applied to a power source for ultrasonic wave oscillation, induction power generation, or plasma generation, or the like, is a power supply device that can output a high-frequency pulse containing a high-frequency component at a predetermined cycle and amplitude value by combining a synchronization pulse that determines the output cycle of the high-frequency pulse and a clock pulse that determines the pulse cycle of the oscillation high-frequency component. In particular, as a high-frequency power supply applied to a plasma generating device, a switching type high-frequency power supply device that contains an amplitude value of a high level (first level) and a low level (second level) in one oscillation cycle is known.

[0003] As a plasma processing device that applies such a switching type high-frequency power supply device, for example, a plasma etching device is disclosed in Patent Literature 1 in which a processing chamber in which a semiconductor wafer as a processed body is housed filled with an etching gas is provided with an upper electrode and a lower electrode opposed across the processed body, a high-frequency voltage from a high-frequency power supply is applied to these upper and lower electrodes, and the etching gas is plasma-ized by discharge between the upper and lower electrodes to perform etching processing on the processed body. In such a device, in order to perform uniform processing on the entire surface of the processed body, it is required that the applied voltage from the high-frequency power supply be stable.

[0004] In a plasma etching device, in order to stably generate plasma, for example, a technique is disclosed in Patent Literature 2 in which a matching network that converts the complex impedance of plasma observed from the end of a transmission path into the nominal impedance of a high-frequency generator is connected between the high-frequency generator and a plasma processing chamber, and the voltage of an induction coil that supplies high-frequency power to the plasma processing chamber is feedback controlled. According to this control technique, by the matching network, the phase of the power waveform applied to the induction coil can be made uniform by feedback control, and thus the substrate processing can be stabilized.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: Japanese Patent Application Laid-Open No. 11-214363

[0008] Patent Literature 2: Japanese Patent Application Laid-Open No. 2007-514300 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] As described above, in the high-frequency power supply device known in the past, the synchronization pulse generator that generates a synchronization pulse and the clock pulse generator that generates a clock pulse are configured to be generally separate bodies, and the two independently operate separately, and thus the phase of an output waveform generated based on the clock pulse in a high-frequency pulse that is output based on the timing of the synchronization pulse cannot be avoided from being inconsistent at the time of switching of the output level of the high-frequency pulse. As a result, the number of pulses generated by the amplitude of the first level and the number of pulses generated by the amplitude of the second level become scattered among the plurality of high-frequency pulses that continuously oscillate, and become a cause of generating jitter.

[0011] In order to solve the problem of unstable output waveform caused by the oscillation configuration of such a high-frequency power supply device, for example, the technology of the above-described Patent Literature 2 is applied, but an additional structure (matching network or the like) must be attached between the plasma processing device and the high-frequency power supply device, and the power supply control also becomes complicated. In addition, since a phenomenon that cannot be coped with when the output waveform of the high-frequency pulse is varied at high speed compared to the response speed of the matching network occurs, it does not become a fundamental solution to the problem that occurs when the high-frequency power supply device of the switching system is applied.

[0012] The present application is completed in order to solve the above-described conventional problems, and aims to provide a high-frequency power supply device and an output control method thereof, in which even in a configuration in which a synchronization pulse and a clock pulse are generated separately, the phase of an output high-frequency pulse can be always consistent.

[0013] Means for solving the problem

[0014] To solve the above problems, one of the representative modes of the present application is a high-frequency power supply device that outputs a high-frequency pulse to a target device based on a synchronization pulse and a clock pulse, characterized by comprising: a synchronization pulse generation mechanism that generates a synchronization pulse including output level information and output timing information of the high-frequency pulse; an output level setting mechanism that generates an output level signal for setting an output level of the high-frequency pulse based on the output level information; and an oscillation mechanism that receives a cycle reference signal of the synchronization pulse and the output level signal and oscillates the high-frequency pulse, wherein the synchronization pulse generation mechanism includes: a synchronization pulse forming circuit that forms the synchronization pulse; a cycle reference signal generator that generates a cycle reference signal at a cycle reference timing in the synchronization pulse; and a timing mechanism that times an output stop time based on the cycle reference signal and sends an output stop signal to the output level setting mechanism, the output level setting mechanism includes: a level discrimination section that discriminates the output level set in the high-frequency pulse based on the output level signal; and a level setting signal generation section that generates a level setting signal based on a discrimination result of the level discrimination section, and the oscillation mechanism includes: a clock pulse generator that generates the clock pulse; and an oscillation amplifier that receives the cycle reference signal, the level setting signal, and the clock pulse and forms the high-frequency pulse based on these signals, and the output level setting mechanism stops transmission of the level setting signal during a period in which the output stop signal is received.

[0015] In addition, one of the other modes of the present application is an output control method of a high-frequency power supply device that outputs a high-frequency pulse to a target device based on a synchronization pulse and a clock pulse, characterized by comprising the steps of: generating an output level signal for setting an output level of the high-frequency pulse based on output level information included in a waveform of the synchronization pulse and generating a cycle reference signal based on output timing information; generating a level setting signal based on the output level signal and timing an output stop time based on the cycle reference signal and generating an output stop signal; and when receiving the cycle reference signal, the level setting signal, and the clock pulse and forming the high-frequency pulse based on these signals, stopping transmission of the level setting signal during a period in which the output stop signal is received.

[0016] According to the high-frequency power supply device of the present application having such a structure, the period reference signal, the level setting signal, and the clock pulse based on the synchronization pulse are received, the output stop time is timed based on the period reference signal when the high-frequency pulse is formed based on these signals, and the output stop signal is generated, and the transmission of the level setting signal is stopped during the period when the output stop signal is received, so that the phase of the output high-frequency pulse can be always consistent even if the structure in which the synchronization pulse and the clock pulse are generated respectively. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a block diagram showing an outline of the high-frequency power supply device of Embodiment 1 which is a representative example of the present application.

[0018] Figure 2 is a block diagram showing an example of the detailed structure of the synchronization pulse generating mechanism of Embodiment 1.

[0019] Figure 3 is a block diagram showing an example of the detailed structure of the output level setting mechanism of Embodiment 1.

[0020] Figure 4 is a block diagram showing an example of the detailed structure of the oscillation mechanism of Embodiment 1.

[0021] Figure 5 is a chart showing an example of the output waveform obtained by the output control method of the high-frequency power supply device of Embodiment 1.

[0022] Figure 6 is a chart showing a modification of the output waveform obtained by the output control method of the high-frequency power supply device of Embodiment 1.

[0023] Figure 7 is a block diagram showing an outline of the high-frequency power supply device of Embodiment 2.

[0024] Figure 8 is a block diagram showing an example of the detailed structure of the output level setting mechanism of Embodiment 2.

[0025] Figure 9 is a block diagram showing an example of the detailed structure of the oscillation mechanism of Embodiment 2.

[0026] Figure 10 is a chart showing an example of the output waveform obtained by the output control method of the high-frequency power supply device of Embodiment 2. DETAILED DESCRIPTION

[0027] Hereinafter, the following Figures 1-10 A representative specific example of the high-frequency power supply device of the present application and the output control method thereof will be described.

[0028] <Embodiment 1>

[0029] Figure 1 This is a block diagram illustrating the general outline of a high-frequency power supply device according to Embodiment 1, which is a representative example of the present invention. Figure 1 As shown, as an example, the high-frequency power supply device 100 of Embodiment 1 includes: a synchronization pulse generation mechanism 110, which generates a synchronization pulse P1 that includes output level information of the output high-frequency pulse PO and output timing information; and an output level setting mechanism 120, which generates an output level signal S that sets the output level of the high-frequency pulse PO based on the output level information of the synchronization pulse P1. L1 S L2 ; and an oscillation mechanism 130, which receives a periodic reference signal S based on the output timing information of the synchronization pulse P1. S and the aforementioned output level signal S L1 S L2 The high-frequency pulse PO is used to oscillate. The high-frequency pulse PO output from the high-frequency power supply device 100 is supplied to the target device 10, such as a plasma, laser generating device, induction heating device, or ultrasonic oscillation device.

[0030] Figure 2 This is a block diagram illustrating an example of the specific structure of the synchronization pulse generation mechanism in Embodiment 1. For example... Figure 2 As shown, the synchronization pulse generation mechanism 110 of Embodiment 1 includes: a synchronization pulse forming circuit 112, which generates the aforementioned synchronization pulse P1; and a periodic reference signal generator 114, which generates a periodic reference signal S at the periodic reference time in the synchronization pulse P1. S ; and timing mechanism 116, which is based on periodic reference signal S S The output stop time is timed, and the output stop signal S is sent. T The output level setting mechanism 120 is sent out. In addition, the synchronization pulse P1 generated from the synchronization pulse forming circuit 112 is also supplied to the output level setting mechanism 120, which will be described later.

[0031] As one example, the synchronous pulse forming circuit 112 includes output level information (amplitude value) and output timing information (amplitude switching timing), outputting a periodic pulse waveform that is approximately rectangular in shape with time passing through two output levels L1 and L2 on the vertical axis relative to the horizontal axis. Additionally, in Figure 2 The example shows the case where the output level is set to high level L1 and low level L2, but as long as it is a periodic, roughly rectangular wave, it can also be set to a pulse waveform based on more than 3 output levels.

[0032] In addition, the synchronization pulse P1 is not limited to a rectangular wave, and can be any waveform as long as it includes output level information and output timing information, such as a sine wave or an extremely short pulse. Furthermore, the synchronization pulse P1 can be composed of a plurality of signal waveforms. As such examples, a method of obtaining output level and output timing by AND processing a plurality of signal waveforms can be exemplified.

[0033] The cycle reference signal generator 114 determines the timing reference of the cycle, that is, the output timing information, as one of the characteristics of the synchronization pulse P1 received from the synchronization pulse forming circuit 112, and outputs the cycle reference signal S S At this time, as an example of the timing reference of the cycle, for example, the timing at which the low level L2 is switched (rises) to the high level L1 can be exemplified. In addition, the cycle reference signal S S The cycle is not limited to one in one period, and for example, the timing at which the high level L1 is switched (falls) to the low level L2 can be adopted in addition to the timing at which the low level L2 is switched (rises) to the high level L1.

[0034] As an example thereof, the timing mechanism 116 has a configuration that receives the cycle reference signal S S from the cycle reference signal generator 114, and continues to transmit the output stop signal S T to the output level setting mechanism 120 described later during a predetermined output stop time from the reception time. At this time, the timing mechanism 116 is configured such that the predetermined output stop time can be arbitrarily selected with respect to the timing of the clock period of the clock pulse generator 132 (refer to Figure 4 ) described later. Thereby, the timing at which the transmission of the output stop signal S T stops can be arbitrarily selected.

[0035] Figure 3 is a block diagram showing an example of a specific configuration of the output level setting mechanism of Embodiment 1. As Figure 3 shown, the output level setting mechanism 120 of Embodiment 1 includes a level discrimination section 122 that transmits a first level setting instruction S1 or a second level setting instruction S2 according to the amplitude value (output level information) of the synchronization pulse P1, and a level setting signal generation section 124 that generates a level setting signal (a first level setting signal S T and a second level setting signal S L1 ) accepting the output stop signal S L2 and the first level setting instruction S1 and the second level setting instruction S2. Furthermore, the level setting signal generation section 124 further includes a first level setting signal generator 126 that generates the first level setting signal S L1; and a second level setting signal generator 128 that generates a second level setting signal S when receiving a second level setting instruction S2 L2 .

[0036] The level discrimination section 122 receives the synchronization pulse Pl from the synchronization pulse generating circuit 112, and transmits a predetermined setting instruction in real time according to which level the output level of the synchronization pulse Pl is. As an example thereof, in Embodiment 1, the level discrimination section 122 transmits a first level setting instruction Sl during the period when the synchronization pulse Pl is the high level LI, and transmits a second level setting instruction S2 when the synchronization pulse Pl is switched to the low level L2.

[0037] The first level setting signal generator 126 generates a first level setting signal S L1 when receiving the first level setting instruction Sl from the level discrimination section 122. Likewise, the second level setting signal generator 128 generates a second level setting signal S L2 when receiving the second level setting instruction S2 from the level discrimination section 122. At this time, the level setting signal generating section 124 is configured to not output the first level setting signal S T or the second level setting signal S L1 generated by the first level setting signal generator 126 or the second level setting signal generator 128 to the oscillation mechanism 130 during the period when receiving the output stop signal S L2 from the synchronization pulse generating mechanism 110.

[0038] Figure 4 is a block diagram showing an example of the detailed structure of the oscillation mechanism of Embodiment 1. As shown in Figure 4 , the oscillation mechanism 130 of Embodiment 1 includes a clock pulse generator 132 that generates a predetermined high frequency range clock pulse P2, and an oscillation amplifier 134 that receives the period reference signal S S from the synchronization pulse generating mechanism 110, the first level setting signal S L1 and the second level setting signal S L2 from the output level setting mechanism 120, and the above clock pulse P2, and forms a high frequency pulse PO based on these signals.

[0039] The clock pulse generator 132 is a unit that generates a high frequency (hundreds of kHz to tens of MHz) clock pulse P2 corresponding to the output of the high frequency pulse PO, for example, a 13.56 MHz clock pulse P2. In addition, the clock pulse generator 132 has clock pulses P2 at equal intervals at the above predetermined high frequency, and at an arbitrary time t rst (see Figure 5 or Figure 6) the function of timing resetting (setting to an arbitrary phase) the generation of the clock pulse P2. Then, the oscillation amplifier 134 determines the oscillation timing of the high-frequency pulse PO based on the period reference signal S S L1 L2 amplifies the amplitude value of the clock pulse P2, thereby generating the high-frequency pulse PO.

[0040] Figure 5 is a graph showing an example of an output waveform obtained by the output control method of the high-frequency power supply apparatus of Embodiment 1. In the output control method of the high-frequency power supply apparatus of Embodiment 1, as an example thereof, first, as shown in (a) of Figure 5 , the synchronization pulse PI formed by the synchronization pulse forming circuit 112 of the synchronization pulse generation mechanism 110 becomes a periodic pulse signal in which the interval from time T L1 becomes the high level LI and the interval from time T L2 becomes the low level L2. Also, as described above, from the synchronization pulse PI, the rising time to the high level LI, for example, as a time reference for one cycle of the pulse is extracted, and the period reference signal generator 114 sends the period reference signal S S at each of the rising times.

[0041] On the other hand, the synchronization pulse PI is also supplied to the output level setting mechanism 120, and the level discrimination section 122 of the output level setting mechanism 120 sets the output level at each time, and sends the first level setting signal S L1 or the second level setting signal S L2 from the first level setting signal generator 126 or the second level setting signal generator 128 to the oscillation mechanism 130. That is, with reference to (a) of Figure 5 , the first level setting signal S L1 is sent in the interval from time T L1 , and the second level setting signal S L2 is sent in the interval from time T L2 .

[0042] Next, in the oscillation amplifier 134 of the oscillation mechanism 130, the amplitude value of the clock pulse P2 is amplified in accordance with the received first level setting signal S L1 or the second level setting signal S L2 . That is, in the case where the first level setting signal S L1 is continuously received, as shown in (b) of Figure 5 , a continuous pulse of which the average height of the output clock pulse P2 is the high level LI is output. On the other hand, in the case where the second level setting signal S L2 is continuously received, as shown in (c) of​​Figure 5 As shown in (c), the average height of the output clock pulse P2 is a continuous pulse of low level L2.

[0043] Here, as Figure 5 As shown in (d), the output stop time T is sent from the timing mechanism 116. st Output stop signal S T In the case of this output stopping time T st any time t during the period rst (This moment is defined as "reset time t") rst The clock pulse P2 generated by the clock pulse generator 132 is reset. Furthermore, if these actions are continuously performed as time changes from the generation of the synchronization pulse P1, then... Figure 5 As shown in (e), a periodic reference signal S is received from the oscillation mechanism 130. S The high-frequency pulse PO begins to output at time T. L1 The interval outputs a continuous high-level pulse L1. Similarly, at time T... L2 The interval outputs a continuous low-level pulse L2.

[0044] At this time, as described above, the output level setting mechanism 120 is configured to receive an output stop signal S. T During this period, the first level setting signal S is not sent. L1 Therefore, from time T L1 The interval starts after the output stopping time T st Previously, no continuous high-level pulses of L1 were output. Here, at this time, the reset time t... rst The timing is based on the output stop time T. st The phase θ of the first high-frequency pulse PO output after the end st This is determined by the reset time t. rst The phase of the reset clock pulse P2, after the output stop time T st The phase of the subsequent high-frequency pulse PO remains the same.

[0045] Figure 6 This is a diagram illustrating a modified example of the output waveform obtained by the output control method of the high-frequency power supply device of Embodiment 1. Figure 6 In the output control method of the high-frequency power supply device shown in the modified example, firstly, as Figure 6 As shown in (a), from the synchronization pulse P1 generated by the synchronization pulse forming circuit 112 of the synchronization pulse generation mechanism 110, and... Figure 5Similarly, as shown, the rising moment of the high level L1, for example, is extracted as a time reference for one cycle of the pulse, and the period reference signal generator 114 sends a period reference signal S at each rising moment. S Furthermore, in the output level setting mechanism 120, at time T... L1 The first level setting signal S is sent within the interval. L1 At time T L2 Within the specified range, a second level setting signal S is sent to the oscillation mechanism 130. L2 .

[0046] Next, with Figure 5 Similarly, in the oscillation amplifier 134 of the oscillation mechanism 130, the received first level setting signal S is used. L1 Or the second level setting signal S L2 The amplitude of clock pulse P2 is amplified. Then, the output is as follows: Figure 6 As shown in (b), the average height of clock pulse P2 is a continuous pulse of high level L1 and Figure 6 As shown in (c), the average height of the clock pulse P2 is a continuous pulse of low level L2.

[0047] Here, as Figure 6 As shown in (d), when the timer 116 sends the output stop time T... st Output stop signal S T At that time, and Figure 5 Similarly, as shown, at the output stopping time T st any time t during the period rst (This moment is defined as "reset time t") rst The clock pulse P2 generated by the clock pulse generator 132 is reset. Furthermore, in the output level setting mechanism 120, since it is configured to receive the output stop signal S... T During this period, the first level setting signal S is not sent. L1 Therefore, if execution continues continuously over time from the generation of synchronization pulse P1, then as... Figure 6 As shown in (e), a periodic reference signal S is received from the oscillation mechanism 130. S The high-frequency pulse PO begins to output at time T. L1 The interval outputs a continuous high-level pulse L1. Similarly, at time T... L2 The interval outputs a continuous low-level pulse L2.

[0048] At this time, Figure 6 In the modified example shown, the reset time t rst The timing is set to occur at the output stop time T. stThe phase θ of the first high-frequency pulse PO output after the end st It is always in phase 0. Therefore, by resetting at time t... rst The phase of the reset clock pulse P2 can stabilize the output after the output stop time T. st The phase of the subsequent high-frequency pulse PO is always phase 0. On the other hand, as... Figure 6 As shown in (e), the output delay is used as the standby time α to make the output phase coincide with phase 0.

[0049] By having the structure described above, the high-frequency power supply device and its output control method of Embodiment 1 are configured such that, upon receiving a periodic reference signal S based on a synchronization pulse P1... S First level setting signal S L1 Second level setting signal S L2 And clock pulse P2, when a high-frequency pulse PO is formed based on these signals, it will be based on the periodic reference signal S. S The output stop time T of the timer st Set to an integer multiple of the clock period of clock pulse P2, upon receiving the output stop signal S T During this period, the output level setting mechanism stops the first level setting signal S. L1 Or the second level setting signal S L2 Therefore, even if the construction generates a synchronization pulse and a clock pulse separately, it is possible to ensure that the phase of the output high-frequency pulse is always consistent.

[0050] <Example 2>

[0051] Figure 7 This is a block diagram illustrating the general outline of the high-frequency power supply device of Embodiment 2. Here, in the high-frequency power supply device 200 of Embodiment 2, for high-frequency power supply devices having the same or identical structure as in Embodiment 1, the same reference numerals as in Embodiment 1 are used, and further descriptions are omitted.

[0052] like Figure 7 As shown, the high-frequency power supply device 200 of Embodiment 2 includes a synchronization pulse generation mechanism 110, an output level setting mechanism 120, and an oscillation mechanism 130. The difference between the high-frequency power supply device 200 of Embodiment 2 and the high-frequency power supply device 100 of Embodiment 1 is that a level 0 signal S is sent from the output level setting mechanism 120 to the oscillation mechanism 130. L0 .

[0053] Figure 8 This is a block diagram illustrating an example of the specific structure of the output level setting mechanism in Embodiment 2. For example... Figure 8 As shown, the output level setting mechanism 120 of Embodiment 2 includes: a level discrimination unit 122, which receives the output stop signal S. Tand the first level setting instruction S1 and the second level setting instruction S2. The level setting signal generation section 124 generates a level setting signal (a level 0 signal S0) based on the output stop signal S T and the first level setting instruction S1 and the second level setting instruction S2. The level setting signal generation section 124 generates a level setting signal (a level 0 signal S0) based on the output stop signal S L0 , the first level setting signal S L1 , and the second level setting signal S L2 ). Further, the level setting signal generation section 124 includes a level 0 signal generator 223 that generates the level 0 signal S T based on the output stop signal S L0 , and the same first level setting signal generator 126 and the second level setting signal generator 128 as in Embodiment 1.

[0054] As in the case of Embodiment 1, the level discrimination section 122 receives the synchronization pulse P1 from the synchronization pulse generation circuit 112, and sends the first level setting instruction S1 during the period when the synchronization pulse P1 is at the high level L1 and sends the second level setting instruction S2 when the synchronization pulse P1 is switched to the low level L2, depending on which level the output level of the synchronization pulse P1 is at.

[0055] The level 0 signal generator 223 is configured to be activated during the period when the level setting signal generation section 124 receives the output stop signal S T , and sends the level 0 signal S T that sets the amplitude value of the high frequency pulse PO to 0 during the period when the output stop signal S L0 is received. On the other hand, as in the case of Embodiment 1, the first level setting signal generator 126 and the second level setting signal generator 128 send the first level setting signal S L1 or the second level setting signal S L2 to the oscillation mechanism 130 if they receive the first level setting instruction S1 or the second level setting instruction S2 from the level discrimination section 122. Thus, the level setting signal generation section 124 outputs only the level 0 signal S L0 to the oscillation mechanism 130 and does not output the first level setting signal S L1 or the second level setting signal S L2 during the period when it receives the output stop signal S T from the synchronization pulse generation mechanism 110.

[0056] Figure 9 is a block diagram showing an example of the detailed configuration of the oscillation mechanism of Embodiment 2. As Figure 9As shown, the oscillation mechanism 130 of Embodiment 2 includes a clock pulse generator 132 and an oscillation amplifier 234. The oscillation amplifier 234 receives the period reference signal S from the synchronization pulse generation mechanism 110. S Level 0 signal S from output level setting mechanism 120 L0 First level setting signal S L1 and the second level setting signal S L2 And the aforementioned clock pulse P2, and based on these signals, a high-frequency pulse PO is formed.

[0057] The oscillator amplifier 234 in Example 2 is based on the periodic reference signal S S To determine the oscillation timing of the high-frequency pulse PO, and in receiving the level 0 signal S L0 During this process, the amplitude value of the high-frequency pulse PO is set to 0. On the other hand, the first level setting signal S is received. L1 and the second level setting signal S L2 During the process, based on these signals, the amplitude of the clock pulse P2 is amplified to a high level L1 or a low level L2, thereby generating a high-frequency pulse PO.

[0058] Figure 10 This is a graph illustrating an example of the output waveform obtained by the output control method of the high-frequency power supply device in Embodiment 2. In the output control method of the high-frequency power supply device in Embodiment 2, regarding... Figure 10 (a)~ Figure 10 The synchronization pulse P1 and the output stop signal S shown in (d) T The relationship between the amplification of the amplitude values ​​of the high-frequency pulse PO and the high-level L1 and low-level L2 is the same as in Example 1, so it will not be explained again.

[0059] On the other hand, in the output control method of the high-frequency power supply device in Embodiment 2, when the output stop signal S is output... T During this period, the output level setting mechanism controls the output level to be 0, which is the level 0 signal S. L0 The output is sent to the oscillation mechanism, therefore, as Figure 9 As shown in (e), even in the output interval of the immediately preceding high-frequency pulse PO (time T) L2 The terminal generates an apparent bounce pulse (damping pulse, PD) caused by the switching (switch) of the output level. In the actual output, it can also suppress the erroneous pulse output and control it as an amplitude value of 0.

[0060] In addition, the above-described embodiments and the descriptions in the modifications are examples of the high-frequency power supply device and the output control method thereof, and the present application is not limited to each embodiment. In addition, those skilled in the art can make various modifications without departing from the spirit of the present application, and they are not excluded from the scope of the present application.

[0061] For example, in Embodiments 1 and 2 described above, the case where the output stop time T st is set at the initial output of the high level L1 is exemplified, but the output stop time T st may be set at the initial output of the low level L2 or the initial output of both the high level L1 and the low level L2. Thus, it is possible to perform control to maintain the number of waves per 1 cycle at the time of output of the high-frequency pulse PO as a fixed value.

[0062] In addition, the structures exemplified in Embodiments 1 and 2 are not structures of separate inventions, and the features of each other can be combined and applied as one high-frequency power supply device.

[0063] Symbol explanation

[0064] 10 Object device

[0065] 100, 200, 300 High-frequency power supply device

[0066] 110 Synchronization pulse generation mechanism

[0067] 112 Synchronization pulse forming circuit

[0068] 114 Cycle reference signal generator

[0069] 116 Timing mechanism

[0070] 120 Output level setting mechanism

[0071] 122 Level discrimination section

[0072] 124 Level setting signal generation section

[0073] 126 First level setting signal generator

[0074] 128 Second level setting signal generator

[0075] 130 Oscillation mechanism

[0076] 132 Clock pulse generator

[0077] 134, 234 Oscillation amplifier

[0078] 223 Level 0 signal generator

[0079] PO High-frequency pulse

[0080] P1 sync pulse

[0081] P2 clock pulse

[0082] S S cycle reference signal

[0083] S T output stop signal

[0084] S L0 level 0 signal

[0085] S L1 first level setting signal

[0086] S L2 second level setting signal

[0087] T st output stop time.

Claims

1. A high-frequency power supply device, which outputs high-frequency pulses to a target device based on synchronization pulses and clock pulses, characterized in that, The high-frequency power supply device includes: A synchronization pulse generation mechanism generates a synchronization pulse that includes output level information and output timing information of the high-frequency pulse. An output level setting mechanism generates a level setting signal for setting the output level of the high-frequency pulse based on the output level information; as well as An oscillation mechanism receives the period reference signal of the synchronization pulse and the level setting signal, and causes the high-frequency pulse to oscillate. The synchronization pulse generation mechanism includes: A synchronization pulse generating circuit, which generates the synchronization pulse; A periodic reference signal generator that generates a periodic reference signal at a periodic reference time in the synchronization pulse; and The timing mechanism counts the output stop time based on the period reference signal and sends an output stop signal to the output level setting mechanism. The output level setting mechanism includes: A level discrimination unit, which determines the set output level in the high-frequency pulse based on the output level information; and The level setting signal generation unit receives the discrimination result from the level discrimination unit and generates the level setting signal. The oscillation mechanism includes: A clock pulse generator that generates the clock pulse; and An oscillator amplifier receives the period reference signal, the level setting signal, and the clock pulse, and generates the high-frequency pulse based on these signals. During the period when the output level setting mechanism receives the output stop signal, it stops sending the level setting signal. When the output stop signal is sent from the timing mechanism, at a reset time during the output stop time, the clock pulse generated from the clock pulse generator is reset, wherein the timing of the reset time is determined based on the phase of the high-frequency pulse that is first output after the output stop time ends.

2. The high-frequency power supply device according to claim 1, characterized in that, The level setting signal includes a first level setting signal that specifies a first output level of the high-frequency pulse and a second level setting signal that specifies a second output level. The level setting signal generation unit includes a first level setting signal generator that generates the first level setting signal and a second level setting signal generator that generates the second level setting signal.

3. The high-frequency power supply device according to claim 1, characterized in that, The output level setting mechanism further includes: a level 0 signal generator, which generates a level 0 signal that sets the amplitude value of the high-frequency pulse to 0. The level 0 signal generator sends the level 0 signal during the period of receiving the output stop signal, and the oscillation mechanism sets the output of the high-frequency pulse to 0 during the period of receiving the level 0 signal.

4. An output control method for a high-frequency power supply device, wherein the high-frequency power supply device outputs high-frequency pulses to a target device based on a synchronization pulse and a clock pulse, characterized in that, The output control method includes the following steps: Based on the output level information contained in the waveform of the synchronization pulse, a level setting signal for setting the output level of the high-frequency pulse is generated, and a period reference signal is generated based on the output timing information. The output stop time is timed based on the periodic reference signal, and an output stop signal is generated. When receiving the period reference signal, the level setting signal, and the clock pulse, and generating the high-frequency pulse based on these signals, the transmission of the level setting signal is stopped during the period of receiving the output stop signal. When the output stop signal is sent, the clock pulse is reset at a reset time during the output stop time, wherein the timing of the reset time is determined based on the phase of the high-frequency pulse that is first output after the output stop time ends.

5. The output control method of the high-frequency power supply device according to claim 4, characterized in that, The level setting signal includes a first level setting signal that specifies a first output level of the high-frequency pulse and a second level setting signal that specifies a second output level.

6. The output control method of the high-frequency power supply device according to claim 4 or 5, characterized in that, During the period of receiving the output stop signal, a level 0 signal with an amplitude of 0 is generated for the high-frequency pulse. During the period of receiving the level 0 signal, the output of the high-frequency pulse is set to 0.

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