An ATE channel latency auto-calibration circuit, apparatus, method

Abstract

The application relates to an ATE channel time delay automatic calibration circuit, device and method, the circuit comprising a main transceiver pin, a plurality of auxiliary transceiver pins, a switch network, a time delay measurement module and a time delay calibration module, the main transceiver pin is electrically connected with an ATE input and output channel and the time delay measurement module respectively; the switch network is electrically connected with the main transceiver pin, the plurality of auxiliary transceiver pins and the ATE input and output channel respectively; the time delay measurement module is located in an FPGA and is used for transmitting and receiving pulses; and the time delay of the ATE input and output channel is measured according to the pulses; and the time delay calibration module is used for compensating the input channel and the output channel respectively according to the measured time delay of the ATE input and output channel. The application realizes the automatic accurate measurement and automatic delay compensation of the ATE channel time delay through a carry chain and a plurality of measurement loops in the FPGA, and the time delay precision can reach the picosecond level.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor testing, and particularly relates to an ATE channel delay automatic calibration circuit, device and method. Background Art

[0002] ATE (Automatic Test Equipment) generally refers to semiconductor testing equipment in the semiconductor industry. It is a high-end semiconductor device integrating various high-precision and high-performance test and measurement functions. It is the most important equipment in the semiconductor testing process and determines the cost and efficiency of semiconductor testing. Semiconductor testing runs through the whole process of design, manufacturing, packaging and application. Classified by production process, semiconductor testing can be divided into three categories: verification testing, wafer testing, and package inspection. Semiconductor testing is a process of measuring the output response of a semiconductor and comparing it with the expected output to determine or evaluate the function and performance of an integrated circuit. Its test content is mainly electrical parameter testing. Semiconductor testing is an important link to ensure product yield and cost management. With the improvement of semiconductor manufacturing process requirements, the status of the testing link in the semiconductor manufacturing process is constantly rising, and it has gradually developed and grown into an independent third-party testing industry during the process of specialization.

[0003] Timing accuracy is a very critical index of ATE equipment. ATE needs to ensure that the signals output by the FPGA reach the pins of the DUT simultaneously. The current technical status is that ATE can calibrate the delay from the output of the channel driver to the pins of the DUT through TDR. However, the delay of the path from the output of the FPGA to the output of the Driver (driver) is currently ensured by controlling the PCB trace delay. However, due to differences in chip processes, the delays of the driver and the receiver themselves are not fixed values, and the maximum difference even exceeds 1 ns. This is very fatal for testing the high-speed signals of the DUT. Summary of the Invention

[0004] To address the issue of improving the timing synchronization accuracy of ATE channels, a first aspect of this invention provides an automatic timing calibration circuit for ATE channels, comprising: a main transceiver pin, multiple auxiliary transceiver pins, a switching network, a timing measurement module, and a timing calibration module. The main transceiver pin is located at the interface between the FPGA and the ATE input / output channel, and is electrically connected to the ATE input / output channel and the timing measurement module, respectively. The switching network is electrically connected to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively. The timing measurement module is located inside the FPGA and is used to send pulses to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively; and to receive the pulses transmitted by the main transceiver pin or the multiple auxiliary transceiver pins and measure the timing delay of the ATE input / output channel accordingly. The timing calibration module is used to compensate the input and output channels of the ATE input / output channel based on the measured timing delay.

[0005] In some embodiments of the present invention, the switch network includes a first switch, a second switch, and a third switch. The input terminal of the first switch is connected to the delay measurement module via a first auxiliary transceiver pin, and its output terminal is connected to multiple auxiliary transceiver pins, the second switch, and the third switch, respectively. The input terminal of the second switch is connected to the delay measurement module via a main transceiver pin, and its output terminal is connected to the first switch and the third switch, respectively. The input terminal of the third switch is connected to the delay measurement module via a main transceiver pin, and its output terminal is connected to the first switch and the second switch, respectively.

[0006] Furthermore, the first switch, the second switch, and the third switch are all high-speed switches with multiple selection capabilities.

[0007] Furthermore, the wiring distances between the first switch, the second switch, and the third switch are equal.

[0008] In some embodiments of the present invention, the delay measurement module forms multiple measurement loops through a switch network, a main transceiver pin, multiple auxiliary transceiver pins, and an ATE input / output channel. The multiple measurement loops are used to measure the transmission delay or reception delay of the switch network and the main transceiver pin, multiple auxiliary transceiver pins, and the ATE input / output channel, respectively.

[0009] Furthermore, the plurality of measurement loops include a first measurement loop, a second measurement loop, and a third measurement loop. In the first measurement loop, a first pulse emitted by the delay measurement module passes sequentially through the transmit pin of the auxiliary transceiver pin, the switch network, and the first receive pin of the auxiliary transceiver pin before reaching the delay measurement module. In the second measurement loop, a second pulse emitted by the delay measurement module passes sequentially through the transmit pin of the main transceiver pin, the ATE output channel, the switch network, and the second receive pin of the auxiliary transceiver pin before reaching the delay measurement module. In the third measurement loop, a third pulse emitted by the delay measurement module passes sequentially through the transmit pin of the auxiliary transceiver pin, the switch network, the ATE input channel, and the receive pin of the main transceiver pin before reaching the delay measurement module.

[0010] In the above embodiments, the delay calibration module includes a line delay unit, which compensates for the input and output channels of the ATE based on the delay measured by the delay measurement module.

[0011] A second aspect of the present invention provides a calibration apparatus based on the ATE channel delay automatic calibration circuit of the first aspect of the present invention, comprising: a DC calibration circuit, which is connected to the ATE input / output channel and its precision measurement unit respectively through a switching network, for calibrating the DC characteristics of the precision measurement unit or the ATE channel delay automatic calibration circuit.

[0012] A third aspect of the present invention provides a calibration method for an ATE channel delay automatic calibration circuit based on the first aspect of the present invention, comprising: using the main transceiver pin, multiple auxiliary transceiver pins, contacts of a switching network, a delay measurement module, and contacts of the ATE input / output channel as measurement points, and constructing multiple measurement loops based on one or more of the measurement points; calculating the delay between every two measurement points between the FPGA interface and the ATE channel interface according to each measurement loop, and calculating the delay of the ATE channel accordingly; and compensating the input and output channels of the ATE channel according to the delay of the ATE channel.

[0013] A fourth aspect of the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the calibration method of the ATE channel delay automatic calibration circuit provided in the third aspect of the present invention.

[0014] In a fifth aspect, the present invention provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the calibration method for the ATE channel delay automatic calibration circuit provided in the third aspect of the present invention.

[0015] The beneficial effects of this invention are:

[0016] This invention provides an automatic delay calibration circuit for ATE channels, comprising: a main transceiver pin, multiple auxiliary transceiver pins, a switching network, a delay measurement module, and a delay calibration module. The main transceiver pin is located at the interface between the FPGA and the ATE input / output channel, and is electrically connected to the ATE input / output channel and the delay measurement module, respectively. The switching network is electrically connected to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively. The delay measurement module is located inside the FPGA and is used to send pulses to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively; and to receive the pulses transmitted by the main transceiver pin or the multiple auxiliary transceiver pins and measure the delay of the ATE input / output channel accordingly. The delay calibration module is used to compensate the input and output channels of the ATE input / output channel based on the measured delay. As can be seen, this invention, by setting multiple main transceiver pins, multiple auxiliary transceiver pins, and a switching network, forms multiple measurement loops with the ATE input / output channels, and achieves precise measurement and compensation of the propagation delay along the path from FPGA output to Driver output based on these multiple loops; since the delay measurement module is implemented through the FPGA's TDC (carry chain), the calibration accuracy can reach the picosecond level (10^-3 picoseconds). －12 Furthermore, because the switching network uses timing devices such as a synchronous clock to achieve rapid automatic switching of the measurement loop, it enables rapid automatic measurement and automatic compensation. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the interfaces of the ATE when it is in working state in the prior art;

[0018] Figure 2 This is a schematic diagram of the interfaces of the ATE when it is in working state in some embodiments of the present invention;

[0019] Figure 3 This is a schematic diagram of the ATE channel delay automatic calibration circuit in some embodiments of the present invention;

[0020] Figure 4 This is a flowchart illustrating the calibration method of the ATE channel delay automatic calibration circuit in some embodiments of the present invention;

[0021] Figure 5 This is a schematic diagram of the structure of an electronic device in some embodiments of the present invention.

[0022] Figure Labels

[0023] 1. FPGA (Field Programmable Gate Array); 2. IO Channel board: Input / output channels;

[0024] 3. Connector; 4. Cable; 5. Pogo pin;

[0025] 6. PB: Substrate; 7. Socket: Socket; 8. DUT: Device Under Test; 9. Driver: Driver;

[0026] 10. Receiver; 11. DC calibration circuit; 12. PMU: Precision Measurement Unit; 13. Switching network; 14. PDL: Line Delay Unit; 15. TDC: Carry Chain;

[0027] 16. Pattern Circuit: Sample circuit. Detailed Implementation

[0028] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0029] refer to Figure 1 The diagram illustrates the operating state where the ATE needs to ensure that the signals output by the FPGA simultaneously reach the pins of the DUT. The specific explanations of the various reference numerals are as follows:

[0030] ATE: Automatic Test Equipment; IO Channel board (2): Input / output channel (layer), or simply IO channel; DUT (8): Device Unit Test, chip under test; Socket (7): Socket, the chip is installed in the Socket when testing the chip; PB (6): Performance Board, the adapter board between the test head and the Socket; Pogo Pin (5): It is a spring pin that dynamically connects the test head channel cable and the PB (6) interface board; Cable (4): It is the cable that connects the Pogo Pin (5) and the IO channel outlet connector; Connector (3): IO channel circuit outlet connector; Driver (9): The driver of the IO channel; Receiver (10): The receiver of the IO channel is usually implemented by a comparator; FPGA (1): The hardware that implements the core logic of the timing generator and template test, controlling the receiving and sending of the Driver (9) and Receiver (10). F, A, B, C, and D are the marker points for timing calibration measurements of each interface. The delay between the A and B interfaces is currently controlled by adjusting the PCB trace length. However, the Driver (9) and Receiver (10) chips themselves have significant drift, and the delay is not a fixed value, which affects the overall signal deviation accuracy.

[0031] In view of this, in some embodiments of the present invention, an automatic ATE channel delay calibration circuit is set between the above-mentioned measurement interfaces A and B to measure and calibrate the delay in different channels. Specifically, a first aspect of the present invention provides an automatic ATE channel delay calibration circuit, comprising: a main transceiver pin, multiple auxiliary transceiver pins, a switch network, a delay measurement module, and a delay calibration module. The main transceiver pin is located at the interface between the FPGA and the ATE input / output channel, and is electrically connected to the ATE input / output channel and the delay measurement module, respectively. The switch network is electrically connected to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively. The delay measurement module is located inside the FPGA and is used to send pulses to the main transceiver pin, the multiple auxiliary transceiver pins, and the ATE input / output channel, respectively; and to receive the pulses transmitted by the main transceiver pin or the multiple auxiliary transceiver pins and measure the delay of the ATE input / output channel accordingly. The delay calibration module is used to compensate the input channel and output channel respectively based on the measured delay of the ATE input / output channel.

[0032] Specifically, Figure 2 In China Figure 1Based on this, multiple auxiliary transceiver pins and a switching network (13) controlling different loops are added; an AC calibration circuit (11) is used to calibrate the DC characteristics of the precision measurement unit or the ATE channel delay automatic calibration circuit; a PMU (12) is used to precisely measure the delay of the Driver (9) and Receiver (10) in one or more drivers of the IO channel or to control the delay. The delay calibration module includes a PDL (14) and a TDC (15), where the TDC (15) is used to measure the delay of the Driver (9) and Receiver (10) in the ATE input and output channels, and the PDL (14) is used to compensate the input and output channels respectively according to the measured delay of the ATE input and output channels.

[0033] In some embodiments of the present invention, the switch network (13) includes a first switch, a second switch, and a third switch. The input terminal of the first switch is connected to the delay measurement module through a first auxiliary transceiver pin, and its output terminal is connected to multiple auxiliary transceiver pins, the second switch, and the third switch, respectively. The input terminal of the second switch is connected to the delay measurement module through a main transceiver pin, and its output terminal is connected to the first switch and the third switch, respectively. The input terminal of the third switch is connected to the delay measurement module through a main transceiver pin, and its output terminal is connected to the first switch and the second switch, respectively.

[0034] Specifically, refer to Figure 3 The switch network (13) includes S0, S1, and S2, corresponding to the first switch, the second switch, and the third switch, respectively. Based on this, to control different measurement circuits, switches S3, S4, S5, S6, and S7 are added to control the transmit measurement circuit, the receive measurement circuit, the transmit calibration circuit, and the receive calibration circuit. T0 and R0 are the transmit and receive pins of the main transceiver pins, respectively; R1 and RT1 are the auxiliary transceiver pins. Further, Figure 3 The components in the process satisfy the following conditions:

[0035] 1. The distance from A to U for all channels is L0; that is: RT1 to S0.1 (U interface): L0; R1 to U interface: L0; T0 to S1.1 (U interface): L0 (including chip package delay); R0 to S2.1 (U interface): L0 (including chip package delay);

[0036] 2. L1: Internal delay of the high-speed relay;

[0037] 3. L2: This refers to the routing delay between S0, S1, and S2. These routing segments are of equal length. All channels adhere to this routing rule.

[0038] 4. When routing PCB traces, specify L2 = 2n * L1, L0 = m * L0, where n and m are natural numbers, and the specific numbers are determined by the PCB layout. This relationship is agreed upon to facilitate the calculation of the delay length of each segment later.

[0039] 5. S1.3 to S3.3: This section of the trace is limited to less than 1ps (to reduce signal reflection);

[0040] 6. S3 to S5: This section of the trace is limited to less than 1ps (to reduce signal reflection).

[0041] In some embodiments of the present invention, the delay measurement module forms multiple measurement loops through a switch network, a main transceiver pin, multiple auxiliary transceiver pins, and an ATE input / output channel. The multiple measurement loops are used to measure the transmission delay or reception delay of the switch network and the main transceiver pin, multiple auxiliary transceiver pins, and the ATE input / output channel, respectively.

[0042] Furthermore, the plurality of measurement loops include a first measurement loop, a second measurement loop, and a third measurement loop. In the first measurement loop, a first pulse emitted by the delay measurement module passes sequentially through the transmit pin of the auxiliary transceiver pin, the switch network, and the first receive pin of the auxiliary transceiver pin before reaching the delay measurement module. In the second measurement loop, a second pulse emitted by the delay measurement module passes sequentially through the transmit pin of the main transceiver pin, the ATE output channel, the switch network, and the second receive pin of the auxiliary transceiver pin before reaching the delay measurement module. In the third measurement loop, a third pulse emitted by the delay measurement module passes sequentially through the transmit pin of the auxiliary transceiver pin, the switch network, the ATE input channel, and the receive pin of the main transceiver pin before reaching the delay measurement module.

[0043] In the above embodiments, the delay calibration module includes a line delay unit, which compensates for the input and output channels of the ATE based on the delay measured by the delay measurement module.

[0044] Specifically, delay compensation includes the following steps:

[0045] 1. Assuming the system has Z IO channels, we measure the propagation delays DelayBR0[X] and DelayRT1R0[X] from T0 and R0 to the B interface through Driver(9) and Comparator(10) using the above method. Among them, Comparator is a Receiver implementation.

[0046] 2.DelayBR0Max=max{DelayBR0[1],...,DelayBR0[Z]}.

[0047] 3.DelayRT1R0Max=max{DelayRT1R0[1],...,DelayRT1R0[Z]}.

[0048] 4. Calculate the delay compensation for each channel (X = 1, ..., Z):

[0049] Send compensation: T0Compensation[x] = DelayRT1R0Max - DelayRT1R0[x],

[0050] Receive compensation: R0Compensation[x] = DelayBR0Max - DelayBR0[x].

[0051] 5. Configure T0Compensation[x] in front of PDL(14) of the x channel T0 transmitting unit, then the data transmitted by all channels Pattern Circuit(16) will arrive at interface B at the same time, completing the internal transmitting circuit delay calibration.

[0052] 6. R0Compensation[x] is configured to PDL(14) in front of the R0 receiving unit of channel x. Then all channels and the signals of the B interface pass through Comparator(10) and arrive at Pattern Circuit(16) at the same time to complete the internal receiving circuit delay calibration.

[0053] Example 2

[0054] refer to Figure 3 In a second aspect, the present invention provides a calibration device based on the ATE channel delay automatic calibration circuit of the first aspect of the present invention, comprising: a DC calibration circuit (11) connected to the ATE input / output channel and its precision measurement unit PMU (12) respectively via a switch network (13), for calibrating the DC characteristics of the precision measurement unit PMU (12) or the ATE channel delay automatic calibration circuit.

[0055] refer to Figure 4 A third aspect of the present invention provides a calibration method for an ATE channel delay automatic calibration circuit based on the first aspect of the present invention, comprising: S100. taking the main transceiver pin, multiple auxiliary transceiver pins, the contacts of the switch network, the delay measurement module, and the contacts of the ATE input / output channel as measurement points, and constructing multiple measurement loops based on one or more of the measurement points; S200. calculating the delay between every two measurement points between the FPGA interface and the ATE channel interface according to each measurement loop, and calculating the delay of the ATE channel according to it; S300. compensating the input channel and output channel of the ATE channel according to the delay of the ATE channel.

[0056] Example 3

[0057] refer to Figure 5 In a fourth aspect, the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the calibration method of the ATE channel delay automatic calibration circuit of the third aspect of the present invention.

[0058] Electronic device 500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from storage device 508 into random access memory (RAM) 503. RAM 503 also stores various programs and data required for the operation of electronic device 500. The processing unit 501, ROM 502, and RAM 503 are interconnected via bus 504. Input / output (I / O) interface 505 is also connected to bus 504.

[0059] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, hard disks; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 5 Each box shown can represent a device or multiple devices as needed.

[0060] Specifically, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, it performs the functions defined in the methods of embodiments of this disclosure. It should be noted that the computer-readable medium described in embodiments of this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0061] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more computer programs, which, when executed by the electronic device, cause the electronic device to:

[0062] Computer program code for performing the operations of embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, C++, and Python—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0063] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An ATE channel latency auto-calibration circuit, characterized by, The application relates to a time delay calibration method and device for an FPGA (Field Programmable Gate Array) and an ATE (Automatic Test Equipment) input-output channel. The main transceiving pin is located at the interface between the FPGA and the ATE input-output channel and is electrically connected with the ATE input-output channel and the time delay measurement module respectively. The switch network is electrically connected with the main transceiving pin, the plurality of auxiliary transceiving pins and the ATE input-output channel respectively. The time delay measurement module is located in the FPGA and is used for sending pulses to the main transceiving pin, the plurality of auxiliary transceiving pins and the ATE input-output channel respectively and receiving the pulses transmitted by the main transceiving pin or the plurality of auxiliary transceiving pins and measuring the time delay of the ATE input-output channel according to the pulses; the time delay measurement module forms a plurality of measurement loops with the main transceiving pin, the plurality of auxiliary transceiving pins and the ATE input-output channel through the switch network, and the plurality of measurement loops are used for measuring the sending time delay or the receiving time delay of the switch network, the main transceiving pin, the plurality of auxiliary transceiving pins and the ATE input-output channel respectively. The plurality of measurement loops comprise a first measurement loop, a second measurement loop and a third measurement loop; the first measurement loop is formed by a first pulse sent by the time delay measurement module, the first pulse sequentially passes through the transmitting pin of the auxiliary transceiving pin, the switch network and the first receiving pin of the auxiliary transceiving pin and then reaches the time delay measurement module; the second measurement loop is formed by a second pulse sent by the time delay measurement module, the second pulse sequentially passes through the transmitting pin of the main transceiving pin, the ATE output channel, the switch network and the second receiving pin of the auxiliary transceiving pin and then reaches the time delay measurement module; and the third measurement loop is formed by a third pulse sent by the time delay measurement module, the third pulse sequentially passes through the transmitting pin of the auxiliary transceiving pin, the switch network, the ATE input channel and the receiving pin of the main transceiving pin and then reaches the time delay measurement module. The time delay calibration module is used for compensating the input channel and the output channel according to the measured time delay of the ATE input-output channel. The switch network comprises a first switch, a second switch and a third switch; the input end of the first switch is connected with the time delay measurement module through the first auxiliary transceiving pin, and the output end of the first switch is connected with the plurality of auxiliary transceiving pins, the second switch and the third switch respectively; 2. The ATE channel latency auto-calibration circuit of claim 1, wherein, The input end of the second switch is connected with the time delay measurement module through the main transceiving pin, and the output end of the second switch is connected with the first switch and the third switch respectively; The input end of the third switch is connected with the time delay measurement module through the main transceiving pin, and the output end of the third switch is connected with the first switch and the second switch respectively. The first switch, the second switch and the third switch are all multi-selection high-speed switches.

3. The ATE channel latency auto-calibration circuit of claim 2, wherein, The wiring distances among the first switch, the second switch and the third switch are equal.

4. The ATE channel latency auto-calibration circuit of claim 2, wherein, The time delay calibration module comprises a line delay unit, and the line delay unit compensates the input channel and the output channel according to the time delay of the ATE input-output channel measured by the time delay measurement module.

5. The ATE channel latency auto-calibration circuit of any of claims 1 to 4, wherein, The application relates to a time delay calibration method and device for an FPGA (Field Programmable Gate Array) and an ATE (Automatic Test Equipment) input-output channel.

6. A calibration apparatus based on the ATE channel latency auto-calibration circuit of claim 1, characterized by, ​ The DC calibration circuit is connected with the ATE input and output channels and their accurate measurement units respectively through a switch network, and is used for calibrating the DC characteristics of the accurate measurement units or the ATE channel delay automatic calibration circuit.

7. A calibration method based on the ATE channel latency auto-calibration circuit of claim 1, characterized in that, The method comprises: Taking the main transceiver pin, the plurality of auxiliary transceiver pins, the contact points of the switch network, the time delay measurement module and the contact points of the ATE input and output channels as measurement points, and constructing a plurality of measurement loops according to one or more of the measurement points; According to each measurement loop, the time delay between each two measurement points between the FPGA interface and the ATE channel interface is calculated respectively, and the time delay of the ATE channel is calculated according to the time delay; According to the time delay of the ATE channel, compensation is made to the input channel and the output channel of the ATE channel respectively.

8. The method of calibrating an ATE channel latency auto-calibration circuit of claim 7, wherein, The delay compensation of the corresponding channels of the plurality of ATE channels is configured by the internal line delay unit of the FPGA.

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