Board level interconnect bga joint thermal fatigue life prediction method, test piece and system

Abstract

The application discloses a kind of board-level interconnect BGA weld spot thermal fatigue life prediction method, test piece and system, belong to electronic package board-level interconnect field, including steps: S1, make BGA package board-level interconnect test piece;S2, temperature cycle test is carried out to the BGA package board-level interconnect test piece, and the coefficient based on the measured Darveaux theory equation is obtained;S3, the average plastic strain energy density increment of the theoretical single stable cycle of BGA weld spot in any position in packaging interconnect region is obtained by establishing finite element model, and is brought into the Darveaux theory equation based on the coefficient obtained using step S2 and constructs thermal fatigue life prediction, realize the thermal fatigue life prediction of the weld spot.The application can quickly, accurately predict the thermal fatigue life of interconnect weld spot, support weld spot reliability fault quantization analysis research, provide key data support for the reliability design of BGA package board-level interconnect product.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic packaging board-level interconnection, and more particularly to a board-level interconnection BGA solder joint thermal fatigue life prediction method, test piece and system. BACKGROUND

[0002] High-density integrated BGA (ceramic ball grid array) packaging units adopting plastic or ceramic packaging integrate radio frequency and digital signal I / O interfaces on a system motherboard through reflow soldering of a packaging substrate to realize high-density signal transmission. Normal products will undergo temperature cycle environmental adaptability tests or power cycles during normal operation. After multiple temperature or power cycles, the interconnection solder joints will change significantly in interconnection resistance due to the accumulation of plastic strain, creep and other effects, and even the interconnection will be disconnected, directly affecting the grounding effect or radio frequency shielding effect. Therefore, during product design, the selection of devices and the structural design of packaging need to be fully considered to predict and improve the thermal fatigue life of the solder joints and avoid the occurrence of the above failures.

[0003] The thermal fatigue life is usually estimated by using the Darveaux theoretical equation based on energy, and the equation is as follows:

[0004]

[0005] The first term in the Darveaux theoretical equation is related to the period of initial crack generation, and the second term is related to crack propagation. The equation involves coefficients K1-K4 that are strongly related to the packaging topology type and material system. When the packaging topology type and material system are not clear, K1-K4 are unknown quantities, and must be calibrated for a specific packaging structure to obtain accurate fatigue life prediction results.

[0006] Chinese patent CN201510226672.9 improves the Darveaux equation by referring to the Paris formula, and gives a correction method related to the crack propagation term from the perspective of theoretical calculation, but does not clearly indicate how to calibrate the packaging coefficients K1-K4. Chinese patent CN201710365258.5 proposes a BGA solder joint thermal fatigue life prediction method and system from the perspective of theoretical calculation, model training and computing resource allocation. The method involved is evolved from the Coffin-Manson equation, and does not involve the calculation or coefficient calibration related to the Darveaux theoretical equation.

[0007] The Chinese patent CN202110294578.2 discloses a numerical simulation method for BGA board-level interconnection under alternating temperature load of packaging unit, mainly using finite element method to calculate the stress, strain and strain energy density of BGA solder joint, and using Darveaux empirical equation based on energy to calculate the characteristic cycle life. The patent accurately calculates the stress, strain and average plastic strain energy density increment AW of the dangerous solder joint in a single stable cycle ave , but the coefficients of the Darveaux theoretical equation used are derived from literature and have not been measured and calibrated, and the accuracy of solder joint life prediction needs to be improved. SUMMARY

[0008] The purpose of the present application is to overcome the shortcomings of the prior art, provide a board-level interconnection BGA solder joint thermal fatigue life prediction method, test piece and system, which can quickly and accurately predict the thermal fatigue life of the interconnection solder joint, support the quantitative analysis of solder joint reliability failure, provide key data support for the reliability design of BGA packaging board-level interconnection products, etc.

[0009] The purpose of the present application is achieved by the following scheme:

[0010] A board-level interconnection BGA solder joint thermal fatigue life prediction method, comprising the following steps:

[0011] S1, making a BGA packaging board-level interconnection test piece: including making a packaging substrate and a system motherboard, the system motherboard including a single-sided or double-sided mounting board, a plurality of BGA packaging soldering areas of different topologies and same or different material systems are arranged in a distributed manner, the packaging substrate and the system motherboard have intercoupled patterned pads in the corresponding areas, and the resistance chain is formed after soldering; the resistance chains in different areas are led out through multi-layer wiring inside the printed board, and a multi-core connector mounting position is reserved in the leading-out area;

[0012] S2, performing temperature cycle test on the BGA packaging board-level interconnection test piece to obtain the coefficients of the Darveaux theoretical equation based on the measured data;

[0013] S3, obtaining the theoretical average plastic strain energy density increment AW' of the BGA solder joint at any position in the packaging interconnection area in a single stable cycle by establishing a finite element model ave , and bringing AW' ave into the Darveaux theoretical equation constructed based on the measured coefficients obtained in step S2 to estimate the thermal fatigue life, thereby realizing the thermal fatigue life prediction of the solder joint.

[0014] Further, in step S1, the topology type refers to the physical structure form of the packaging substrate and the BGA solder joint structure form; the material system includes the material of the packaging substrate, the material of the patterned pads on the substrate, and the BGA solder joint material, and the topology type and the material system are determined for a specific BGA package.

[0015] Further, in step S1, a periodic discontinuous bone-shaped pad structure is made on each of the packaging substrate upper surfaces by a patterning process, and there are 4 circles of pad patterns, and the pad pattern surface meets the solderability requirements.

[0016] Further, in step S1, the pad patterns on the packaging substrate are distributed in a ring shape, each circle of patterns has the packaging substrate center as the center and R1, R2, R3, and R4 as the radii, and the principle that the strain energy of the BGA solder joint is strongly related to the distance from the packaging substrate center is used to ensure that the average plastic strain energy density increment ΔW ave of any BGA solder joint in the same circle on the packaging substrate after the BGA interconnection with the system motherboard is theoretically single stable and cyclic.

[0017] Further, in step S1, the system motherboard is made with a periodic discontinuous bone-shaped pad structure in the soldering area with the packaging substrate, and there are 4 circles of pad patterns in each area, and a metallized hole is made in the center of the bone-shaped pad of the signal lead-out end for connecting the inner layer wiring of the system motherboard; the patterned pads on the system motherboard and the pad patterns on the packaging substrate are intercoupled, and the pad pattern surface meets the solderability requirements.

[0018] Further, in step S1, the patterned pads with intercoupling refer to the end parts of the bone-shaped pad structures in the 1st, 2nd, 3rd, and 4th circles of pad patterns on the packaging substrate and the end parts of the bone-shaped pad structures in the 1st, 2nd, 3rd, and 4th circles of pad patterns on the system motherboard after being interconnected by BGA solder joints, forming a closed and uninterrupted resistance chain.

[0019] Further, in step S2, the BGA package board-level interconnection test piece made in step S1 is subjected to a temperature cycle test, the interface connecting line of the multi-core connector is a high and low temperature resistant wire, the high and low temperature resistant wire is connected with a low resistance test equipment, the number of test channels is consistent with the number of resistance chains to be tested, and four-wire method is used for measuring resistance in each test channel;

[0020] The resistance chain of a certain packaging substrate under a specific topology type and material system on the system motherboard is monitored online until the interconnection fails, and the temperature cycle resistance of 4 groups of resistance chains is recorded as N w1 , N w2 , N w3 , N w4 , and the thermal fatigue life of each resistance chain is equivalent to the measured thermal fatigue life.

[0021] Further, in step S3, the BGA package board-level interconnection test piece made in step S1 is subjected to finite element simulation modeling, and the average plastic strain energy density increment AW of each BGA solder joint in the four groups of resistance chains is calculated in turn by selecting any solder joint in each group of resistance chains. ave 1, AW ave 2, AW ave 3, AW ave 4, and the following four groups of formulas are constructed on the basis of the Darveaux theoretical equation:

[0022]

[0023]

[0024]

[0025]

[0026] In the formula, a is the equivalent diameter of the contact area of the BGA solder joint and the substrate, which is a known quantity, and K1', K2', K3', and K4' are four constants obtained by solving, which are the coefficients of the Darveaux theoretical equation for thermal fatigue life calculation under the specific topology type and material system based on the actual measurement.

[0027] A test piece for predicting the thermal fatigue life of a board-level interconnection BGA solder joint, comprising a package substrate and a system motherboard, the system motherboard comprising a single-sided or double-sided mounting board, a plurality of BGA package soldering areas of different topologies and material systems being arranged in a distributed manner, the package substrate and the system motherboard having corresponding areas with intercoupled patterned pads, and the resistance chains being formed after soldering; the resistance chains in different areas are led out through multi-layer wiring inside the printed board, and the leading-out area is provided with a reserved multi-core connector mounting position.

[0028] A system for predicting the thermal fatigue life of a board-level interconnection BGA solder joint, comprising the test piece as described above, and a temperature environment test box and an external test data processing and display system, the temperature environment test box being provided with a low-resistance test device, the resistance chains in the test piece being connected to the low-resistance test device through the interface connection of the multi-core connector, and the low-resistance test device being connected to the external test data processing and display system.

[0029] The beneficial effects of the present application include:

[0030] The method designs a test piece, realizes on-line monitoring of interconnection resistance chains of different BGA packages after double-sided mounting on the same system motherboard, further realizes calibration of coefficients of the Darveaux theoretical equation through the method combining actual measurement with simulation, and can quickly and accurately predict the thermal fatigue life of the interconnection solder joint by using the calibrated equation, supports quantitative analysis of solder joint reliability failure, and provides key data support for reliability design of BGA package board-level interconnection products. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 It is a perspective view of a package substrate, and the shaded part is a patterned pad.

[0033] Figure 2 It is a top view of a system motherboard in a butt-welding area with a package substrate, and the shaded part is a patterned pad.

[0034] Figure 3 It is a schematic diagram of resistance chains formed by patterned pads coupled to each other after butt-welding of a package substrate and a system motherboard; 1a and 1b respectively represent the start and end of a first resistance chain, 2a and 2b respectively represent the start and end of a second resistance chain, and so on, and there are four resistance chains in total.

[0035] Figure 4 It is a front view of a package substrate after butt-welding with a system motherboard, and the dashed line represents a resistance chain.

[0036] Figure 5 It is a front view of a complex system motherboard BGA pad distributed arrangement and multi-layer wiring (different line types represent different layer wiring).

[0037] Figure 6 It is a back view of a complex system motherboard BGA pad distributed arrangement and multi-layer wiring (different line types represent different layer wiring).

[0038] Figure 7 It is a front view of a package substrate and a complex system motherboard BGA board-level interconnection.

[0039] Figure 8 It is a schematic diagram of a test system.

[0040] In the figure, 1 - package substrate, 2 - patterned pads on the package substrate, 3 - system motherboard, 4 - patterned pads on the system motherboard, 5 - metallized holes, 6 - resistance chain 1, 7 - resistance chain 2, 8 - resistance chain 3, 9 - resistance chain 4, 10 - BGA solder ball, 11 - complex system motherboard, 12 - inner layer wiring in the complex system motherboard, 13 - multi-core connector mounting area, 14 - BGA package substrate solder pad pattern area, 15 - multi-core connector, 16 - BGA package board-level interconnection test piece, 17 - temperature environmental test chamber, 18 - interface connection, 19 - low resistance test equipment, 20 - test data processing and display system, 101 - represents a BGA package under a certain topology type and material system, which is referred to as 101 BGA package in the following specific embodiment description, 102 - represents another BGA package under a certain topology type and material system, which is referred to as 102 BGA package in the following specific embodiment description. DETAILED DESCRIPTION

[0041] All features disclosed in the embodiments of the present specification, or all steps in the methods or processes impliedly disclosed, can be combined and / or extended, replaced, in any manner, except for mutually exclusive features and / or steps.

[0042] Compared with the scheme in the prior art that the coefficients of the Darveaux theoretical equation are derived from the literature, the inventors of the present application have made creative thinking and adopted a method combining measurement with theory, aiming to solve the problems in the background. One of the purposes of the embodiments of the present application is to provide a board-level interconnection BGA solder joint thermal fatigue life prediction method, aiming to improve the accuracy of solder joint life prediction, and the main technical idea is that: the bone-shaped pads are realized by patterning in the surface pad area of the package substrate, and the bone-shaped pads are realized by the printed board patterning process in the surface pad area of the system motherboard, the bone-shaped pads on the package substrate and the system motherboard form a mutual coupling structure, and after reflow soldering, each circle forms a continuous resistance chain. In the specific implementation process, the temperature cycle resistance of each circle of resistance chain is obtained by online resistance monitoring as the measured thermal fatigue life, and then the average plastic strain energy density increment AW of the dangerous solder joint in each circle of resistance chain in a single stable temperature cycle is calculated by using the finite element method. ave , and the coefficients of the Darveaux theoretical equation are calibrated with this as input, and finally the rapid and accurate prediction of the thermal fatigue life of the board-level interconnection solder joint is realized.

[0043] In the specific implementation process, the technical scheme of the board-level interconnection BGA solder joint thermal fatigue life prediction provided by the present application further includes the following invention points in the specific implementation process:

[0044] The invention point (1) is that a BGA package board-level interconnection test piece is made, which includes a package substrate and a system motherboard, the system motherboard can be a single-sided or double-sided mounting board, a plurality of BGA package welding areas of different topological types and material systems are distributed, the package substrate and the system motherboard have intercoupled patterned pads in the corresponding areas, and a resistance chain is formed after welding. The resistance chains of different areas are led out through the internal multilayer wiring of the printed board, the multi-core connector mounting position is reserved in the leading-out area, and the pad pattern structure and the internal wiring of the printed board are shown as Figure 5 、 Figure 6 ;

[0045] The topological type refers to the physical structure form of the package substrate and the structure form of the BGA welding point, the material system includes the material of the package substrate, the material of the patterned pad on the substrate, and the material of the BGA welding point, and the topological type and the material system are determined for a specific BGA package.

[0046] The invention point (2) is that the BGA package board-level interconnection test piece described in the invention point (1) is described, a plurality of package substrates of different topological types and material systems are distributed, a periodic discontinuous bone-shaped pad structure is made on the upper surface of each package substrate through a patterning process, and there are 4 circles of pad patterns, the surface of the pad pattern meets the weldability requirement, and the detailed structure is shown as Figure 1 ;

[0047] In particular, the pad pattern on the package substrate is distributed in a ring shape, each circle of pattern has the center of the package substrate as the center and R1, R2, R3, and R4 as the radii, since the strain energy of the BGA welding point is strongly related to the distance from the center of the package substrate, it is ensured that the average plastic strain energy density increment ΔW ave of any BGA welding point in the same circle within a single stable cycle after the BGA interconnection of the package substrate and the system motherboard is the same.

[0048] The invention point (3) is that the BGA package board-level interconnection test piece described in the invention point (1) is involved, a periodic discontinuous bone-shaped pad structure is made in the welding area of the package substrate, there are 4 circles of pad patterns in each area, a metallized hole is made in the center of the bone-shaped pad at the signal leading-out end for connecting the internal wiring of the system motherboard, and the detailed structure is shown as Figure 2 . The patterned pad on the system motherboard is intercoupled with the pad pattern on the package substrate in step (2), and the surface of the pad pattern meets the weldability requirement;

[0049] The intercoupling of the pad pattern is shown in detail in Figure 3, is to form a closed discontinuous resistance chain after the end of the bone-shaped pad structure in the 1st, 2nd, 3rd and 4th pad patterns on the packaging substrate and the end of the bone-shaped pad structure in the 1st, 2nd, 3rd and 4th pad patterns on the system motherboard are interconnected by BGA solder joints, and the signal flow is as shown in Figure 4 .

[0050] The invention point (4) is that the BGA packaging board-level interconnection test piece is subjected to temperature cycle test, the interface wire of the multi-core connector in the invention point (1) is a high and low temperature resistant wire and the resistance of a single wire is not more than 0.15Ω, the high and low temperature resistant wire is connected with a low resistance test equipment, the number of test channels is consistent with the number of resistance chains to be tested, and four-wire method is used for testing resistance of each test channel;

[0051] In particular, the resistance chains of a certain packaging substrate under a specific topology type and material system on the system motherboard are monitored online until the interconnection fails (the interconnection resistance value exceeding 20% of the initial resistance value is considered to fail), and the temperature cycle resistance of the four groups of resistance chains is recorded as N w1 , N w2 , N w3 , N w4 , and is equivalent to the thermal fatigue life actually measured for each resistance chain;

[0052] In particular, a finite element simulation model is established for the BGA packaging board-level interconnection test piece in the invention points (1) to (3), any solder joint in each resistance chain is selected, and the average plastic strain energy density increment AW ave 1, AW ave 2, AW ave 3, AW ave 4 are calculated in turn, and the following four groups of formulas are constructed on the basis of formula (1):

[0053]

[0054]

[0055]

[0056]

[0057] In the formula, a is the equivalent diameter of the contact area between the BGA solder joint and the substrate, which is a known quantity, and K1', K2', K3' and K4' are four constants obtained by simultaneous solution by programming with Matlab, that is, the coefficients of the Darveaux theoretical equation for thermal fatigue life calculation under the specific topology type and material system.

[0058] The fifth invention point is that, for the BGA package board-level interconnection structure (the array arrangement form of the BGA solder joint on the substrate is not limited) with the same topological type and material system as the first invention point to the third invention point, the average plastic strain energy density increment AW of the BGA solder joint at any position in the package interconnection area in a single stable cycle is obtained by establishing a finite element model a ve The thermal fatigue life prediction of the solder joint can be realized by using formula (6);

[0059]

[0060] The sixth invention point is that, the BGA package with the topological type and material system corresponds to only one set of coefficients of the Darveaux theoretical equation, and for other BGA packages with different topological types and material systems arranged on the system motherboard, the coefficient calibration of the Darveaux theoretical equation can be realized in batches by using the processing method in the fourth invention point, the thermal fatigue life calculation is not limited by the array arrangement form of the BGA solder joint, and the rapid and accurate prediction of the thermal fatigue life of the BGA board-level interconnection solder joint under various topological types and material systems in engineering application is flexibly met.

[0061] The embodiment of the present application provides a board-level interconnection BGA solder joint thermal fatigue life prediction method, and the specific implementation process comprises the following steps:

[0062] As shown in Figure 1 , a package substrate 1 is manufactured, and a periodic discontinuous patterned pad 2 (bone type in the embodiment) on the package substrate is realized by a graphic process, in the specific implementation, the typical thickness of the package substrate 1 can be 2 mm, the typical diameter of the pad on the package substrate 1 can be 0.45 mm, and the pad meets the weldability requirement. Wherein, R1-R4 all represent the pad diameter, which can be taken as: R1=2mm, R2=3.2mm, R3=4.5mm, R4=5.75mm in the embodiment;

[0063] As shown in Figure 2 , a periodic discontinuous patterned pad 4 (bone type in the embodiment) on the system motherboard is manufactured on the surface of the system motherboard 3 opposite to the package substrate 1, and the pad and the periodic discontinuous bone type patterned pad on the package substrate 1 form a mutual coupling structure, in the embodiment, the typical thickness of the system motherboard 3 is 3 mm, the typical diameter of the pad on the system motherboard 3 is 0.45 mm, and the pad meets the weldability requirement.

[0064] After the package substrate 1 and the system motherboard 3 are welded by BGA solder balls (or also called BGA solder columns, the solder balls and the solder columns are essentially equivalent in the embodiment) 10 through a reflow furnace, a structure as shown in Figure 3 ​The shown closed uninterrupted resistance chain (resistance chain one 6, resistance chain two 7, resistance chain three 8, resistance chain four 9), 1a, 1b respectively represent the start and end of the first resistance chain, 2a, 2b respectively represent the start and end of the second resistance chain, and so on, a total of four. Figure 4 The dashed line part with an arrow indicates the resistance chain signal path.

[0065] As shown in Figure 5 , Figure 6 , according to step (1), a plurality of packaging substrates with bone-shaped patterned pads of different topological types and material systems are prepared, and according to step (2), a complex system motherboard 11 is prepared, which is characterized in that a plurality of BGA packaging substrate welding pad pattern areas 14 are distributed on the same system motherboard, multi-layer wiring is used to realize the resistance chain leading out of different areas to the multi-core connector mounting area 13, and the resistance chain of each BGA package is connected to the inner layer wiring 12 in the system motherboard through the metallized hole 5.

[0066] Different sizes of BGA packaging substrates and multi-core connectors 15 are welded to the corresponding areas of the complex system motherboard 11 to form a BGA packaging board-level interconnection test piece 16.

[0067] The distributed BGA packaging board-level interconnection resistance online test system is shown in Figure 8 During the entire test process, the BGA packaging board-level interconnection test piece 16 is placed in a temperature environment test box 17 (high temperature 100℃, low temperature -40℃, holding time 30min, high and low temperature conversion time 5min), the resistance chain in the test piece is connected to the low resistance test equipment 19 through the interface connection of the multi-core connector 15, and the external test data processing and display system 20 is connected.

[0068] One of the characteristics of the embodiment of the present application is that the interface connection 18 of the multi-core connector 15 is a high and low temperature resistant wire, and the resistance of a single wire is 0.12Ω. In this example, the number of test channels of the low resistance test equipment is 32, four-wire method is used to measure resistance for each test channel, temperature trigger mode is used for resistance online sampling, and sampling is performed every 10min during the high and low temperature holding stage.

[0069] According to the test data of each channel, the resistance dynamic change process curve of each resistance chain during the entire test period is drawn, the resistance value not exceeding 20% of the initial value is taken as the failure criterion, and the temperature cycle resistance of each resistance chain is determined.

[0070] Select Figure 7 BGA packages of two different topological types and material systems 101 and 102 are selected as examples: for the 101 BGA package, the temperature cycle resistance of the four resistance chains is measured as: N101_w1 = 978, N 101_w2 = 1269, N 101_w3 = 1463, N 101_w4 = 1832, the finite element simulation model was built to calculate the average plastic strain energy density increment AW in a single stable cycle of the dangerous solder joint in each resistance chain in the 101 package 101_ave 1 = 0.40825 MPa, AW 101_ave 2 = 0.3235 MPa, AW 101_ave 3 = 0.2851 MPa, AW 101_ave 4 = 0.2335 MPa, the coefficients of the Darveaux theoretical equation are calibrated as follows:

[0071]

[0072]

[0073]

[0074]

[0075] In the formula, a is the equivalent diameter of the BGA solder joint and the substrate contact area, a = 0.52 mm in this example, and four coefficients K' are obtained by simultaneous solution using Matlab programming 101_1 = 17.63, K' 101_2 = -1.58, K' 101_3 = 1.51 x 10 -3 , K' 101_4 = 1.08.

[0076] For any solder joint of other size BGA packages of the 101 topology type and material system, only the average plastic strain energy density increment AW' in a single stable cycle of the solder joint is obtained by finite element simulation 101_ave , then the thermal fatigue life can be quickly and accurately predicted according to the following formula without repeated experiments:

[0077]

[0078] For the 102 BGA package, the temperature cycle resistance times of the four resistance chains were measured as follows: 102_w1 = 615, N 102_w2 = 766, N 102_w3 = 895, N 102_w4 = 1076, the finite element simulation model was built to calculate the average plastic strain energy density increment AW in a single stable cycle of the dangerous solder joint in each resistance chain in the 102 BGA package 102_ave 1 = 0.513, AW 102_ave2 = 0.423, ΔW 102_ave 3 = 0.369, ΔW 102_ave 4 = 0.314, the coefficients of the Darveaux theoretical equation are calibrated as follows:

[0079]

[0080]

[0081]

[0082]

[0083] wherein a is the equivalent diameter of the BGA solder joint and the contact area of the substrate, a = 0.45 mm in this example, and the four coefficients K' are obtained by simultaneous solution using Matlab programming 102_1 = 18.29, K' 102_2 = -1.38, K' 102_3 = 1.67 x 10 -3 , K' 102_4 = 1.12.

[0084] For other size BGA packages of the 102 topology type and material system, only the average plastic strain energy density increment ΔW' of the solder joint in a single stable cycle is obtained by finite element simulation 102_ave , the thermal fatigue life can be quickly and accurately predicted according to the following formula without repeated experiments:

[0085]

[0086] Example 1

[0087] A method for predicting the thermal fatigue life of a board-level interconnection BGA solder joint, comprising the following steps:

[0088] S1, making a BGA package board-level interconnection test piece: including making a package substrate and a system motherboard, the system motherboard including a single-sided or double-sided mounting board, a plurality of BGA package soldering areas of the same or different topology types and material systems being arranged in a distributed manner, the package substrate and the system motherboard having a patterned pad in the corresponding area, and the resistance chain being formed after soldering; the resistance chains in different areas are led out through multi-layer wiring inside the printed board, and a multi-core connector mounting position is reserved in the leading-out area;

[0089] S2, performing a temperature cycle test on the BGA package board-level interconnection test piece to obtain the coefficients of the Darveaux theoretical equation based on the measured values;

[0090] S3, obtaining the average plastic strain energy density increment AW' of the BGA solder joint at any position in the packaging interconnection region in a single stable cycle by establishing a finite element model ave , and inputting AW' ave into the Darveaux theoretical equation constructed based on the measured coefficients obtained in step S2 to predict the thermal fatigue life, thereby realizing the thermal fatigue life prediction of the solder joint.

[0091] Embodiment 2

[0092] Based on embodiment 1, in step S1, the topology type refers to the physical structure form of the packaging substrate and the structure form of the BGA solder joint; the material system includes the material of the packaging substrate, the material of the patterned pad on the substrate, and the material of the BGA solder joint, and the topology type and the material system are determined for a specific BGA packaging.

[0093] Embodiment 3

[0094] Based on embodiment 1, in step S1, a periodic discontinuous bone-shaped pad structure is made on each of the upper surfaces of the packaging substrates by a patterning process, and there are 4 circles of pad patterns, and the surface of the pad pattern meets the solderability requirement.

[0095] Embodiment 4

[0096] Based on embodiment 1, in step S1, the pad patterns on the packaging substrate are distributed in a ring shape, each circle of pattern has the center of the packaging substrate as the center and R1, R2, R3, and R4 as the radii, and the principle that the strain energy of the BGA solder joint is strongly related to the distance from the center of the packaging substrate is used to ensure that the average plastic strain energy density increment AW ave of any BGA solder joint in a single stable cycle in the same circle of the packaging substrate and the system motherboard BGA interconnection is the same.

[0097] Embodiment 5

[0098] Based on embodiment 1, in step S1, a periodic discontinuous bone-shaped pad structure is made on the packaging substrate, and there are 4 circles of pad patterns in each region, and a metallized hole is made at the center of the bone-shaped pad of the signal lead-out end for connecting the inner layer wiring of the system motherboard; the patterned pad on the system motherboard and the pad pattern on the packaging substrate are coupled, and the surface of the pad pattern meets the solderability requirement.

[0099] Embodiment 6

[0100] On the basis of embodiment 1, in step S1, the patterned pad with mutual coupling refers to the closed and uninterrupted resistance chain formed by the end of the bone-shaped pad structure in the 1st, 2nd, 3rd and 4th pad patterns on the package substrate and the end of the bone-shaped pad structure in the 1st, 2nd, 3rd and 4th pad patterns on the system motherboard after being interconnected by BGA solder joints.

[0101] Embodiment 7

[0102] On the basis of embodiment 1, in step S2, the BGA package board-level interconnection test piece prepared in step S1 is subjected to temperature cycle test, the interface wire of the multi-core connector is a high and low temperature resistant wire, the high and low temperature resistant wire is connected with a low resistance test device, the number of test channels is consistent with the number of resistance chains to be tested, and four-wire method is used for measuring resistance of each test channel;

[0103] The resistance chain of a certain package substrate under a specific topology type and material system on the system motherboard is subjected to online monitoring until the interconnection fails, and the temperature cycle resistance numbers of the four groups of resistance chains are recorded as N w1 , N w2 , N w3 , N w4 , and are equivalent to the thermal fatigue life of each resistance chain actually measured.

[0104] Embodiment 8

[0105] On the basis of embodiment 7, in step S3, the following sub-steps are included: a finite element simulation model is established for the BGA package board-level interconnection test piece prepared in step S1, any solder joint in each circle of resistance chain is selected, and the average plastic strain energy density increment ΔW ave 1, ΔW ave 2, ΔW ave 3, ΔW ave 4 of the BGA solder joint in the four groups of resistance chains are calculated in turn.

[0106]

[0107]

[0108]

[0109]

[0110] In the formula, a is the equivalent diameter of the contact area of the BGA solder joint and the substrate, which is a known quantity, K1', K2', K3' and K4' are four constants obtained by solving, and the coefficients of the Darveaux theoretical equation for thermal fatigue life calculation under the specific topology type and material system based on the actual measurement are obtained.

[0111] Embodiment 9

[0112] A test piece for predicting the thermal fatigue life of a board-level interconnection BGA solder joint, comprising a fabricated package substrate and a system motherboard, the system motherboard comprising a single-sided or double-sided mounting board, a plurality of BGA package soldering areas of different topologies and same or different material systems being arranged in a distributed manner, the package substrate and the system motherboard having corresponding areas with intercoupled patterned pads, and a resistance chain being formed after soldering; the resistance chains in different areas are led out through multilayer wiring inside the printed board, and a multi-core connector mounting position is reserved in the leading-out area.

[0113] Embodiment 10

[0114] A system for predicting the thermal fatigue life of a board-level interconnection BGA solder joint, comprising the test piece as described in Embodiment 9, and a temperature environment test box and an external test data processing and display system, the temperature environment test box being provided with a low-resistance test device, the resistance chains in the test piece being connected to the low-resistance test device through the interface connection of the multi-core connector, and the low-resistance test device being connected to the external test data processing and display system.

[0115] The parts not involved in the present application are the same as or can be realized by the prior art.

[0116] The above technical solution is only one embodiment of the present application, and for those skilled in the art, on the basis of the application disclosed application method and principle, various types of improvements or modifications can be easily made, and are not limited to the method described in the above embodiment, therefore the above-described method is only preferred, and does not have a limiting meaning.

[0117] In addition to the above examples, those skilled in the art can obtain other embodiments by making changes based on the above disclosure or using knowledge or technology in related fields, the features of each embodiment can be interchanged or replaced, and the changes and variations made by those skilled in the art do not deviate from the spirit and scope of the present application, and should be within the protection scope of the appended claims of the present application.

Claims

1. A method for predicting thermal fatigue life of board-level interconnect BGA solder joints, characterized in that: The method comprises the following steps: S1, making BGA package board level interconnection test piece: including making package substrate and system motherboard, the system motherboard includes single-sided or double-sided mounting board, a plurality of topology types are arranged in a distributed manner, and the BGA package welding areas are the same or different in material system, the corresponding areas of the package substrate and the system motherboard have intercoupling patterned pads, and the resistance chain is formed after welding; the resistance chains in different areas are led out through the multilayer wiring inside the printed board, and a plurality of core connector mounting positions are reserved in the leading-out area; in step S1, the pad pattern on the package substrate is distributed in a ring shape, each circle of pattern takes the center of the package substrate as the center, and R1, R2, R3 and R4 are radii, the principle that the strain energy of the BGA welding point is strongly related to the distance from the center of the package substrate is used to ensure that the average plastic strain energy density increment of any BGA welding point on the same circle in a theoretical single stable cycle after BGA interconnection of the package substrate and the system motherboard is the same; S2, temperature cycle test is performed on the BGA package board-level interconnection test piece to obtain coefficients of the Darveaux theoretical equation based on actual measurement; S3, obtaining the average plastic strain energy density increment of the BGA solder joint at any position in the packaging interconnection region in a single stable cycle by establishing a finite element model , and entering the Darveaux theoretical equation constructed based on the coefficients obtained by the step S2 to predict the thermal fatigue life, and realizing the thermal fatigue life prediction of the solder joint.

2. The board level interconnect BGA joint thermal fatigue life prediction method of claim 1, wherein, In step S1, the topology type refers to the physical structure form of the package substrate and the BGA solder joint structure form; the material system includes the material of the package substrate, the material of the patterned pad on the substrate, and the material of the BGA solder joint, and the topology type and the material system are determined for a specific BGA package.

3. The board level interconnect BGA joint thermal fatigue life prediction method of claim 1, wherein, In step S1, a periodic discontinuous bone-shaped pad structure is formed on each of the upper surfaces of the package substrates by a patterning process, and there are a total of 4 pad patterns, and the surface of the pad pattern meets the weldability requirement.

4. The board level interconnect BGA joint thermal fatigue life prediction method of claim 1, wherein, In step S1, a periodic discontinuous bone-shaped pad structure is formed on each of the upper surfaces of the package substrates by a patterning process, and there are a total of 4 pad patterns, and the surface of the pad pattern meets the weldability requirement.

5. The board level interconnect BGA joint thermal fatigue life prediction method of claim 1, wherein, In step S1, the patterned pads with intercoupling refer to the end portions of the bone-shaped pad structures in the first, second, third, and fourth pad patterns on the package substrate and the end portions of the bone-shaped pad structures in the first, second, third, and fourth pad patterns on the system motherboard, which form a closed and uninterrupted resistance chain after being interconnected by BGA solder joints.

6. The board level interconnect BGA joint thermal fatigue life prediction method of claim 1, wherein, In step S2, the BGA package board-level interconnection test piece prepared in step S1 is subjected to a temperature cycle test, the interface connection line of the multi-core connector is a high and low temperature resistant wire, the high and low temperature resistant wire is connected with a low resistance test device, the number of test channels is consistent with the number of resistance chains to be tested, and four-wire method is used for measuring resistance in each test channel. The resistance chain of a certain packaging substrate under a certain topology type and material system on the system motherboard is monitored online until the interconnection failure, and the temperature cycle resistance of 4 groups of resistance chains is recorded in turn: N w1 , N w2 , N w3 , N w4 , and the equivalent thermal fatigue life of each resistance chain is measured.

7. The board level interconnect BGA joint thermal fatigue life prediction method of claim 6, wherein, In step S3, the BGA package board-level interconnection test piece prepared in step S1 is subjected to finite element simulation modeling, and the average plastic strain energy density increment of each solder joint in the four groups of resistance chains is calculated in turn by selecting any solder joint in each circle of resistance chains 、 、 、 and the following four groups of formulas are constructed on the basis of the Darveaux theoretical equation: In the formula, a is the equivalent diameter of the contact area between the BGA solder joint and the substrate, which is a known quantity, K1, K2, K3, and K4 are four constants obtained by solving, and the coefficients of the Darveaux theoretical equation based on actual measurement for the calculation of the thermal fatigue life of the specific topology type and material system are obtained.

8. A test piece for board level interconnect BGA joint thermal fatigue life prediction, characterized by, The method comprises the following steps:

9. A board level interconnect BGA joint thermal fatigue life prediction system, characterized by, The method comprises the following steps:

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