Display module, driving method thereof, and display device

Abstract

The present disclosure provides a display module and its driving method, and a display device, which belong to the field of display technology. The display module includes a plurality of pixels, a plurality of data lines, and a plurality of light-emitting control lines. In this method, data signals with different potentials can be provided to the plurality of data lines in the display stage and the reset stage, and a light-emitting control signal with a plurality of pulse periods can be provided to each light-emitting control line to drive the plurality of pixels to emit light. Because the switching points between each two adjacent pulse periods in the light-emitting control signal provided do not overlap with the reset stage, that is, they all avoid the reset stage, it is possible to avoid the potential jump of the data signal in the reset stage affecting the potential of the light-emitting control signal, thereby improving the display abnormality problem caused by signal delay, and ensuring a better display effect of the display module.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module, a driving method thereof, and a display device. Background Art

[0002] Organic light emitting diode (OLED) display modules are widely used in various display devices due to their advantages such as self-luminescence, wide viewing angle, fast response speed and high contrast.

[0003] Currently, OLED display modules typically include multiple pixels and multiple signal lines. The signal lines are electrically connected to the pixels and are used to provide signals to the pixels, driving them to emit light, allowing the OLED display module to display an image. For example, the signal lines typically include light-control signal lines and data lines, and there is a delay between the light-control signals provided by two adjacent light-control signal lines.

[0004] Due to signal delay, some rows of pixels in OLED display modules are prone to display anomalies. For example, high brightness at low grayscale levels can cause bright streaks to appear on the OLED display module, affecting the display quality. Summary of the Invention

[0005] Provided are a display module, a driving method thereof, and a display device, which can solve the problem of poor display effects of display modules in related technologies. The technical solution is as follows:

[0006] In one aspect, a method for driving a display module is provided, wherein the display module includes: a plurality of pixels, a plurality of data lines, and a plurality of light-emitting control lines; the method includes:

[0007] providing a first data signal to the plurality of data lines during a display phase of each frame scan;

[0008] In a reset phase between two adjacent frame scans, a second data signal is provided to the plurality of data lines, wherein the potential of the second data signal is different from the potential of the first data signal;

[0009] providing light-emitting control signals to the plurality of light-emitting control lines, wherein the light-emitting control signal provided to each light-emitting control line has a plurality of pulse periods, and a switching point between two adjacent pulse periods does not overlap with the reset phase;

[0010] The plurality of pixels are electrically connected to the plurality of data lines and the plurality of light-emitting control lines, respectively, and are configured to emit light based on the first data signal and the light-emitting control signal.

[0011] Optionally, the switching point between every two adjacent pulse periods is located within the display phase and does not overlap with the rising edge and the falling edge of the first data signal.

[0012] Optionally, the number of pulse periods of the light emitting control signal provided to each light emitting control line is the same, and the time interval between every two adjacent pulse periods is equal.

[0013] Optionally, the plurality of pixels are arranged in an array, the plurality of light-emitting control lines are electrically connected to a plurality of rows of pixels, and each light-emitting control line is electrically connected to a different row of pixels; and providing light-emitting control signals to the plurality of light-emitting control lines includes:

[0014] Determining at least two target row pixels based on the number of pulse cycles and the number of pixel rows electrically connected to each light emitting control line, wherein the at least two target row pixels include at least a first row of pixels;

[0015] In response to a light-emission control start signal, providing a light-emission control signal to each target light-emission control line electrically connected to the at least two target row pixels among the plurality of light-emission control lines, wherein a switching point between each two adjacent pulse periods in the provided light-emission control signal does not overlap with the reset phase;

[0016] For any two adjacent light control lines other than the target light control lines, a light control signal is provided to the next light control line based on the light control signal provided to the previous light control line along the direction from the first row of pixels to the last row of pixels.

[0017] Optionally, when a light-emitting control signal is provided to each target light-emitting control line, the corresponding light-emitting control start signal is the same.

[0018] Optionally, each light emitting control line is electrically connected to two adjacent rows of pixels; except for the first row of pixels, the number of pixels in the remaining target rows satisfies: m / n*M;

[0019] Wherein, M is the number of the plurality of rows of pixels, n is the number of pulse cycles, and m is an integer less than n.

[0020] Optionally, n is 3 or 16.

[0021] Optionally, in the display stage during each frame scan, in the luminescence control signal provided to each target luminescence control line in response to the luminescence control start signal, the switching point of the first pulse cycle is located within the display stage, and the switching point of the last pulse cycle is located within the display stage during the next frame scan.

[0022] On the other hand, a display module is provided, comprising: a plurality of pixels, a plurality of data lines, a plurality of light-emitting control lines, a source driving circuit, and a light-emitting control circuit;

[0023] The source driver circuit is electrically connected to the plurality of data lines and is configured to provide a first data signal to the plurality of data lines during a display phase during each frame scan, and to provide a second data signal to the plurality of data lines during a reset phase between each two adjacent frame scans, wherein a potential of the second data signal is different from a potential of the first data signal;

[0024] The light-emitting control circuit is electrically connected to the plurality of light-emitting control lines and is configured to provide light-emitting control signals to the plurality of light-emitting control lines, wherein the light-emitting control signal provided to each light-emitting control line has a plurality of pulse periods, and a switching point between each two adjacent pulse periods does not overlap with the reset phase;

[0025] The plurality of pixels are electrically connected to the plurality of data lines and the plurality of light emission control lines, respectively, and are configured to emit light based on the first data signal and the light emission control signal.

[0026] Optionally, the display module further includes: a light emitting control start line; the light emitting control circuit includes: a plurality of light emitting control sub-circuits;

[0027] The plurality of light-emitting control subcircuits are electrically connected to a plurality of target light-emitting control lines among the plurality of light-emitting control lines in a one-to-one correspondence, the plurality of target light-emitting control lines are electrically connected to at least two rows of target row pixels, the at least two rows of target row pixels are determined based on the number of pulse cycles and the number of pixel rows electrically connected to each light-emitting control line, and the target row pixels include at least a first row of pixels;

[0028] Each light-emitting control subcircuit is further electrically connected to the light-emitting control enable line and other light-emitting control lines between each two adjacent target light-emitting control lines. Each light-emitting control subcircuit is configured to provide a light-emitting control signal to a corresponding target light-emitting control line in response to a light-emitting control enable signal provided by the light-emitting control enable line, and to provide a light-emitting control signal to a subsequent light-emitting control line based on the light-emitting control signal provided to the previous light-emitting control line along a direction from a first row of pixels to a last row of pixels.

[0029] In which, in the light-emitting control signal provided by each light-emitting control subcircuit to the target light-emitting control line, the switching point between each two adjacent pulse periods does not overlap with the reset stage, so that in the light-emitting control signal provided to other light-emitting control lines except the target light-emitting control line, the switching point between each two adjacent pulse periods does not overlap with the reset stage.

[0030] Optionally, each light-emitting control subcircuit includes: a plurality of light-emitting control units cascaded in sequence, wherein the plurality of light-emitting control units are electrically connected to a target light-emitting control line and other light-emitting control lines between the target light-emitting control line and another adjacent target light-emitting control line in a one-to-one correspondence, and the light-emitting control unit electrically connected to the target light-emitting control line is also electrically connected to the light-emitting control start line;

[0031] Among them, the light-emitting control unit electrically connected to the target light-emitting control line is used to provide a light-emitting control signal to a corresponding target light-emitting control line in response to the light-emitting control start signal, and other light-emitting control units except the light-emitting control unit electrically connected to the target light-emitting control line are used to provide a light-emitting control signal to an electrically connected light-emitting control line based on the light-emitting control signal provided by the previous-level light-emitting control unit of the cascade.

[0032] Optionally, the display module includes: a light emitting control start line, and the multiple light emitting control sub-circuits all share the light emitting control start line;

[0033] Alternatively, the display module includes: multiple light-emitting control start lines, and the multiple light-emitting control sub-circuits are electrically connected to the multiple light-emitting control start lines in a one-to-one correspondence; and the light-emitting control start lines electrically connected to each light-emitting control sub-circuit provide the same light-emitting control start signal.

[0034] Optionally, each pixel includes: a pixel circuit and a light-emitting element, wherein the pixel circuit is electrically connected to the light-emitting control line, the data line, and the light-emitting element, respectively, and is also electrically connected to a gate line, a first power line, a reset signal line, and a reset power line, respectively, and the light-emitting element is also electrically connected to the second power line;

[0035] In which, the pixel circuit is used to transmit a drive signal to the light-emitting element in response to the gate drive signal provided by the gate line, the first power line provided by the first power line, the reset signal provided by the reset signal line, the reset power signal provided by the reset power line, the light-emitting control signal and the data signal; the light-emitting element is used to emit light based on the drive signal and the second power signal provided by the second power line.

[0036] Optionally, the pixel circuit includes: a data writing transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, a compensation transistor, a driving transistor and a storage capacitor;

[0037] The gate of the data writing transistor and the gate of the compensation transistor are both electrically connected to the gate line; the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the first node; the first electrode of the compensation transistor is electrically connected to the second node, and the second electrode of the compensation transistor is electrically connected to the third node;

[0038] The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the light-emitting control line; a first electrode of the first light-emitting control transistor is electrically connected to the first power line, and a second electrode of the first light-emitting control transistor is electrically connected to the first node; a first electrode of the second light-emitting control transistor is electrically connected to the third node, and a second electrode of the second light-emitting control transistor is electrically connected to the fourth node;

[0039] The gate of the first reset transistor and the gate of the second reset transistor are both electrically connected to the reset signal line; the first electrode of the first reset transistor and the first electrode of the second reset transistor are both electrically connected to the reset power line, the second electrode of the first reset transistor is electrically connected to the second node, and the second electrode of the second reset transistor is electrically connected to the fourth node;

[0040] The gate of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node;

[0041] One end of the storage capacitor is electrically connected to the second node, and the other end of the storage capacitor is electrically connected to the first power line;

[0042] A first electrode of the light emitting element is electrically connected to the fourth node, and a second electrode of the light emitting element is electrically connected to the second power line.

[0043] In another aspect, a display device is provided, comprising: a power supply component, and the display module as described in the above aspect;

[0044] The power supply component is electrically connected to the display module and is used to supply power to the display module.

[0045] In summary, the beneficial effects brought about by the technical solutions provided by the embodiments of the present disclosure may include at least:

[0046] A display module, a driving method thereof, and a display device are provided. The display module includes multiple pixels, multiple data lines, and multiple light-emitting control lines. In this method, data signals with different potentials can be provided to the multiple data lines during the display phase and the reset phase, and a light-emitting control signal with multiple pulse periods can be provided to each light-emitting control line to drive the multiple pixels to emit light. Because the switching points between each two adjacent pulse periods in the provided light-emitting control signal do not overlap with the reset phase, that is, they avoid the reset phase, the potential jump of the data signal during the reset phase can be prevented from affecting the potential of the light-emitting control signal. This can further improve display abnormalities caused by signal delays and ensure a better display effect of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 This is a flow chart of a method for driving a display module provided by an embodiment of the present disclosure;

[0049] Figure 2 is a structural diagram of a display module provided by an embodiment of the present disclosure;

[0050] Figure 3 is a timing diagram of a data signal provided by an embodiment of the present disclosure;

[0051] Figure 4 is a timing diagram of a light emitting control signal and a data signal provided by an embodiment of the present disclosure;

[0052] Figure 5 is a flow chart of a method for providing a light-emitting control signal provided by an embodiment of the present disclosure;

[0053] Figure 6 is a structural diagram of a light emitting control circuit provided by an embodiment of the present disclosure;

[0054] Figure 7 is a structural diagram of another display module provided by an embodiment of the present disclosure;

[0055] Figure 8 is a structural diagram of a light emitting control subcircuit provided by an embodiment of the present disclosure;

[0056] Figure 9 is a schematic structural diagram of a pixel provided by an embodiment of the present disclosure;

[0057] Figure 10 is a structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0058] Figure 11 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0060] Figure 1 This is a flowchart of a method for driving a display module provided by an embodiment of the present disclosure. Figure 2 This is a schematic diagram of the structure of a display module provided by an embodiment of the present disclosure. Figure 2 It can be seen that the display module described in the embodiment of the present disclosure includes: a plurality of pixels P1, a plurality of data lines Data and a plurality of light emitting control lines EM. Figure 1 It can be seen that for Figure 2 The driving method of the display module shown includes:

[0061] Step 101 : During a display phase of each frame scan, provide a first data signal to a plurality of data lines.

[0062] Optional, reference Figure 2 The display module may further include a source driver circuit O1. The plurality of pixels P1 may be arranged in an array, i.e., the plurality of pixels P1 may be divided into a plurality of rows and columns of pixels. The source driver circuit O1 may be electrically connected to the plurality of columns of pixels P1 via a plurality of data lines Data in a one-to-one correspondence. That is, the display module may include a plurality of data lines Data electrically connected to the plurality of columns of pixels P1 in a one-to-one correspondence.

[0063] In the embodiment of the present disclosure, the source driver circuit 01 can provide a first data signal of a required potential to multiple data lines Data according to the desired display image during the display phase of each frame scan, so as to drive multiple pixels P1 to emit light and achieve image refresh, that is, control the display module to display the image.

[0064] Step 102: During a reset phase between two adjacent frame scans, provide a second data signal to a plurality of data lines.

[0065] Optional, continue combining Figure 2 In the embodiment of the present disclosure, the source driving circuit 01 can still provide a second data signal to the plurality of data lines Data during the reset phase between each two adjacent frame scans to control the display module to stop refreshing the screen.

[0066] Furthermore, the potential of the second data signal can be different from the potential of the first data signal. For example, in the disclosed embodiment, the potential of the first data signal can be high, and the potential of the second data signal can be low, that is, the potential of the first data signal can be greater than the potential of the second data signal. For example, the potential of the first data signal can be greater than 0, and the potential of the second data signal can be equal to 0. For example, during the reset phase, the data line Data can be grounded to pull the potential of the data signal down to 0.

[0067] For example, taking the potential of the first data signal as a high potential and the potential of the second data signal as a low potential as an example, Figure 3 A timing diagram of a data signal is shown.

[0068] like Figure 3 As shown, when the display module displays the picture, it can include a display phase t1 during each frame scan and a reset phase t2 located between each two adjacent frame scans. In the display phase t1, a first data signal with a high potential can be provided to the multiple data lines Data to control the display module to refresh the display picture. The display phase t1 can also be called a display area. In the reset phase t2, a second data signal with a low potential can be provided to the multiple data lines Data to control the display module to stop refreshing. In this way, the reset phase t2 can also be called a blanking phase. Based on the arrangement of multiple pixel P1 arrays, it can be understood as the reset time when refreshing the picture from the first row to the last row.

[0069] Still reference Figure 3 As can be seen, each reset phase t2 can be divided into a front porch t21 and a back porch t22. The front porch t21 refers to the preparation time before the official refresh to the display phase t1, which can generally be 16 hours; the back porch t22 refers to the reset time after the refresh of the display phase t1 ends and before the preparation begins, which can generally be 20 hours. Accordingly, the reset phase t2 can also be called the porch area. Each frame scan actually includes the front porch t21 + display phase t1 + back porch t22, which are executed in sequence. Figure 3 Here, "H" refers to a unit for indicating time, and will not be described in detail in the following embodiments.

[0070] Step 103: providing light-emitting control signals to a plurality of light-emitting control lines.

[0071] Optional, continue to refer to Figure 2The display module may further include a light control circuit 02. The light control circuit 02 may be electrically connected to multiple rows of pixels P1 via multiple light control lines EM. That is, the display module may include multiple light control lines EM electrically connected to multiple rows of pixels P1 in a one-to-one correspondence. In the disclosed embodiment, the light control circuit 02 may provide light control signals to the multiple light control lines EM. During display stage t1, the multiple pixels P1 may emit light based on the received first data signal and the light control signals.

[0072] Furthermore, the light control signal provided by the light control circuit 02 to each light control line EM may have multiple pulse periods, i.e., multiple pulses. The number of pulse periods of the light control signal may determine the number of refreshes per frame scan. Within each pulse period, the potential of the light control signal provided by the light control circuit 02 to each light control line EM may be an effective potential, and between each two adjacent pulse periods, the potential of the light control signal provided by the light control circuit 02 to each light control line EM may be an inactive potential. Multiple pixels P1 may emit light based on the first data signal and the light control signal with an effective potential. Thus, the light control signal with an effective potential may also be referred to as an EM-ON signal, and the light control signal with an inactive potential may also be referred to as an EM-OFF signal. Furthermore, in the disclosed embodiment, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2, and the switching point may also be referred to as the potential transition point between the EM-ON signal and the EM-OFF signal, i.e., the on / off switching point of the EM signal.

[0073] For example, in Figure 3 Based on the timing of the data signal shown, taking the case where the light emitting control signal has three pulse periods t3-1, t3-2 and t3-3, and the effective potential is a high potential and the invalid potential is a low potential as an example, Figure 4 A timing diagram including light emission control signals is shown.

[0074] Combine Figure 3 and Figure 4 It can be seen that the switching points between adjacent pulse periods t3-1 and t3-2, as well as the switching points between adjacent pulse periods t3-2 and t3-3, do not overlap with reset phase t2, that is, they both avoid the Porch region. Furthermore, the EM ON signal provided by the light-emitting control circuit 02 can avoid the Porch region and coincide with display phase t1, which provides the first data signal, to ensure reliable lighting of pixel P1.

[0075] Optionally, pixel P1 may generally include a pixel circuit and a light-emitting element electrically connected to each other, and the pixel circuit is used to transmit a light-emitting drive signal (such as a drive current) to the light-emitting element based on a first data signal and a light-emitting control signal of an effective potential to drive the light-emitting element to emit light.

[0076] Currently, the switching point between each two adjacent pulse cycles in the provided light-emitting control signal is generally located at the reset phase t2. This results in overlap between the EM-ON signal and the Porch region. Based on this, test simulations have found that because the potential of the data signal provided to the data line Data jumps in the Porch region, the potential at the connection point between the pixel circuit and the light-emitting element rises, which in turn affects the brightness of the light-emitting element when it reaches the next EM-OFF state. This appears as bright horizontal stripes on the display, resulting in a significant difference in brightness. Furthermore, this is clearly visible in low grayscale and low brightness displays, adversely affecting image quality.

[0077] In the disclosed embodiment, by setting the switching point between each two adjacent pulse periods in the provided light-emitting control signal to avoid the Porch region, the on and off of the light-emitting control signal is not affected by the potential jump of the data signal within the Porch region. This ensures that during the period of normal provision of the first data signal, i.e., during display phase t1, an EM-ON signal with an effective potential is provided, reliably illuminating pixel P1. This prevents the brightness of the light-emitting element from being affected during the next EM-OFF phase, improves the bright streaks phenomenon in the display module, and thus avoids the occurrence of bright and dark differences, ensuring excellent display quality.

[0078] It should be noted that the embodiments of the present disclosure Figure 1 The execution order of the steps shown is not limited. That is, the source driving circuit 01 provides the data signal and the light emitting control circuit 02 provides the light emitting control signal. Figure 1 The execution order shown in the accompanying figure.

[0079] In summary, the embodiments of the present disclosure provide a method for driving a display module. The display module includes a plurality of pixels, a plurality of data lines, and a plurality of light-emitting control lines. In this method, data signals with different potentials can be provided to the plurality of data lines during the display stage and the reset stage, and a light-emitting control signal with a plurality of pulse periods can be provided to each light-emitting control line to drive the plurality of pixels to emit light. Because the switching points between each two adjacent pulse periods in the light-emitting control signal provided do not overlap with the reset stage, that is, they all avoid the reset stage, it is possible to avoid the potential jump of the data signal in the reset stage affecting the potential of the light-emitting control signal, thereby improving the display abnormality problem caused by signal delay, and ensuring a better display effect of the display module.

[0080] Optional, continue combining Figure 4As can be seen, in the disclosed embodiment, the switching points between each of the multiple pulse periods of the light-emitting control signal provided by the light-emitting control circuit 02 can all be located within display phase t1 and do not overlap with either the rising or falling edges of the first data signal. In other words, the switching points between each of the two adjacent pulse periods are all located within the display area, ensuring that the effective potential of the EM ON signal is reliably increased during the time period when the first data signal is normally provided, thereby driving the pixel P1 to reliably emit light, effectively improving the brightness difference that occurs during display of the display module, and ensuring high-quality display images from the display module.

[0081] Among them, combined Figure 3 and Figure 4 It can be seen that the rising edge of the first data signal may refer to the moment when the low-potential second data signal jumps to the high-potential first data signal, that is, the moment when the reset phase t2 enters the display phase t1 (that is, the display area switches to the porch area). The falling edge of the first data signal may refer to the moment when the high-potential first data signal jumps to the low-potential second data signal (that is, the porch area switches to the display area), that is, the moment when the display phase t1 enters the reset phase t2.

[0082] Optional, continue combining Figure 4 As can be seen, in the disclosed embodiment, the number of pulse periods of the light-emission control signal provided by the light-emission control circuit 02 to each light-emission control line EM can be the same, and the time interval between each two adjacent pulse periods can be equal. In other words, each frame scan performs the same number of refreshes, and each refresh duration can be the same, thus ensuring good display uniformity.

[0083] As described in the above embodiment, in the embodiment of the present disclosure, a plurality of pixels P1 can be arranged in an array, a plurality of light emitting control lines EM can be electrically connected to a plurality of rows of pixels P1, and each light emitting control line EM can be electrically connected to a different row of pixels P1. Figure 5 It can be seen that Figure 1 Step 103, i.e. providing a light-emitting control signal to a plurality of light-emitting control lines, may include:

[0084] Step 1031 : Determine at least two target row pixels based on the number of pulse cycles and the number of pixel rows electrically connected to each light emitting control line.

[0085] In the embodiment of the present disclosure, the light control signal provided by the light control circuit 02 to the light control line EM may be a delay signal. Figure 2Under the premise that each emission control line EM is electrically connected to two adjacent rows of pixels P1, the emission control signal provided to each emission control line EM will naturally be delayed by 2H, and the emission control signal provided to each emission control line EM is a one-to-two signal. Furthermore, the delay period and the pulse period can be the same. For example, assuming the pulse period is 3, and the display module includes a total of M rows of pixels P1, the emission control signal timing provided to the emission control lines EM electrically connected to the 1st row of pixels P1, the 1 / 3*Mth row of pixels P1, and the 2 / 3*Mth row of pixels P1 can be the same.

[0086] In this way, at least two target row pixels P1 can be determined based on the number of pulse cycles and the number of pixel rows electrically connected to each light-emitting control line EM. Furthermore, the at least two target row pixels P1 include at least the first row (i.e., row 1) of pixels. Alternatively, the determination can be made directly by the light-emitting control circuit 02, or by another circuit independent of the light-emitting control circuit and then sent to the light-emitting control circuit 02.

[0087] For example, if each emission control line EM is electrically connected to two adjacent rows of pixels P1, that is, the emission control signal is a one-to-two signal as described in the above embodiment, the number of target rows of pixels, excluding the first row of pixels, can satisfy the following equation: m / n*M. Here, M is the number of rows of pixels, n is the number of pulse cycles, and m can be an integer less than n.

[0088] For example, assuming that n is 3 as described in the above embodiment, that is, pulse=3, referred to as 3pulse, the determined target row pixels may include the 1st row pixel P1, the 1 / 3*Mth row pixel P1, and the 2 / 3*Mth row pixel P1. Assuming n is 16, that is, pulse = 16, called 16pulse, the determined target row pixels may include the 1st row pixel P1, the 1st / 16*M row pixel P1, the 2nd / 16*M row pixel P1, the 3rd / 16*M row pixel P1, the 4th / 16*M row pixel P1, the 5th / 16*M row pixel P1, the 6th / 16*M row pixel P1, the 7th / 16*M row pixel P1, the 8th / 16*M row pixel P1, the 9th / 16*M row pixel P1, the 10th / 16*M row pixel P1, the 11th / 16*M row pixel P1, the 12th / 16*M row pixel P1, the 13th / 16*M row pixel P1, the 14th / 16*M row pixel P1, and the 15th / 16*M row pixel P1.

[0089] Of course, in some other embodiments, the number of pulse periods may also be 4, 6, or 12, which may be referred to as 4 pulses, 6 pulses, or 12 pulses, respectively. This disclosure does not limit this.

[0090] Step 1032 : In response to the light emission control start signal, provide a light emission control signal to each target light emission control line electrically connected to at least two target row pixels among the plurality of light emission control lines.

[0091] Optional, reference Figure 6 The display module described in the embodiment of the present disclosure may further include: a light emitting control start line ESTV. The light emitting control circuit 02 may include: a plurality of light emitting control sub-circuits 021.

[0092] The multiple emission control sub-circuits 021 can be electrically connected to the multiple target emission control lines EM in a one-to-one correspondence. Accordingly, the number of emission control sub-circuits 021 can be the same as the number of target emission control lines EM. The multiple target emission control lines EM are electrically connected to at least two rows of target row pixels P1. Furthermore, each emission control sub-circuit 021 can also be electrically connected to the emission control enable line ESTV and other emission control lines EM between each two adjacent target emission control lines EM.

[0093] In the embodiment of the present disclosure, each light-emission control sub-circuit 021 may provide a light-emission control signal to a corresponding target light-emission control line EM in response to a light-emission control enable signal provided by the light-emission control enable line ESTV. Furthermore, in the light-emission control signal provided by the light-emission control sub-circuit 021 to the target light-emission control line EM, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2.

[0094] Optionally, when the light emitting control circuit 02 provides the light emitting control signal to each target light emitting control line EM, the corresponding light emitting control start signal may be the same, that is, the timing may be consistent.

[0095] Example, combined Figure 6 The display module described in the embodiment of the present disclosure may include: multiple light control enable lines ESTV, and multiple light control sub-circuits 021 may be electrically connected to the multiple light control enable lines ESTV in a one-to-one correspondence. Moreover, the light control enable lines ESTV electrically connected to each light control sub-circuit 021 may provide the same light control enable signal. Alternatively, the display module described in the embodiment of the present disclosure may include: only one light control enable line ESTV, and multiple light control sub-circuits 021 may share the same light control enable line ESTV, thereby receiving the same light control enable signal.

[0096] Step 1033: For any two adjacent light-emitting control lines other than the target light-emitting control lines, a light-emitting control signal is provided to the next light-emitting control line based on the light-emitting control signal provided to the previous light-emitting control line along the direction from the first row of pixels to the last row of pixels.

[0097] After the delay period, the timing of the light-emitting control signals provided to the target light-emitting control lines EM connected to each target row pixel P1 is the same. For each light-emitting control line EM connected to other rows of pixels P1 between every two adjacent rows of target row pixels P1, the light-emitting control signals provided to each light-emitting control line EM are delayed by 2H relative to the light-emitting control signal provided to one of the light-emitting control lines EM.

[0098] Therefore, on this basis, combined with Figure 2 In the embodiment of the present disclosure, for any two adjacent light-emitting control lines EM other than the target light-emitting control lines EM, each light-emitting control sub-circuit 021 can provide a light-emitting control signal to the next light-emitting control line EM based on the light-emitting control signal provided to the previous light-emitting control line EM along the direction from the first row of pixels P1 to the last row of pixels P1.

[0099] Because the switching points between each two adjacent pulse periods in the emission control signal provided by the emission control sub-circuit 021 to the target emission control line EM do not overlap with the reset phase t2, the emission control signal provided to the next emission control line EM based on the emission control signal provided to the previous emission control line EM, while maintaining a delay, can ensure that the switching points between each two adjacent pulse periods in the emission control signal provided to each emission control line EM do not overlap with the reset phase t2. In other words, the switching points between each two adjacent pulse periods in the emission control signal avoid the Porch region, thereby improving the brightness difference problem. Providing the emission control signal described in the above embodiment to each target emission control line EM based on the emission control start signal can also be referred to as resetting the emission control signal.

[0100] For example, reference Figure 6 , which is a light emitting control circuit shown as an example with the target row pixels being the 1st row pixel P1, the 1 / 3*Mth row pixel P1, and the 2 / 3*Mth row pixel P1. Based on this example, refer to Figure 6 As can be seen, the light control circuit 02 may include three light control sub-circuits 021, and accordingly, may include three light control enable lines ESTV, labeled ESTV1, ESTV2, and ESTV3. The three light control sub-circuits 021 are electrically connected to the three light control enable lines ESTV1, ESTV2, and ESTV3 in a one-to-one correspondence.

[0101] Furthermore, the light control sub-circuit 021 electrically connected to the light control enable line ESTV1 is also electrically connected to each of the light control lines EM electrically connected to the pixels in the first row (the target row of pixels) P1 through the pixels in the 1 / 3*M-1 row. Furthermore, the light control sub-circuit 021 can provide a light control signal to the light control line EM electrically connected to the pixels in the first row of pixels P1 based on the light control enable signal provided by the light control enable line ESTV1, and can provide a light control signal to the light control line EM electrically connected to the pixels in the first row of pixels P1 through the light control line EM electrically connected to the pixels in the 1 / 3*M-1 row of pixels based on the light control signal provided to the previous light control line EM. Furthermore, in the light control signal provided to the light control line EM electrically connected to the pixels in the first row of pixels P1, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2, thereby ensuring that the switching point between each two adjacent pulse periods in the light control signal provided to the light control lines EM electrically connected to the pixels in other rows of pixels also does not overlap with the reset phase t2.

[0102] Similarly, the light control sub-circuit 021 electrically connected to the light control enable line ESTV2 is also electrically connected to each of the light control lines EM electrically connected to the pixels P1 in the 1 / 3*M row (the target row pixels) to the pixels P1 in the 2 / 3*M-1 row. Furthermore, the light control sub-circuit 021 can provide a light control signal to the light control line EM electrically connected to the pixels P1 in the 1 / 3*M row based on the light control enable signal provided by the light control enable line ESTV2, and provide a light control signal to the light control line EM electrically connected to the pixels P1 in the 1 / 3*M row, starting from the light control line EM electrically connected to the pixels P1 in the 1 / 3*M row to the light control line EM electrically connected to the pixels P1 in the 2 / 3*M-1 row, based on the light control signal provided to the previous light control line EM. Furthermore, in the light-emitting control signal provided to the light-emitting control line EM electrically connected to the 1 / 3*M-th row of pixels P1, the switching point between each two adjacent pulse periods does not overlap with the reset stage t2, thereby ensuring that in the light-emitting control signal provided to the light-emitting control line EM electrically connected to the other rows of pixels, the switching point between each two adjacent pulse periods does not overlap with the reset stage t2.

[0103] The light control sub-circuit 021 electrically connected to the light control enable line ESTV3 is also electrically connected to each of the light control lines EM electrically connected to the pixels P1 in the 2 / 3*M row (the target row pixels) through the M-th row. Furthermore, the light control sub-circuit 021 can provide a light control signal to the light control line EM electrically connected to the pixels P1 in the 2 / 3*M row based on the light control enable signal provided by the light control enable line ESTV3, and can provide a light control signal to the light control line EM electrically connected to the pixels P1 in the 2 / 3*M row through the M-th row based on the light control signal provided to the previous light control line EM. Furthermore, in providing the light control signal to the light control line EM electrically connected to the pixels P1 in the 2 / 3*M row, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2, thereby ensuring that in providing the light control signal to the light control lines EM electrically connected to the pixels in other rows, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2.

[0104] exist Figure 6 Based on this, it can be seen that in the embodiment of the present disclosure, multiple rows of pixels P1 can be divided into multiple partitions along the pixel column direction, and each partition can include at least two rows of pixels P1. In addition, the number of partitions can be the same as the number of target light-emitting control lines EM, and the number of light-emitting control sub-circuits 021 can be the same as the number of partitions, and they correspond one to one. For example, Figure 6 The structure of a display module is shown as an example based on the premise of 3 pulses, that is, the target light-emitting control lines EM are connected to the first row of pixels P1, the 1 / 3*M rows of pixels P1, and the 2 / 3*M rows of pixels P1. Figure 6 The structure shown can be divided into three partitions: A1-1, A1-2, and A1-3. Partition A1-1 includes the first row of pixels P1, and pixels from the first row to the 1 / 3*M-1th row of pixels P1; partition A1-2 includes pixels from the 2 / 3*Mth row to the 2 / 3*M-1th row of pixels P1; and partition A1-3 includes pixels from the 2 / 3*Mth row to the Mth row of pixels P1. The same applies to other numbers of pulses and will not be further described here.

[0105] exist Figure 6 Based on the structure shown, Figure 7 An equivalent diagram of a display module is shown. Figure 7 It can be seen that the display module 00 can be divided into three partitions A1-1, A1-2 and A1-3. Moreover, each of the three partitions can be provided with a light-emitting control enable line, that is, a total of three light-emitting control enable lines ESTV1, ESTV2 and ESTV3 can be provided.

[0106] Optionally, in an embodiment of the present disclosure, during display phase t1 of each frame scan, the switching point of the first pulse cycle of the light control signal provided by the light control circuit 02 to each target light control line EM in response to the light control start signal can be located within display phase t1, and the switching point of the last pulse cycle can be located within display phase t1 of the next frame scan. That is, compared to the current solution, the timing of the EM ON signal can be shifted back as a whole to ensure that when the current frame refreshes the image, the first EM ON signal of the light control signal required is located within display phase t1 of the current frame, that is, within the time period when the first data signal is normally provided to illuminate the pixel P1. Of course, in some other embodiments, the timing of the EM ON signal can also be shifted forward as a whole, that is, when the current frame refreshes the image, the first EM ON signal of the light control signal required is located within display phase t1 of the previous frame.

[0107] In summary, the embodiments of the present disclosure provide a method for driving a display module. The display module includes a plurality of pixels, a plurality of data lines, and a plurality of light-emitting control lines. In this method, data signals with different potentials can be provided to the plurality of data lines during the display stage and the reset stage, and a light-emitting control signal with a plurality of pulse periods can be provided to each light-emitting control line to drive the plurality of pixels to emit light. Because the switching points between each two adjacent pulse periods in the light-emitting control signal provided do not overlap with the reset stage, that is, they all avoid the reset stage, it is possible to avoid the potential jump of the data signal in the reset stage affecting the potential of the light-emitting control signal, thereby improving the display abnormality problem caused by signal delay, and ensuring a better display effect of the display module.

[0108] The present disclosure provides a display module. Figure 2 It can be seen that the display module may include: a plurality of pixels P1, a plurality of data lines Data, a plurality of light-emitting control lines EM, a source driving circuit 01 and a light-emitting control circuit 02.

[0109] The source driver circuit 01 is electrically connected to the plurality of data lines Data. The source driver circuit 01 is configured to provide a first data signal to the plurality of data lines Data during a display phase t1 during each frame scan, and to provide a second data signal to the plurality of data lines Data during a reset phase t2 between each two adjacent frame scans. The potential of the provided second data signal may be different from the potential of the first data signal.

[0110] The light control circuit 02 is electrically connected to the plurality of light control lines EM. The light control circuit 02 is configured to provide light control signals to the plurality of light control lines EM. The light control signals provided to each light control line EM have multiple pulse periods, and the switching point between each two adjacent pulse periods does not overlap with the reset phase t2.

[0111] The plurality of pixels P1 are electrically connected to the plurality of data lines Data and the plurality of emission control lines EM, respectively, and are configured to emit light based on a first data signal and an emission control signal.

[0112] Optional, reference Figure 6 and Figure 7 The display module described in the embodiment of the present disclosure may further include: a light emitting control start line ESTV. The light emitting control circuit 02 may include: a plurality of light emitting control sub-circuits 021.

[0113] The plurality of emission control sub-circuits 021 can be electrically connected to a plurality of target emission control lines EM in a one-to-one correspondence among the plurality of emission control lines EM. The plurality of target emission control lines EM can be electrically connected to at least two rows of target row pixels P1. The at least two rows of target row pixels P1 can be determined based on the number of pulse cycles and the number of rows of pixels P1 electrically connected to each emission control line EM, and the target row pixels P1 can include at least a first row of pixels P1. Each emission control sub-circuit 021 can also be electrically connected to an emission control enable line ESTV and other emission control lines EM between each two adjacent target emission control lines EM.

[0114] In the embodiment of the present disclosure, each light-emitting control sub-circuit 021 can be configured to provide a light-emitting control signal to a corresponding target light-emitting control line EM in response to a light-emitting control enable signal provided by a light-emitting control enable line ESTV. Furthermore, based on the light-emitting control signal provided to the previous light-emitting control line EM, the light-emitting control signal can be provided to the next light-emitting control line EM in a direction from the first row of pixels P1 to the last row of pixels P1. Furthermore, in the light-emitting control signal provided by each light-emitting control sub-circuit 021 to the target light-emitting control line EM, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2, so that in the light-emitting control signal provided to the light-emitting control lines EM other than the target light-emitting control line EM, the switching point between each two adjacent pulse periods does not overlap with the reset phase t2 either.

[0115] exist Figure 6 Based on this, continue to refer to Figure 8 It can be seen that each light emitting control subcircuit 021 described in the embodiment of the present disclosure may include: a plurality of light emitting control units 0211 cascaded in sequence.

[0116] Multiple light-emitting control units 0211 can also be electrically connected to a target light-emitting control line EM, and other light-emitting control lines EM between a target light-emitting control line EM and another adjacent target light-emitting control line EM, and the light-emitting control unit 0211 electrically connected to the target light-emitting control line EM can also be electrically connected to the light-emitting control start line ESTV.

[0117] For example, reference Figure 8 The light-emitting control subcircuit 021 electrically connected to the first row of pixels P1 (target row of pixels) may include multiple cascaded light-emitting control units 0211. The first light-emitting control unit 0211 may be electrically connected to a target light-emitting control line EM (i.e., the first light-emitting control line EM) and the light-emitting control enable line ESTV1. The second light-emitting control unit 0211 may be electrically connected to the second light-emitting control line EM and the first light-emitting control unit 0211. The third light-emitting control unit 0211 may be electrically connected to the third light-emitting control line EM and the second light-emitting control unit 0211, and so on. The electrical connection method of the light-emitting control units 0211 included in the remaining light-emitting control subcircuits 021 is similar and will not be further described.

[0118] The light emitting control unit 0211 electrically connected to the target light emitting control line EM can be configured to provide a light emitting control signal to the corresponding target light emitting control line EM in response to a light emitting control start signal. Furthermore, light emitting control units 0211 other than the light emitting control unit 0211 electrically connected to the target light emitting control line EM can be configured to provide a light emitting control signal to the light emitting control line EM electrically connected thereto based on a light emitting control signal provided by a light emitting control unit 0211 in a previous stage of the cascade connection.

[0119] In addition, in combination with the above embodiments and Figure 8 As can be seen, in the disclosed embodiment, the display module may include multiple light-emission control enable lines ESTV, and multiple light-emission control sub-circuits 021 may be electrically connected to the multiple light-emission control enable lines ESTV in a one-to-one correspondence. Furthermore, the light-emission control enable lines ESTV electrically connected to each light-emission control sub-circuit 021 may provide the same light-emission control enable signal.

[0120] Alternatively, in some other embodiments, the display module may include only one light emitting control enabling line ESTV, and the plurality of light emitting control sub-circuits 021 may share the one light emitting control enabling line ESTV.

[0121] Optional, Figure 9 Schematic diagram of a pixel structure provided by an embodiment of the present disclosure. Figure 9 As shown, each pixel P1 may include: a pixel circuit P11 and a light emitting element L1.

[0122] Pixel circuit P11 can be electrically connected to the emission control line EM, the data line Data, and the light-emitting element L1, respectively. It can also be electrically connected to the gate line Gate, the first power line VDD, the reset signal line Reset, and the reset power line Vinit, respectively. The light-emitting element L1 can also be electrically connected to the second power line VSS. Optionally, the second power line VSS can be the ground terminal GND.

[0123] The pixel circuit P11 can be configured to transmit a driving signal (e.g., a driving current) to the light-emitting element L1 in response to a gate driving signal provided by the gate line Gate, a first power line VDD provided by the first power line VDD, a reset signal provided by the reset signal line Reset, a reset power signal provided by the reset power line Vinit, a light-emission control signal provided by the light-emission control line EM, and a data signal provided by the data line Data. The light-emitting element L1 can be configured to emit light based on the driving signal and a second power signal provided by the second power line VSS.

[0124] Optionally, in the embodiment of the present disclosure, the potential of the first power signal provided by the first power line VDD may be a high potential, and the potential of the second power signal provided by the second power line VSS may be a low potential.

[0125] Optional, Figure 10 Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. Figure 10 As shown, the pixel circuit P11 may include: a data writing transistor T1, a first light emission control transistor T2, a second light emission control transistor T3, a first reset transistor T4, a second reset transistor T5, a compensation transistor T6, a driving transistor T7 and a storage capacitor C1.

[0126] The gate of the data write transistor T1 and the gate of the compensation transistor T6 can both be electrically connected to the gate line Gate. The first electrode of the data write transistor T1 can be electrically connected to the data line Data, and the second electrode of the data write transistor T1 can be electrically connected to the first node N1. The first electrode of the compensation transistor T6 can be electrically connected to the second node N2, and the second electrode of the compensation transistor T6 can be electrically connected to the third node N3.

[0127] The gate of the first emission control transistor T2 and the gate of the second emission control transistor T3 may both be electrically connected to the emission control line EM. A first electrode of the first emission control transistor T2 may be electrically connected to the first power line VDD, and a second electrode of the first emission control transistor T2 may be electrically connected to the first node N1. A first electrode of the second emission control transistor T3 may be electrically connected to the third node N3, and a second electrode of the second emission control transistor T3 may be electrically connected to the fourth node N4.

[0128] The gate of the first reset transistor T4 and the gate of the second reset transistor T5 may both be electrically connected to the reset signal line Reset. The first electrode of the first reset transistor T4 and the first electrode of the second reset transistor T5 may both be electrically connected to the reset power supply line Vinit. The second electrode of the first reset transistor T4 may be electrically connected to the second node N2, and the second electrode of the second reset transistor T5 may be electrically connected to the fourth node N4.

[0129] A gate electrode of the driving transistor T7 may be electrically connected to the second node N2 , a first electrode of the driving transistor T7 may be electrically connected to the first node N1 , and a second electrode of the driving transistor T7 may be electrically connected to the third node N3 .

[0130] One end of the storage capacitor C1 may be electrically connected to the second node N2 , and the other end of the storage capacitor C1 may be electrically connected to the first power line VDD.

[0131] A first electrode of the light emitting element L1 may be electrically connected to the fourth node N4 , and a second electrode of the light emitting element L1 may be electrically connected to the second power line VSS.

[0132] Optional, combined Figure 10 The first electrode of the light emitting element L1 may be an anode. The second electrode of the light emitting element L1 may be a cathode. Of course, in some embodiments, the first electrode of the light emitting element L1 may also be a cathode, and correspondingly, the second electrode of the light emitting element L1 may be an anode.

[0133] Optionally, the transistors used in the embodiments of the present disclosure may all be field-effect transistors (FETs) or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Of the first and second electrodes of a transistor, one electrode may be referred to as a source electrode, and the other as a drain electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the gate electrode, the signal input end is designated as the first electrode, and the signal output end is designated as the second electrode. Furthermore, the transistors used in the embodiments of the present disclosure may include P-type transistors and / or N-type transistors. For P-type transistors, the effective potential can be low relative to the ineffective potential, meaning that a P-type transistor is turned on when the gate potential is low and turned off when the gate potential is high. For N-type transistors, the effective potential can be high relative to the ineffective potential, meaning that an N-type transistor is turned on when the gate potential is high and turned off when the gate potential is low. Furthermore, multiple signals in various embodiments of the present disclosure have corresponding effective potentials and ineffective potentials. The effective potential and ineffective potential merely indicate that the potential of the signal has two states and do not represent specific values. The embodiments of the present disclosure are described assuming that each transistor is an N-type transistor. Furthermore, the pixel circuit described in the embodiment of the present disclosure can be Figure 10 In addition to the 7T1C structure shown (ie, including 7 transistors and 1 capacitor), other structures are also possible.

[0134] refer to Figure 10 A coupling capacitor C_N1_data may be provided between the first node N1 and the data line Data, a coupling capacitor C_N1_vdd may be provided between the first node N1 and the first power line VDD, and a coupling capacitor Cgs may be provided between the gate and source of the driving transistor T7.

[0135] When the potential of the data signal provided by the data line Data changes (occurring in the Porch region), if the potential of the light-emission control signal also changes at this time, the potential of the first node N1 will gradually rise due to the influence of the coupling capacitors C_N1_data and C_N1_vdd. The larger the capacitance value, the more significant the potential increase. Furthermore, due to the coupling effect of the coupling capacitor Cgs, if the potential of the first node N1 rises, the potential of the second node N2 will also rise. Consequently, the potential of the second node N2 will leak to the third node N3. As the ratio of the potentials of the second node N2 to the first node N1 decreases, the potential of the third node N3 gradually rises, ultimately causing the potential of the fourth node N4 to also gradually rise. In other words, the current value at the fourth node N4 will increase due to the overlap of the pulse cycle transition point of the light-emission control signal and the Porch region. The larger the capacitance value of the coupling capacitor, the greater the current increase. This, in turn, affects the brightness of the light-emitting element L1 during the next EM OFF signal, appearing as bright horizontal stripes. Furthermore, as described in the above embodiment, the location of the bright horizontal stripes is related to the pulse period. For a 3-pulse, the locations of the bright horizontal stripes can generally be the 1st row, 1 / 3*Mth row, and 2 / 3*Mth row. The same applies to other pulses and will not be repeated here.

[0136] In the disclosed embodiment, by setting the switching point between every two adjacent pulse periods of the light-emitting control signal to avoid the Porch region where the data signal potential jumps, the potential of the first node N1 can be prevented from rising, thereby preventing an increase in the current value transmitted by the pixel circuit P11 to the fourth node N4 (i.e., the anode of the light-emitting element L1). Furthermore, an abnormal increase in the brightness of the light-emitting element L1 is avoided, and the bright horizontal stripe problem is improved.

[0137] In summary, the embodiments of the present disclosure provide a display module. The display module includes multiple pixels, multiple data lines, multiple light-emitting control lines, a light-emitting control circuit, and a source driving circuit. The source driving circuit can provide data signals of different potentials to the multiple data lines in the display stage and the reset stage, and the light-emitting control circuit can provide a light-emitting control signal with multiple pulse periods to each light-emitting control line to drive multiple pixels to emit light. Because the switching points between each two adjacent pulse periods in the light-emitting control signal provided by the light-emitting control circuit do not overlap with the reset stage, that is, they all avoid the reset stage, it is possible to avoid the potential jump of the data signal in the reset stage affecting the potential of the light-emitting control signal, thereby improving the display abnormality problem caused by signal delay, and ensuring a better display effect of the display module.

[0138] Figure 11 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 11As shown, the display device includes: a power supply component J1, and a display module 00 as shown in the above drawings.

[0139] The power supply component J1 can be electrically connected to the display module 00 and used to supply power to the display module 00 .

[0140] Optionally, the display device described in the embodiments of the present disclosure may be any product or component with a display function, such as an organic light-emitting diode (OLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0141] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0142] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0143] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0144] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0145] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0146] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0147] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for driving a display module, characterized in that: The display module includes: a plurality of pixels, a plurality of data lines and a plurality of light-emitting control lines; the method includes: providing a first data signal to the plurality of data lines during a display phase of each frame scan; In a reset phase between two adjacent frame scans, a second data signal is provided to the plurality of data lines, wherein the potential of the second data signal is different from the potential of the first data signal; providing light-emitting control signals to the plurality of light-emitting control lines, wherein the light-emitting control signal provided to each light-emitting control line has a plurality of pulse periods, and a switching point between two adjacent pulse periods does not overlap with the reset phase; The plurality of pixels are electrically connected to the plurality of data lines and the plurality of light-emitting control lines, respectively, and are configured to emit light based on the first data signal and the light-emitting control signal; The plurality of pixels are arranged in an array, the plurality of light-emitting control lines are electrically connected to a plurality of rows of pixels, and each light-emitting control line is electrically connected to a different row of pixels; and providing light-emitting control signals to the plurality of light-emitting control lines includes: Determining at least two target row pixels based on the number of pulse cycles and the number of pixel rows electrically connected to each light emitting control line, wherein the at least two target row pixels include at least a first row of pixels; In response to a light-emission control start signal, providing a light-emission control signal to each target light-emission control line electrically connected to the at least two target row pixels among the plurality of light-emission control lines, wherein a switching point between each two adjacent pulse periods in the provided light-emission control signal does not overlap with the reset phase; For any two adjacent light control lines other than the target light control lines, a light control signal is provided to the next light control line based on the light control signal provided to the previous light control line along the direction from the first row of pixels to the last row of pixels.

2. The method according to claim 1, characterized in that The switching point between every two adjacent pulse periods is located within the display phase and does not overlap with the rising edge and the falling edge of the first data signal.

3. The method according to claim 1, characterized in that The number of pulse periods of the light emitting control signal provided to each light emitting control line is the same, and the time interval between every two adjacent pulse periods is equal.

4. The method according to any one of claims 1 to 3, characterized in that: When the light emission control signal is provided to each target light emission control line, the corresponding light emission control start signal is the same.

5. The method according to any one of claims 1 to 3, characterized in that: Each light-emitting control line electrically connects two adjacent rows of pixels; except for the first row of pixels, the number of pixels in the remaining target rows satisfies: m / n*M; Wherein, M is the number of the plurality of rows of pixels, n is the number of pulse cycles, and m is an integer less than n.

6. The method according to claim 5, characterized in that The n is 3 or 16.

7. The method according to claim 4, characterized in that In the display stage during each frame scan, in the luminescence control signal provided to each target luminescence control line in response to the luminescence control start signal, the switching point of the first pulse cycle is located within the display stage, and the switching point of the last pulse cycle is located within the display stage during the next frame scan.

8. A display module, characterized in that: The display module includes: a plurality of pixels, a plurality of data lines, a plurality of light-emitting control lines, a source driving circuit and a light-emitting control circuit; The source driver circuit is electrically connected to the plurality of data lines and is configured to provide a first data signal to the plurality of data lines during a display phase during each frame scan, and to provide a second data signal to the plurality of data lines during a reset phase between each two adjacent frame scans, wherein a potential of the second data signal is different from a potential of the first data signal; The light-emitting control circuit is electrically connected to the plurality of light-emitting control lines and is configured to provide light-emitting control signals to the plurality of light-emitting control lines, wherein the light-emitting control signal provided to each light-emitting control line has a plurality of pulse periods, and a switching point between each two adjacent pulse periods does not overlap with the reset phase; The plurality of pixels are electrically connected to the plurality of data lines and the plurality of light emitting control lines, respectively, and are configured to emit light based on the first data signal and the light emitting control signal; The display module further includes: a light emitting control start line; the light emitting control circuit includes: a plurality of light emitting control sub-circuits; The plurality of light-emitting control subcircuits are electrically connected to a plurality of target light-emitting control lines among the plurality of light-emitting control lines in a one-to-one correspondence, the plurality of target light-emitting control lines are electrically connected to at least two rows of target row pixels, the at least two rows of target row pixels are determined based on the number of pulse cycles and the number of pixel rows electrically connected to each light-emitting control line, and the target row pixels include at least a first row of pixels; Each light-emitting control subcircuit is further electrically connected to the light-emitting control enable line and other light-emitting control lines between each two adjacent target light-emitting control lines. Each light-emitting control subcircuit is configured to provide a light-emitting control signal to a corresponding target light-emitting control line in response to a light-emitting control enable signal provided by the light-emitting control enable line, and to provide a light-emitting control signal to a subsequent light-emitting control line based on the light-emitting control signal provided to the previous light-emitting control line along a direction from a first row of pixels to a last row of pixels. In which, in the light-emitting control signal provided by each light-emitting control subcircuit to the target light-emitting control line, the switching point between each two adjacent pulse periods does not overlap with the reset stage, so that in the light-emitting control signal provided to other light-emitting control lines except the target light-emitting control line, the switching point between each two adjacent pulse periods does not overlap with the reset stage.

9. The display module according to claim 8, wherein: Each light-emitting control subcircuit includes: a plurality of light-emitting control units connected in cascade sequence, wherein the plurality of light-emitting control units are electrically connected to a target light-emitting control line and other light-emitting control lines between the target light-emitting control line and another adjacent target light-emitting control line in a one-to-one correspondence, and the light-emitting control unit electrically connected to the target light-emitting control line is also electrically connected to the light-emitting control start line; Among them, the light-emitting control unit electrically connected to the target light-emitting control line is used to provide a light-emitting control signal to a corresponding target light-emitting control line in response to the light-emitting control start signal, and other light-emitting control units except the light-emitting control unit electrically connected to the target light-emitting control line are used to provide a light-emitting control signal to an electrically connected light-emitting control line based on the light-emitting control signal provided by the previous-level light-emitting control unit of the cascade.

10. The display module according to claim 9, wherein: The display module includes: a light-emitting control start line, and the multiple light-emitting control sub-circuits all share the light-emitting control start line; Alternatively, the display module includes: multiple light-emitting control start lines, and the multiple light-emitting control sub-circuits are electrically connected to the multiple light-emitting control start lines in a one-to-one correspondence; and the light-emitting control start lines electrically connected to each light-emitting control sub-circuit provide the same light-emitting control start signal.

11. The display module according to any one of claims 8 to 10, characterized in that: Each pixel includes: a pixel circuit and a light-emitting element, wherein the pixel circuit is electrically connected to the light-emitting control line, the data line and the light-emitting element respectively, and is also electrically connected to the gate line, the first power line, the reset signal line and the reset power line respectively, and the light-emitting element is also electrically connected to the second power line; In which, the pixel circuit is used to transmit a drive signal to the light-emitting element in response to the gate drive signal provided by the gate line, the first power line provided by the first power line, the reset signal provided by the reset signal line, the reset power signal provided by the reset power line, the light-emitting control signal and the data signal; the light-emitting element is used to emit light based on the drive signal and the second power signal provided by the second power line.

12. The display module according to claim 11, wherein: The pixel circuit includes: a data writing transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, a second reset transistor, a compensation transistor, a driving transistor and a storage capacitor; The gate of the data writing transistor and the gate of the compensation transistor are both electrically connected to the gate line; the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the first node; the first electrode of the compensation transistor is electrically connected to the second node, and the second electrode of the compensation transistor is electrically connected to the third node; The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the light-emitting control line; a first electrode of the first light-emitting control transistor is electrically connected to the first power line, and a second electrode of the first light-emitting control transistor is electrically connected to the first node; a first electrode of the second light-emitting control transistor is electrically connected to the third node, and a second electrode of the second light-emitting control transistor is electrically connected to the fourth node; The gate of the first reset transistor and the gate of the second reset transistor are both electrically connected to the reset signal line; the first electrode of the first reset transistor and the first electrode of the second reset transistor are both electrically connected to the reset power line, the second electrode of the first reset transistor is electrically connected to the second node, and the second electrode of the second reset transistor is electrically connected to the fourth node; The gate of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node; One end of the storage capacitor is electrically connected to the second node, and the other end of the storage capacitor is electrically connected to the first power line; A first electrode of the light emitting element is electrically connected to the fourth node, and a second electrode of the light emitting element is electrically connected to the second power line.

13. A display device, characterized in that: The display device comprises: a power supply component, and a display module according to any one of claims 8 to 12; The power supply component is electrically connected to the display module and is used to supply power to the display module.

Images