Flash memory chip and programming and testing method thereof

Abstract

The application discloses a flash memory chip and a programming method and a testing method thereof. The flash memory chip comprises a controller and a flash memory array electrically connected with the controller, and a plurality of flash memory unit arrays are arranged in the flash memory array. The flash memory chip further comprises a plurality of control gate lines, each of which is connected with the first end of a row of flash memory units; a plurality of erase gate lines, each of which is connected with the second end of a column of flash memory units; and a plurality of selection gate lines, each of which is connected with the third end of a row of flash memory units. The controller is used for providing a selection voltage to the i-th row of flash memory units through the selection gate line, and providing a selected voltage to the j-th column of flash memory units through the erase gate line to select the to-be-programmed flash memory unit located at the i-th row and the j-th column, and providing a preset voltage to the p-th row of flash memory units through the control gate line, wherein i is greater than or equal to 1, j is greater than or equal to 1, and p is greater than or equal to 1, and p is not equal to i. The technical scheme of the embodiment of the application can reduce the interference to the programmed flash memory unit, and improve the programming data precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flash memory, in particular to a flash memory chip and a programming method and a testing method thereof. BACKGROUND

[0002] Flash memory is a kind of non-volatile memory, which will not lose data when power off, and is widely used.

[0003] Figure 1 is a structure diagram of a flash memory array in the prior art, as shown in Figure 1 The flash memory array contains a plurality of flash memory units 10, and usually two rows of flash memory units 10 share an erase gate line EG, but two rows of flash memory units share an erase gate line EG, and when the selected voltage is written by using the erase gate line, two rows of flash memory units 10 are selected, and a certain flash memory unit 10 cannot be selected alone.

[0004] In order to accurately select a certain flash memory unit, a column of flash memory units shares an erase gate line; however, when the selected flash memory unit is programmed, the erase gate voltage of the flash memory unit in the selected column is large; thus, when programming, there is a certain interference to the already programmed flash memory unit in the selected column and the unselected row, which affects the programming data accuracy. SUMMARY

[0005] The present application provides a flash memory chip and a programming method and a testing method thereof, so as to reduce the interference to the already programmed flash memory unit and improve the programming data accuracy.

[0006] According to an aspect of the present application, a flash memory chip is provided, which comprises a controller and a flash memory array electrically connected with the controller, wherein a plurality of flash memory unit arrays are arranged in the flash memory array;

[0007] The flash memory chip further comprises a plurality of control gate lines, the control gate lines extend along a first direction, the first direction is a row direction of the flash memory unit array arrangement, and each control gate line is connected with a first end of a row of flash memory units;

[0008] a plurality of erase gate lines, the erase gate lines extend along a second direction, the second direction is a column direction of the flash memory unit array arrangement, and each erase gate line is connected with a second end of a column of flash memory units;

[0009] a plurality of selection gate lines, the plurality of selection gate lines extend along the first direction, and each selection gate line is connected with a third end of a row of flash memory units;

[0010] The controller is configured to provide a selection voltage to the flash memory cells in the ith row through the selection gate line, and to provide a selection voltage to the flash memory cells in the jth column through the erase gate line when the flash memory cell at the ith row and the jth column is selected to be programmed, and to provide a preset voltage to the flash memory cells in the pth row through the control gate line, wherein i≥1, j≥1, p≥1, and p≠i.

[0011] Optionally, the flash memory chip further comprises a plurality of drain lines and a plurality of source lines,

[0012] The plurality of source lines extend along the first direction, and each of the source lines is connected to the fourth end of at least one row of the flash memory cells.

[0013] The plurality of drain lines extend along the second direction, and each of the drain lines is electrically connected to the fifth end of one column of the flash memory cells.

[0014] Alternatively, the plurality of drain lines extend along the first direction, and each of the drain lines is electrically connected to the fifth end of one row of the flash memory cells.

[0015] Optionally, the flash memory cell comprises a first transistor and a second transistor.

[0016] The gate of the first transistor is the third end of the flash memory cell, and the drain of the first transistor is the fifth end of the flash memory cell.

[0017] The control gate of the second transistor is the first end of the flash memory cell, the drain of the second transistor is electrically connected to the source of the first transistor, the erase gate of the second transistor is the second end of the flash memory cell, and the source of the second transistor is the fourth end of the flash memory cell; the second transistor further comprises a floating gate.

[0018] Optionally, each two adjacent rows of the flash memory cells form a flash memory group, and each of the flash memory groups is connected to one of the source lines, and the source line is arranged between the two rows of flash memory cells of the flash memory group.

[0019] In each of the flash memory groups, in the two flash memory cells in the same column, the second transistor is arranged close to the source line, and the first transistor is arranged on the side of the source line away from the second transistor.

[0020] Optionally, the flash memory chip further comprises a programming circuit.

[0021] The controller is electrically connected to the flash memory array through the programming circuit.

[0022] According to another aspect of the present application, a programming method of a flash memory chip is provided, which is used for programming the flash memory chip according to any of the embodiments of the present application, and the programming method comprises:

[0023] When selecting a flash memory cell at the i-th row and the j-th column by providing a selection voltage to the flash memory cells at the i-th row through the selection gate line and providing a selection voltage to the flash memory cells at the j-th column through the erase gate line, a preset voltage is provided to the flash memory cells at the p-th row through the control gate line; wherein i≥1, j≥1, p≥1, and p is not equal to i.

[0024] According to another aspect of the present application, a testing method of a flash memory chip is provided for testing the flash memory chip according to any of the embodiments of the present application, the testing method comprising:

[0025] writing an erase voltage to the flash memory cell to be erased through the erase gate line;

[0026] programming a flash memory cell to be programmed by providing a selection voltage to the flash memory cells at the i-th row through the selection gate line and providing a selection voltage to the flash memory cells at the j-th column through the erase gate line, wherein i≥1, j≥1;

[0027] writing a preset voltage to the first to-be-tested cell through the control gate line, and determining that the flash memory chip is qualified when the parameter information of the first to-be-tested cell meets the first preset condition; wherein p≥1, and p is not equal to i, and the first to-be-tested cell is any of the flash memory cells at the p-th row and the j-th column.

[0028] Optionally, writing a preset voltage to the first to-be-tested cell through the control gate line when the parameter information of the first to-be-tested cell meets the first preset condition comprises:

[0029] acquiring a first initial current of the first to-be-tested cell, and writing a preset voltage to the first to-be-tested cell through the control gate line when the first initial current is less than a first preset current;

[0030] acquiring a first test current of the first to-be-tested cell, and determining that the parameter information of the first to-be-tested cell meets the first preset condition when the difference between the first test current and a first initial current of the first to-be-tested cell is within a first preset range.

[0031] Optionally, before providing a selection voltage to the flash memory cells at the i-th row through the selection gate line, the method further comprises:

[0032] acquiring a second initial current of the second to-be-tested cell, and writing a preset voltage to the second to-be-tested cell through the control gate line when the second initial current is greater than a second preset current; wherein the second to-be-tested cell is any of the flash memory cells at the p-th row and the k-th column, and k≥1, and k is not equal to j;

[0033] Collecting a second test current of the second to-be-tested unit, when a difference between the second test current and the second initial current is within a second difference range, determining that the second to-be-tested unit is normal.

[0034] Optionally, the parameter information of the first to-be-tested unit satisfies a first preset condition, and the parameter information comprises:

[0035] A difference between the erase gate voltage and the floating gate voltage of the first to-be-tested unit is less than a tunneling threshold voltage.

[0036] The technical scheme of the embodiment of the application, the flash memory unit comprises a floating gate transistor; when the controller selects the voltage provided by the select gate line to the i-th row of flash memory units and selects the voltage provided by the erase gate line to the j-th column of flash memory units to select the to-be-programmed flash memory unit located in the i-th row and the j-th column, the controller provides a preset voltage to the p-th row of flash memory units through the control gate line; the voltage of the first end of the p-th row of flash memory units is coupled to the floating gate of the p-th row of flash memory units, that is, the floating gate voltage of the p-th row of flash memory units is increased, so that the voltage difference between the second end and the floating gate of the p-th row of flash memory units is reduced, and the tunneling of the p-th row of flash memory units due to the writing of the selected voltage by the erase gate line is avoided; thus, the programming voltage written into the p-th row of flash memory units can be maintained, the interference on the programmed flash memory units is reduced, and the programming data accuracy is improved. The technical scheme of the embodiment of the application solves the problem that when the selected voltage is written into the to-be-programmed flash memory unit through the erase gate line, great interference is generated on the programmed flash memory units in other rows, the tunneling of the p-th row of flash memory units due to the writing of the selected voltage by the erase gate line is avoided, the interference on the programmed flash memory units is reduced, and the programming data accuracy is improved.

[0037] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0039] Figure 1 is a structural schematic diagram of a flash memory array in the prior art;

[0040] Figure 2 is a structural schematic diagram of a flash memory chip provided by the embodiment of the application;

[0041] Figure 3is a structure schematic diagram of another flash memory chip provided by the embodiment of the present application;

[0042] Figure 4 is Figure 3 is a structure schematic diagram of the flash memory unit in the pth row and jth column;

[0043] Figure 5 is Figure 3 is a structure schematic diagram of the flash memory unit in the pth row and kth column;

[0044] Figure 6 is a flow chart of a programming method of a flash memory chip provided by the embodiment of the present application;

[0045] Figure 7 is a flow chart of a test method of a flash memory chip provided by the embodiment of the present application;

[0046] Figure 8 is a flow chart of another test method of a flash memory chip provided by the embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without making creative efforts should belong to the scope of protection of the present application.

[0048] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the term "comprising" and any variation thereof is intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0049] Figure 2 is a structure schematic diagram of a flash memory chip provided by the embodiment of the present application, referring to Figure 2The flash memory chip comprises a controller 101 and a flash memory array 102 electrically connected with the controller 101, wherein a plurality of flash memory units 1021 are arranged in the flash memory array 102; the flash memory chip further comprises a plurality of control gate lines CG', the control gate lines CG' extend along a first direction X, the first direction X is a row direction of the arrangement of the flash memory units 1021, and each control gate line CG' is connected with the first ends of a row of flash memory units 1021; a plurality of erase gate lines EG', the erase gate lines EG' extend along a second direction Y, the second direction Y is a column direction of the arrangement of the flash memory units 1021, and each erase gate line EG' is connected with the second ends of a column of flash memory units 1021; a plurality of select gate lines WL', the plurality of select gate lines WL' extend along the first direction X, and each select gate line WL' is connected with the third ends of a row of flash memory units 1021; the controller 101 is configured to provide a selection voltage to the i-th row of flash memory units 1021 through the select gate line WL' and provide a selected voltage to the j-th column of flash memory units 1021 through the erase gate line EG' to select the flash memory unit to be programmed located at the i-th row and the j-th column, and provide a preset voltage to the p-th row of flash memory units through the control gate line CG', wherein i≥1, j≥1, p≥1, and p is not equal to i.

[0050] The flash memory chip is, for example, a memory-computing integrated chip, that is, the flash memory chip can not only store but also compute. The controller 101 can control the working mode of the flash memory array 102, including a computing mode and a storage mode. When in the computing mode, the controller 101 programs the flash memory array 102, and the computation can be realized after the input of the data to be processed into the flash memory array 102. When in the storage mode, the data to be stored is input into the flash memory array 102, and the controller 101 programs the flash memory array 102 to store the data. The flash memory unit 1021 comprises, for example, a floating gate transistor, the floating gate of the flash memory unit 1021 can capture electrons and store, and even after power failure, the electrons will not flow away, that is, the data will not be lost.

[0051] Specifically, the controller 101 can write an erase voltage to the flash memory unit 1021 through the erase gate line EG' to realize the erase operation, and each erase gate line EG' can erase a column of flash memory units 1021. When the flash memory unit to be programmed located at the i-th row and the j-th column needs to be programmed, the selection voltage is written to the i-th row of flash memory units 1021 through the select gate line WL', and the selected voltage is provided to the j-th column of flash memory units 1021 through the erase gate line EG' to select the flash memory unit to be programmed located at the i-th row and the j-th column; the controller 101 writes the programming voltage to the selected flash memory unit to be programmed to realize the programming of the flash memory unit to be programmed.

[0052] And when the to-be-programmed flash memory cell in the i-th row and the j-th column is selected, the voltage of the second end of the flash memory cell in the j-th column is all the selected voltage. By controlling the gate line CG' to provide a preset voltage to the flash memory cell in the p-th row, p is not equal to i, that is, the first end of the flash memory cell 1021 in the remaining rows except the i-th row is written with the preset voltage; the voltage of the first end of the flash memory cell 1021 in the p-th row is coupled to the floating gate of the flash memory cell 1021 in the p-th row, that is, the floating gate voltage of the flash memory cell 1021 in the p-th row is increased, so as to reduce the voltage difference between the second end and the floating gate of the flash memory cell 1021 in the p-th row, and the tunneling of the flash memory cell 1021 in the p-th row due to the writing of the selected voltage by the erase gate line EG' can be avoided; thus, the programming voltage written to the flash memory cell 1021 in the p-th row can be maintained, the interference to the programmed flash memory cell is reduced, and the programming data accuracy is improved.

[0053] The technical scheme of the embodiment, the flash memory cell comprises a floating gate transistor; the controller provides a selection voltage to the flash memory cell in the i-th row through a selection gate line, and provides a selected voltage to the flash memory cell in the j-th column through an erase gate line; when the to-be-programmed flash memory cell in the i-th row and the j-th column is selected, a preset voltage is provided to the flash memory cell in the p-th row through a control gate line; the voltage of the first end of the flash memory cell in the p-th row is coupled to the floating gate of the flash memory cell in the p-th row, that is, the floating gate voltage of the flash memory cell in the p-th row is increased, so as to reduce the voltage difference between the second end and the floating gate of the flash memory cell in the p-th row, and the tunneling of the flash memory cell in the p-th row due to the writing of the selected voltage by the erase gate line can be avoided; thus, the programming voltage written to the flash memory cell in the p-th row can be maintained, the interference to the programmed flash memory cell is reduced, and the programming data accuracy is improved. The technical scheme of the embodiment solves the problem that when the selected voltage is written to the to-be-programmed flash memory cell through the erase gate line, great interference is generated to the programmed flash memory cell in other rows, the tunneling of the flash memory cell in the p-th row due to the writing of the selected voltage by the erase gate line can be avoided, the interference to the programmed flash memory cell is reduced, and the programming data accuracy is improved.

[0054] Figure 3 is another structure diagram of a flash memory chip provided by the embodiment of the present application, and Figure 3 The flash memory chip further comprises a plurality of drain lines BL' and a plurality of source lines SL'. The plurality of source lines SL' extend along a first direction X, and each source line SL' is connected to the fourth end of at least one row of flash memory cells 1021. The plurality of drain lines BL' extend along a second direction Y, and each drain line BL' is electrically connected to the fifth end of a column of flash memory cells 1021. Alternatively, the plurality of drain lines BL' extend along the first direction X, and each drain line BL' is electrically connected to the fifth end of a row of flash memory cells 1021.

[0055] Specifically, the controller 101 can apply a programming voltage to the fourth end of the flash memory cell 1021 through the source line SL', and the fifth end of the flash memory cell 1021 is grounded or at a low voltage through the drain line BL', the programming voltage accelerates the channel electrons to a high speed, and injects electrons into the flash memory cell 1021 by using the hot electron injection effect, so as to realize programming of the flash memory cell 1021. The plurality of drain lines BL' can extend along the first direction X, or extend along the second direction Y. When the plurality of drain lines BL' extend along the second direction Y, a column of flash memory cells 1021 can share one drain line BL'; when the plurality of drain lines BL' extend along the first direction X, a row of flash memory cells 1021 can share one drain line BL'. It should be noted that, Figure 3 The case where the plurality of drain lines BL' extend along the second direction Y is shown in the figure, but the disclosure is not limited thereto.

[0056] Optionally, referring to Figure 3 , the flash memory cell comprises a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is the third end of the flash memory cell 1021, and the drain of the first transistor M1 is the fifth end of the flash memory cell 1021; the control gate of the second transistor M2 is the first end of the flash memory cell 1021, the drain of the second transistor M2 is electrically connected with the source of the first transistor M1, the erase gate of the second transistor M2 is the second end of the flash memory cell 1021, and the source of the second transistor M2 is the fourth end of the flash memory cell 1021; the second transistor M2 further comprises a floating gate FG.

[0057] Specifically, the gate of the first transistor M1 is the third terminal of the flash memory cell 1021, i.e., the select gate WL of the flash memory cell; the drain of the first transistor M1 is the fifth terminal of the flash memory cell 1021, i.e., the drain BL of the flash memory cell 1021; the control gate of the second transistor M2 is the first terminal of the flash memory cell 1021, i.e., the control gate CG of the flash memory cell 1021, and the erase gate of the second transistor M2 is the second terminal of the flash memory cell 1021, i.e., the erase gate EG of the flash memory cell 1021; the source of the second transistor M2 is the fourth terminal of the flash memory cell 1021, i.e., the source SL of the flash memory cell. When the flash memory cell to be programmed in the ith row and the jth column is selected, the voltage of the erase gate EG of the flash memory cell in the jth column is the selected voltage. A preset voltage is provided to the flash memory cell in the pth row through the control gate line CG', p is not equal to i, i.e., the preset voltage is written to the control gate CG of the flash memory cell 1021 in the remaining rows except the ith row; the voltage of the control gate CG of the flash memory cell 1021 in the pth row is coupled to the floating gate FG of the flash memory cell 1021 in the pth row, i.e., the floating gate voltage of the flash memory cell 1021 in the pth row is increased, so as to reduce the voltage difference between the erase gate EG and the floating gate FG of the flash memory cell 1021 in the pth row, thereby avoiding the tunneling of the flash memory cell 1021 in the pth row due to the writing of the selected voltage by the erase gate line EG'; thus, the programming voltage written to the flash memory cell 1021 in the pth row can be maintained, the interference to the programmed flash memory cell is reduced, and the programming data accuracy is improved.

[0058] Figure 4 is Figure 3 the structure of the flash memory cell in the pth row and the jth column in the table, and optionally, referring to Figure 4, the flash cell in the pth row and jth column is the flash cell in the selected column and the unselected row, the voltage of the erase gate EG of the flash cell in the pth row and jth column is the selected voltage, about 3.5V-5V, and can also be other values; the voltage of the control gate CG of the flash cell in the pth row and jth column is the preset voltage, for example, 2.5V-5V, and can also be other values, which can be determined according to actual conditions; the voltage of the drain BL of the flash cell in the pth row and jth column is, for example, 0.5V; and the voltage Vfg1 of the floating gate FG of the flash cell in the pth row and jth column is Vfg1=CReg1*Veg1+CRcg1*Vcg1+CRwl1*Vwl1+CRsl1*Vsl1+Qfg1 / Ctot_fg1, where Veg1 is the voltage of the erase gate of the flash cell in the pth row and jth column, CReg1 is the coupling capacitance ratio of the erase gate to the floating gate of the flash cell in the pth row and jth column, Vcg1 is the voltage of the control gate of the flash cell in the pth row and jth column, CRcg1 is the coupling capacitance ratio of the control gate to the floating gate of the flash cell in the pth row and jth column, Vwl1 is the voltage of the select gate of the flash cell in the pth row and jth column, CRwl1 is the coupling capacitance ratio of the select gate to the floating gate of the flash cell in the pth row and jth column, Vsl1 is the voltage of the source of the flash cell in the pth row and jth column, CRsl1 is the coupling capacitance ratio of the source to the floating gate of the flash cell in the pth row and jth column, Qfg1 is the programmed charge in the floating gate of the flash cell in the pth row and jth column, and Ctot_fg1 is the sum of the floating gate capacitances of the flash cell in the pth row and jth column. Taking Veg1=4.5V and Vcg1=5V as examples, Vfg1=4.5V*0.22+Vcg*0.4+Qfg1 / Ctot_fg1, and Vfg1 is about 2.5V-3.5V, and the voltage difference between Vfg1 and Veg1 is about 1V-2V; the voltage difference between the floating gate FG and the erase gate EG of the flash cell in the pth row and jth column is small, and tunneling does not occur, so that the programming voltage of the flash cell in the pth row 1021 can be maintained, interference to the programmed flash cell is reduced, and the programming data accuracy is improved.

[0059] Figure 5 is Figure 3 the structure diagram of the flash cell in the pth row and kth column in the memory, which can be optionally referred to Figure 5The flash memory cell in the pth row and the kth column is a flash memory cell in an unselected row and an unselected column; the voltage Veg2 of the erase gate EG of the flash memory cell in the pth row and the kth column is 0 V; the voltage Vcg2 of the control gate CG of the flash memory cell in the pth row and the kth column is a preset voltage, for example, 2.5 V-5 V, or other values, which can be determined according to actual conditions; the voltage of the drain BL of the flash memory cell in the pth row and the kth column is, for example, 0 V or the power supply voltage Vdd, which can be determined according to actual conditions; the voltage Vfg2 of the floating gate FG of the flash memory cell in the pth row and the kth column is Vcg2*0.4+Qfg2 / Ctot_fg2, where Qfg2 is the charge programmed in the floating gate of the flash memory cell in the pth row and the kth column, and Ctot_fg2 is the sum of the floating gate capacitances of the flash memory cell in the pth row and the kth column. When the flash memory cell is in an erase state, for example, Vcg2=4.5 V, Vfg2 is about 1.8 V-3 V, the difference between Veg2 and Vfg2 is small, and the flash memory cell in the pth row and the kth column will not tunnel. When the flash memory cell is in a program state, for example, Vcg2=4.5 V, Vfg2 is about 0 V-1.8 V, the difference between Veg2 and Vfg2 is small, and the flash memory cell in the pth row and the kth column will not tunnel. Therefore, when the control gate line CG' is used to write the preset voltage into the flash memory cell in the pth row, the flash memory cells in other columns will not be affected, and the flash memory cell in the pth row and the kth column will not be disturbed.

[0060] It should be noted that, Figure 4 and Figure 5 are structural diagrams of flash memory cells, so Figure 4 and Figure 5 have the same structure, but Figure 4 represents any flash memory cell in the pth row and the jth column, Figure 5 represents any flash memory cell in the pth row and the kth column, and the voltage conditions of the flash memory cell in the pth row and the jth column are different from those of the flash memory cell in the pth row and the kth column.

[0061] Optionally, referring to Figure 3 each two adjacent rows of flash memory cells 1021 form a flash memory group 103, and each flash memory group 103 is connected with a source line SL', which is arranged between the two rows of flash memory cells 1021 in the flash memory group 103; in each flash memory group 103, the second transistor M2 is arranged close to the source line SL' in the two flash memory cells 1021 in the same column, and the first transistor M1 is arranged on the side of the source line SL' away from the second transistor M2.

[0062] Specifically, each flash memory group 103 is connected with one source line SL', i.e. each two adjacent rows of flash memory cells 1021 share one source line SL', the number of source lines SL' can be reduced, thus the number of wirings in the flash memory chip can be reduced, which is beneficial to reduce the size of the flash memory chip. Moreover, in the two flash memory cells 1021 in the same column, the second transistor M2 is arranged close to the source line SL', which can facilitate the connection of the sources of the two second transistors M2 and facilitate the wiring.

[0063] Optionally, referring to Figure 3 , the flash memory chip further comprises a programming circuit 104; the controller 101 is electrically connected with the flash memory array 102 through the programming circuit 104.

[0064] Specifically, according to the control instruction of the controller 101, the programming circuit 104 can write a programming voltage to the source line SL' and the control gate line CG', and write an erase voltage to the erase gate line EG', so as to write the programming voltage or the erase voltage to the flash memory array 102, and realize the programming or erasing operation of the flash memory array 102. The controller 101 can also write a preset voltage to the control gate line CG' through the programming circuit 104, so as to write the preset voltage to the control gate CG of the flash memory cell 1021 through the control gate line CG'.

[0065] Figure 6 is a flowchart of a programming method of a flash memory chip provided by an embodiment of the present application, referring to Figure 2 and Figure 6 , the programming method of the flash memory chip comprises:

[0066] S210, when selecting the to-be-programmed flash memory cell located at the ith row and the jth column by providing a selection voltage to the flash memory cell in the ith row through the selection gate line and providing a selection voltage to the flash memory cell in the jth column through the erase gate line, a preset voltage is provided to the flash memory cell in the pth row through the control gate line; wherein i≥1, j≥1, p≥1, and p is not equal to i.

[0067] Specifically, when the flash memory cell to be programmed located at the i-th row and the j-th column needs to be programmed, the flash memory cell to be programmed located at the i-th row and the j-th column is selected by selecting the gate line WL' to write a selection voltage to the i-th row of flash memory cells 1021 and providing a selected voltage to the j-th column of flash memory cells 1021 through the erase gate line EG', the controller 101 writes a programming voltage to the selected flash memory cell to be programmed to program the flash memory cell to be programmed. And when the flash memory cell to be programmed located at the i-th row and the j-th column is selected, the voltage of the second end of the flash memory cell in the j-th column is the selected voltage. By controlling the gate line CG' to provide a preset voltage to the p-th row of flash memory cells, p is not equal to i, that is, a preset voltage is written to the first end of the flash memory cells 1021 in the remaining rows except the i-th row; the voltage of the first end of the p-th row of flash memory cells 1021 is coupled to the floating gate of the p-th row of flash memory cells 1021, that is, the floating gate voltage of the p-th row of flash memory cells 1021 is increased, thereby reducing the voltage difference between the second end and the floating gate of the p-th row of flash memory cells 1021, and the tunneling of the p-th row of flash memory cells 1021 due to the writing of the selected voltage by the erase gate line EG' can be avoided; thereby, the programming voltage written to the p-th row of flash memory cells 1021 can be maintained, the interference to the programmed flash memory cells is reduced, and the programming data accuracy is improved.

[0068] Figure 7 is a flowchart of a test method of a flash memory chip provided by an embodiment of the present application, referring to Figure 2 and Figure 7 , the test method of the flash memory chip comprises:

[0069] S310, write an erase voltage to the flash memory cell to be erased through the erase gate line.

[0070] Specifically, the flash memory cell to be erased is, for example, all flash memory cells 1021 in the flash memory array 102, and the controller 101 writes an erase voltage to the flash memory cell to be erased through the erase gate line EG', that is, performs an erase operation on the entire flash memory array, which is convenient for operation, and the erase voltage is, for example, a voltage greater than 10V, and can also be other voltage values, thereby realizing the erase operation; the test of the flash memory chip is performed in the background of the entire flash memory array being erased.

[0071] S320, provide a selection voltage to the i-th row of flash memory cells through the selection gate line, and provide a selected voltage to the j-th column of flash memory cells through the erase gate line to select the flash memory cell to be programmed located at the i-th row and the j-th column, and program the flash memory cell to be programmed; wherein i≥1, j≥1.

[0072] Specifically, the controller 101 selects the gate line WL' to write a selection voltage to the i-th row of flash memory cells 1021, and selects the erase gate line EG' to provide a selection voltage to the j-th column of flash memory cells 1021, so as to select the flash memory cell to be programmed in the i-th row and the j-th column; the controller 101 writes a programming voltage to the selected flash memory cell to be programmed, so as to program the flash memory cell to be programmed.

[0073] In S330, a preset voltage is written to the first to-be-tested cell through the control of the gate line, and when the parameter information of the first to-be-tested cell meets the first preset condition, it is determined that the flash memory chip is qualified; wherein p is greater than or equal to 1, and p is not equal to i, and the first to-be-tested cell is any flash memory cell in the p-th row and the j-th column.

[0074] Specifically, the controller 101 controls the gate line CG' to provide a preset voltage to the p-th row of flash memory cells, and p is not equal to i, that is, a preset voltage is written to the first end of the flash memory cells 1021 in the remaining rows except the i-th row, so as to write a preset voltage to the first to-be-tested cell; the voltage at the first end of the p-th row of flash memory cells 1021 is coupled to the floating gate of the p-th row of flash memory cells 1021, that is, the voltage of the floating gate of the p-th row of flash memory cells 1021 is increased, so as to reduce the voltage difference between the second end and the floating gate of the p-th row of flash memory cells 1021, thereby avoiding the tunneling of the p-th row of flash memory cells 1021 due to the writing of the selection voltage by the erase gate line EG'. The parameter information of the first to-be-tested cell is collected, and the parameter information includes, for example, voltage information and current information. When the parameter information of the first to-be-tested cell meets the first preset condition, for example, the voltage difference between the second end and the floating gate of the first to-be-tested cell is small, or the current of the first to-be-tested cell meets the requirement, that is, the first to-be-tested cell will not tunnel, it can be determined that the flash memory chip is qualified.

[0075] On the basis of the above technical solutions, the parameter information of the first to-be-tested cell meeting the first preset condition comprises:

[0076] The difference between the erase gate voltage and the floating gate voltage of the first to-be-tested cell is less than the tunneling threshold voltage.

[0077] Specifically, with reference to Figure 3 When the difference between the erase gate voltage and the floating gate voltage of the first to-be-tested cell is less than the tunneling threshold voltage, the first to-be-tested cell will not tunnel, and will not interfere with the programmed data, so the voltage of the first to-be-tested cell meets the requirement, and the parameter information of the first to-be-tested cell meets the first preset condition.

[0078] Optionally, in some other embodiments, after step S310, the flash memory cells in the entire flash memory array can be programmed, and then a preset voltage is written to the flash memory cells in the entire flash memory array, and then whether the flash memory chip is qualified is determined according to the parameter information of all flash memory cells, which can facilitate operation, reduce detection time, and improve test efficiency.

[0079] Figure 8 is a flowchart of still another test method of a flash memory chip provided by an embodiment of the present application, which is optionally combined with Figure 3 and Figure 8 , the test method of the flash memory chip comprises:

[0080] S410, write an erase voltage to a to-be-erased flash memory cell through an erase gate line.

[0081] S420, collect a second initial current of a second to-be-tested cell, and when the second initial current is greater than a second preset current, write a preset voltage to the second to-be-tested cell through a control gate line; wherein the second to-be-tested cell is any flash memory cell in the pth row and the kth column, wherein k is greater than or equal to 1, and k is not equal to j.

[0082] Specifically, the second to-be-tested cell is any flash memory cell in the pth row and the kth column, i.e., a flash memory cell in a different row and a different column from the selected to-be-programmed cell. Because an erase operation is performed, the flash memory cell 1021 has fewer electrons, i.e., the current of the flash memory cell 1021 is greater. If the second initial current is less than or equal to the second preset current, it indicates that the second initial current of the second to-be-tested cell is too small, and the flash memory chip may be abnormal, i.e., the abnormal flash memory chip can be selected. If the second initial current is greater than the second preset current, the flash memory chip is further tested, and the preset voltage is written to the second to-be-tested cell through the control gate line CG', and the second to-be-tested cell is tested for interference.

[0083] S430, collect a second test current of the second to-be-tested cell, and when a difference between the second test current and the second initial current is within a second difference range, determine that the second to-be-tested cell is normal.

[0084] Specifically, after the preset voltage is written to the second to-be-tested cell through the control gate line CG', the current of the second to-be-tested cell changes. If the difference between the second test current and the second initial current is within the second difference range, it indicates that the current change of the second to-be-tested cell is normal, and the flash memory cell in the pth row and the kth column will not tunnel. Therefore, when the preset voltage is written to the flash memory cell in the pth row through the control gate line CG', the flash memory cells in other columns will not be affected, and the flash memory cell in the pth row and the kth column will not be interfered.

[0085] If the difference between the second test current and the second initial current is not within the second difference range, the second to-be-tested cell may be abnormal, i.e., the abnormal flash memory chip can be selected.

[0086] S440, provide a selection voltage to the flash memory cell in the ith row through a selection gate line, and provide a selected voltage to the flash memory cell in the jth column through an erase gate line to select the to-be-programmed flash memory cell in the ith row and the jth column, and program the to-be-programmed flash memory cell; wherein i is greater than or equal to 1, and j is greater than or equal to 1.

[0087] S450, collect the first initial current of the first to-be-tested unit, and when the first initial current is less than the first preset current, write a preset voltage into the first to-be-tested unit by controlling the gate line.

[0088] Specifically, because the programming operation is performed, the current of the first to-be-tested unit is small, if the first initial current is greater than or equal to the first preset current, the first initial current of the first to-be-tested unit is too large, and the first to-be-tested unit may be abnormal, that is, the abnormal flash memory chip can be selected; if the first initial current is less than the first preset current, the current of the first to-be-tested unit is normal; by controlling the gate line CG' to write a preset voltage into the first to-be-tested unit, the interference test is performed on the first to-be-tested unit.

[0089] S460, collect the first test current of the first to-be-tested unit, and when the difference between the first test current and the first initial current of the first to-be-tested unit is within the first preset range, determine that the parameter information of the first to-be-tested unit meets the first preset condition, and determine that the flash memory chip is qualified.

[0090] Specifically, after the preset voltage is written into the first to-be-tested unit by controlling the gate line CG', the current of the first to-be-tested unit changes, if the difference between the first test current and the first initial current of the first to-be-tested unit is not within the first preset range, the first to-be-tested unit may be interfered, the first to-be-tested unit is abnormal, that is, the abnormal flash memory chip can be selected; if the difference between the first test current and the first initial current of the first to-be-tested unit is within the first preset range, the current change of the first to-be-tested unit is normal, that is, it can be determined that the flash memory chip is qualified.

[0091] It should be understood that various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0092] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A flash memory chip, characterized in that, include: A controller and a flash memory array electrically connected to the controller, wherein a plurality of flash memory cells are arranged in an array within the flash memory array; The flash memory chip further includes: multiple control gate lines, which extend along a first direction, the first direction being the row direction of the flash memory cell array, and each control gate line connecting to the first end of a row of flash memory cells; Multiple erase gate lines extend along a second direction, which is the column direction of the flash memory cell array. Each erase gate line connects to the second end of a column of flash memory cells. Multiple selection gate lines extend along the first direction, and each selection gate line connects to the third end of a row of flash memory cells; The multiple erase gate lines and the multiple select gate lines are used to select the flash memory cell to be programmed; The controller is used to provide a selection voltage to the flash memory cell in the i-th row through the selection gate line, and to provide a selection voltage to the flash memory cell in the j-th column through the erase gate line. When the flash memory cell to be programmed is selected in the i-th row and j-th column, a preset voltage is provided to the flash memory cell in the p-th row through the control gate line, where i≥1, j≥1, p≥1, and p is not equal to i.

2. The flash memory chip according to claim 1, characterized in that, It also includes multiple drain lines and multiple source lines. The plurality of source lines extend along the first direction, and each source line connects to the fourth end of at least one row of flash memory cells; The plurality of drain lines extend along the second direction, and each drain line is electrically connected to the fifth terminal of a column of flash memory cells; Alternatively, the plurality of drain lines extend along the first direction, and each drain line is electrically connected to the fifth terminal of a row of flash memory cells.

3. The flash memory chip according to claim 2, characterized in that, The flash memory cell includes a first transistor and a second transistor; The gate of the first transistor is the third terminal of the flash memory cell, and the drain of the first transistor is the fifth terminal of the flash memory cell. The control gate of the second transistor is the first terminal of the flash memory cell, the drain of the second transistor is electrically connected to the source of the first transistor, the erase gate of the second transistor is the second terminal of the flash memory cell, and the source of the second transistor is the fourth terminal of the flash memory cell; the second transistor also includes a floating gate.

4. The flash memory chip according to claim 3, characterized in that, Each pair of adjacent rows of flash memory cells forms a flash memory group, and each flash memory group is connected to a source line, which is disposed between the two rows of flash memory cells in the flash memory group. In each of the flash memory groups, in two flash memory cells in the same column, the second transistor is disposed close to the source line, and the first transistor is disposed on the side of the source line away from the second transistor.

5. The flash memory chip according to claim 1, characterized in that, It also includes programming circuits; The controller is electrically connected to the flash memory array via the programming circuit.

6. A method for programming a flash memory chip, characterized in that, The programming method is used for programming the flash memory chip according to any one of claims 1-5, the programming method comprising: When a flash memory cell in row i is selected by selecting a gate line and a selection voltage is provided to the flash memory cell in column j by erasing a gate line, a preset voltage is provided to the flash memory cell in row p by controlling a gate line; where i≥1, j≥1, p≥1, and p is not equal to i.

7. A testing method for a flash memory chip, characterized in that, The test method for testing the flash memory chip according to any one of claims 1-5 includes: An erase voltage is written to the flash memory cell to be erased by erasing the erase gate line; The flash memory cell to be programmed is selected by providing a selection voltage to the flash memory cell in the i-th row through the selection gate line and a selection voltage to the flash memory cell in the j-th column through the erase gate line; where i≥1, j≥1; A preset voltage is written to the first unit under test by controlling the gate line. When the parameter information of the first unit under test meets the first preset condition, the flash memory chip is determined to be qualified; wherein, p≥1 and p is not equal to i, and the first unit under test is any of the flash memory cells in the p-th row and j-th column.

8. The test method for a flash memory chip according to claim 7, characterized in that, A preset voltage is written to the first unit under test by controlling the gate line. When the parameter information of the first unit under test meets the first preset condition, it includes: The first initial current of the first unit under test is collected. When the first initial current is less than the first preset current, a preset voltage is written to the first unit under test through the control gate line. The first test current of the first unit under test is collected. When the difference between the first test current and the first initial current of the first unit under test is within a first preset range, it is determined that the parameter information of the first unit under test meets the first preset condition.

9. The testing method for a flash memory chip according to claim 7, characterized in that, Before providing the selection voltage to the flash memory cell in the i-th row via the selection gate line, the method further includes: The second initial current of the second unit under test is collected. When the second initial current is greater than the second preset current, a preset voltage is written to the second unit under test through the control gate line. The second unit under test is any of the flash memory cells in the p-th row and k-th column, where k≥1 and k is not equal to j. The second test current of the second unit under test is collected. When the difference between the second test current and the second initial current is within the second difference range, the second unit under test is determined to be normal.

10. The test method for a flash memory chip according to claim 7, characterized in that, The parameter information of the first unit under test satisfies the first preset condition, including: The difference between the erase gate voltage and the floating gate voltage of the first test cell is less than the tunneling threshold voltage.

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