Method of improving PMOS ac performance

Abstract

The application provides a method for improving PMOS AC performance, which comprises the following steps: providing a substrate, forming an active region on the substrate, forming a plurality of gate structures on the active region, and forming an epitaxial layer between the two gate structures, forming a side wall structure for etching protection on the side wall of the gate structure, and forming a stack for etching protection between the epitaxial layer and the gate structure; etching and removing the stack to form a groove; forming a low-K dielectric layer covering the gate structure and the epitaxial layer on the substrate, so that the low-K dielectric layer fills the groove; forming a first side wall on the low-K dielectric layer; and etching the first side wall to a target thickness. In the application, the filling layer between the gate and the epitaxial layer is changed from a SIN layer, an oxidation layer and a SiN layer into a silicon nitride layer and an oxidation layer, the medium K value is reduced, and the AC performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a method for improving AC performance of PMOS. BACKGROUND

[0002] For PMOS, SiGe (embedded germanium silicon technology) can significantly improve the device performance by generating compressive stress on the channel.

[0003] In the current process, please refer to Figure 1 , the filling layer in the space between the gate and the SiGe epitaxial layer is the SIN layer, the oxide layer, the SiN layer (the hard mask layer of the SiGe epitaxial layer), and due to K (SiN) > K (oxide), the existence of the SiGe hard mask layer will have a negative effect on the AC (alternating current) capacitance.

[0004] In order to solve the above problems, a new method for improving the AC performance of PMOS needs to be proposed. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving the AC performance of PMOS, which is used to solve the problem that in the current process, the filling layer in the space between the gate and the SiGe epitaxial layer is the SIN layer, the oxide layer, the SiN layer, and due to K (SiN) > K (oxide), the existence of the SiGe hard mask layer will have a negative effect on the AC (alternating current) capacitance.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving the AC performance of PMOS, which comprises:

[0007] Step one, providing a substrate, forming an active region on the substrate, forming a plurality of gate structures on the active region, and forming an epitaxial layer between the two gate structures, the sidewall of the gate structure is formed with a side wall structure for etching protection, and the epitaxial layer and the gate structure are formed with a stack layer for etching protection;

[0008] Step two, etching to remove the stack layer to form a groove;

[0009] Step three, forming a low-K dielectric layer on the substrate to cover the gate structure and the epitaxial layer, so that the low-K dielectric layer fills the groove;

[0010] Step four, forming a first side wall on the low-K dielectric layer;

[0011] Step five, etching the first side wall to a target thickness.

[0012] Preferably, the substrate in step one is a silicon substrate.

[0013] Preferably, the epitaxial layer in step one is a germanium-silicon epitaxial layer.

[0014] Preferably, the gate structure in step one is composed of a polysilicon layer, an ONO layer and a gate insulating layer stacked from bottom to top.

[0015] Preferably, the stack in step one is composed of a first silicon nitride layer, an oxide layer and a second silicon nitride layer stacked from bottom to top.

[0016] Preferably, the side wall structure in step one comprises a second and a third side wall structure.

[0017] Preferably, the material of the second side wall in step one is silicon dioxide.

[0018] Preferably, the material of the third side wall in step one is silicon nitride.

[0019] Preferably, the stack in step two is etched by a wet etching method, so that the second silicon nitride layer is removed.

[0020] Preferably, the material of the low-K dielectric layer in step three is silicon dioxide.

[0021] Preferably, the material of the first side wall in step four is silicon nitride.

[0022] Preferably, the etching method in step five is dry etching.

[0023] As described above, the method for improving the AC performance of PMOS according to the present application has the following beneficial effects:

[0024] The present application changes the filling layer between the gate and the epitaxial layer from SIN layer, oxide layer and SiN layer to silicon nitride layer and oxide layer, reduces the dielectric K value, and improves the AC performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A PMOS germanium-silicon epitaxial layer structure according to the prior art is shown in the schematic diagram;

[0026] Figure 2 An etching filling layer between the gate and the epitaxial layer according to the present application is shown in the schematic diagram;

[0027] Figure 3 Forming a low-K dielectric layer according to the present application is shown in the schematic diagram;

[0028] Figure 4 Forming a side wall according to the present application is shown in the schematic diagram;

[0029] Figure 5 Continuing to etch the side wall to adjust its thickness according to the present application is shown in the schematic diagram;

[0030] Figure 6 The process flow of the present application is shown in the following schematic diagram. DETAILED DESCRIPTION

[0031] The present application is described in detail by specific embodiments, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. The present application can also be implemented or applied by other different embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications without departing from the spirit of the present application.

[0032] Referring to Figure 6 The present application provides a method for improving PMOS AC performance, which comprises:

[0033] Step one, referring to Figure 1 , a substrate 101 is provided, and a plurality of gate structures 103 are formed on the substrate 101, and an epitaxial layer 110 is formed between the two gate structures 103, a side wall structure for etching protection is formed on the side wall of the gate structure 103, and a stack layer for etching protection is formed between the epitaxial layer 110 and the gate structure 103. Before the epitaxial layer 110 process, an oxide or nitride protective layer is needed for NMOS, and then after development, etching of the silicon substrate 101 of PMOS and removal of residual polymer are performed. Specifically, a silicon nitride layer can be formed on the substrate 101, and then the silicon nitride layer in the PMOS area is etched to define the formation area of the epitaxial layer 110, and then the epitaxial layer 110 is formed by etching and deposition, wherein the side wall structure and the stack layer are protective layers in the etching process.

[0034] In the embodiment of the present application, the substrate 101 in step one is a silicon substrate 101.

[0035] In the embodiment of the present application, the epitaxial layer 110 in step one is a germanium-silicon epitaxial layer 110, and the embedded germanium-silicon in the COMS process flow uses a selective germanium-silicon process. Before the selective germanium-silicon process, an oxide or nitride protective layer is needed for NMOS, and then after development, etching of the silicon substrate 101 of PMOS and removal of residual polymer are performed.

[0036] In the embodiment of the present application, the gate structure 103 in step one is composed of a polysilicon layer, an ONO layer (oxide layer, nitride layer, oxide layer) and a gate insulating layer 106 stacked from bottom to top, and the material of the gate insulating layer 106 is silicon nitride or silicon dioxide.

[0037] In the embodiment of the present application, the side wall structure in step one includes second and third side wall structures.

[0038] In the embodiment of the present application, the material of the second side wall 104 in step one is silicon dioxide, which can be formed by chemical vapor deposition.

[0039] In the embodiment of the present application, the structure of the third side wall 105 in step one is silicon nitride, which can be formed by chemical vapor deposition.

[0040] In the embodiment of the present application, the stack in step one is composed of the first silicon nitride layer 107, the oxide layer 108 and the second silicon nitride layer 109 stacked from bottom to top.

[0041] Step two, please refer to Figure 2 , etching to remove the stack to form the groove, i.e. etching to remove the stack with higher K value to reserve space for forming the medium layer with lower K value later;

[0042] In the embodiment of the present application, the stack is etched by wet etching in step two, so that the stack is removed, i.e. the first silicon nitride layer 107, the oxide layer 108 and the second silicon nitride layer 109 stacked from bottom to top are etched and removed in turn.

[0043] Step three, please refer to Figure 3 , forming the low-K medium layer 111 covering the gate structure 103 and the epitaxial layer 110 on the substrate 101, so that the low-K medium layer 111 fills the groove;

[0044] In the embodiment of the present application, the material of the low-K medium layer 111 in step three is silicon dioxide, which can be formed by chemical vapor deposition.

[0045] Step four, please refer to Figure 4 , forming the first side wall 112 on the low-K medium layer 111;

[0046] In the embodiment of the present application, the material of the first side wall 112 in step four is silicon nitride.

[0047] Step five, please refer to Figure 5 , etching the exposed low-K medium layer 111 to the target thickness, i.e. the critical dimension of the first side wall 112 formed by etching should be controlled within the required range.

[0048] In the embodiment of the present application, the etching method in step five is dry etching, which removes the stack, i.e. the first silicon nitride layer 107, the oxide layer 108 and the second silicon nitride layer 109 filling the groove become the low-K medium layer 111 filling the groove and the first side wall 112 formed on the low-K medium layer, which reduces the medium K value and improves the AC performance of the device.

[0049] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the diagrams, not drawn according to the number, shape and size of the components in actual implementation. The shape, number and proportion of each component in actual implementation can be arbitrarily changed, and the component layout pattern can be more complex.

[0050] In summary, the present application changes the filling layer between the gate and the epitaxial layer from SIN layer, oxide layer and SiN layer to silicon nitride layer and oxide layer, reduces the medium K value, and improves the AC performance of the device. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0051] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of improving PMOS AC performance, comprising: At least comprising: Step one, providing a substrate, forming an active region on the substrate, forming a plurality of gate structures on the active region, and forming an epitaxial layer between two gate structures, forming a side wall structure for etching protection on the side wall of the gate structure, forming a stack for etching protection between the epitaxial layer and the gate structure, the stack is composed of a first silicon nitride layer, an oxide layer, and a second silicon nitride layer stacked from bottom to top; Step two, etching to remove the stack to form a groove; Step three, forming a low-K dielectric layer on the substrate to cover the gate structure and the epitaxial layer, so that the low-K dielectric layer fills the groove, and the material of the low-K dielectric layer is silicon dioxide; Step four, forming a first side wall on the low-K dielectric layer, and the material of the first side wall is silicon nitride; Step five, etching the first side wall to a target thickness.

2. The method of claim 1, wherein: The substrate in step one is a silicon substrate.

3. The method of claim 2 to improve PMOS AC performance, wherein: The epitaxial layer in step one is a germanium-silicon epitaxial layer.

4. The method of claim 1, wherein: The gate structure in step one is composed of a polysilicon layer, an ONO layer, and a gate insulating layer stacked from bottom to top.

5. The method of improving PMOS AC performance of claim 1, wherein: The side wall structure in step one includes second and third side wall structures.

6. The method of improving PMOS AC performance of claim 5, wherein: The structure of the second side wall in step one is silicon oxide.

7. The method of improving PMOS AC performance of claim 5, wherein: The structure of the third side wall in step one is silicon nitride.

8. The method of claim 1, wherein: In step two, the stack is removed by wet etching.

9. The method of claim 1, wherein: In step five, the etching method is dry etching.

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