Encapsulations and methods of making the same

Abstract

The application discloses a packaging body and a preparation method thereof, wherein the packaging method of the packaging body comprises the following steps: obtaining a carrier plate with a plurality of conductive bosses formed on at least one side of the carrier plate, and arranging a release plating-resistant film on at least one side of the carrier plate, and exposing the conductive bosses; electroplating at least one side of the carrier plate to prepare a solder pad on the side of each conductive boss away from the carrier plate; wherein the solder pad comprises a first solder pad and a second solder pad; corresponding mounting a chip to the side of the first solder pad away from the carrier plate, and packaging the chip; preparing a connecting piece on the side of the chip away from the carrier plate and the side of the second solder pad away from the carrier plate, and electrically connecting the chip and the second solder pad through the connecting piece; removing the carrier plate and the release plating-resistant film to prepare the packaging body. Through the above method, the alignment accuracy of the inner and outer solder pads can be improved, and the structural stability and reliability of the packaging body are enhanced.

Description

Technical Field

[0001] This invention applies to the technical field of board packaging, and in particular to a package and its preparation method. Background Technology

[0002] Packaging technology is used to house semiconductor integrated circuit chips, and plays a role in placing, fixing, sealing, protecting the chip, enhancing its electrothermal performance, and also serves as a bridge between the internal circuitry of the chip and the external circuitry.

[0003] Currently, when packaging products are made with external pads, due to the high density and miniaturization of packaging, there are very precise requirements for the alignment between the inner and outer pads.

[0004] However, due to the high density and miniaturization of the packaging, the inner and outer pads are very easy to misalign, which affects the reliability of the package. Summary of the Invention

[0005] This invention provides a package and its preparation method to solve the problem of easy misalignment between the inner and outer pads of the package.

[0006] To address the aforementioned technical problems, the present invention provides a packaging method for a package, comprising: obtaining a carrier plate having a plurality of conductive protrusions formed on at least one side, and providing a release liner on at least one side of the carrier plate, exposing each conductive protrusion; electroplating at least one side of the carrier plate to prepare pads on the side of each conductive protrusion away from the carrier plate; wherein the pads include a first pad and a second pad; mounting a chip to the side of the first pad away from the carrier plate and encapsulating the chip; preparing connectors on the side of the chip away from the carrier plate and on the side of the second pad away from the carrier plate, electrically connecting the chip and the second pad through the connectors; and removing the carrier plate and the release liner to prepare the package.

[0007] The step of electroplating at least one side of the carrier board to prepare pads on the side of each conductive boss away from the carrier board includes: pressing a first rigid member onto the side of the release liner away from the carrier board; drilling holes in the first rigid member based on the position of each conductive boss to form through holes exposing each conductive boss; electroplating the side of the first rigid member away from the carrier board until each through hole is filled and a first conductive layer is formed on the side of the first rigid member away from the carrier board; and etching the first conductive layer based on the position of each conductive boss to form each pad.

[0008] The thickness of the conductive boss is the same as the thickness of the release coating.

[0009] The steps of mounting the chip to the side of the first pad away from the carrier board and encapsulating the chip include: pasting or soldering the chip to the side of each first pad away from the carrier board; encapsulating the chip to form an encapsulation layer that wraps the chip and fills the gap between the chip and the release liner.

[0010] The step of fabricating connectors on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board, and electrically connecting the chip and the second pad through the connectors, includes: drilling holes in the package layer from the side away from the carrier board based on the positions of each chip and each second pad, to form first blind vias exposing each chip and second blind vias exposing each second pad; electroplating the side of the package layer away from the carrier board to fill the first blind vias and second blind vias to form first conductive vias and second conductive vias respectively, and forming a second conductive layer on the side of the package layer away from the carrier board; etching the second conductive layer, and retaining the second conductive layer between the first conductive vias and the second conductive vias to form the connectors.

[0011] The step of preparing connectors on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board to electrically connect the chip and the second pad further includes: pressing a second rigid member onto the side of the encapsulation layer away from the carrier board.

[0012] The steps of obtaining a carrier board with multiple conductive protrusions formed on at least one side, and setting a release liner on at least one side of the carrier board to expose each conductive protrusion include: obtaining the carrier board and preparing multiple conductive protrusions on opposite sides of the carrier board; setting a release liner on opposite sides of the carrier board and exposing each conductive protrusion; electroplating at least one side of the carrier board to prepare pads on the side of each conductive protrusion away from the carrier board includes: electroplating opposite sides of the carrier board to prepare pads on the side of each conductive protrusion away from the carrier board; and removing the carrier board and the release liner to prepare a package includes: separating the carrier board and removing the release liner to prepare two packages.

[0013] To solve the above-mentioned technical problems, the present invention provides a package comprising: a plurality of pads disposed on the same horizontal plane, the pads including a first pad and a second pad; a chip mounted on one side of the first pad; a connector, one end of which is electrically connected to the side of the chip away from the first pad, and the other end of which is electrically connected to one side of the second pad; and a plurality of conductive bumps, each conductive bump being electrically connected to the other side of its corresponding pad.

[0014] The package also includes: a package layer that wraps the chip; a connector including a first conductive hole, a second conductive layer and a second conductive hole, wherein the chip and the corresponding second pad are electrically connected in sequence through the first conductive hole, the second conductive layer and the second conductive hole; the package layer wraps the chip and the sides of the first conductive hole, the second conductive hole and the pad, and the second conductive layer is attached to one side of the package layer.

[0015] The package further includes: a first rigid member; the first rigid member is attached to the side of the package layer away from the connector; the first rigid member has through holes formed at the positions corresponding to each pad, and conductive members are formed in the through holes, one end of each conductive member is electrically connected to the corresponding pad, and the other end of each conductive member is electrically connected to the corresponding conductive boss.

[0016] To address the aforementioned technical problems, the packaging method of the present invention involves obtaining a carrier plate with multiple conductive bumps formed on at least one side, and setting a release liner on at least one side of the carrier plate, exposing each conductive bump; electroplating at least one side of the carrier plate to prepare pads on the side of each conductive bump away from the carrier plate; mounting a chip to the side of the first pad away from the carrier plate and encapsulating the chip; preparing a connector to electrically connect the chip and the second pad; and removing the carrier plate and the release liner to prepare the package. By preparing the pads through setting the release liner and exposing the conductive bumps before electroplating, the conductive bumps and pads ultimately form the outer and inner pads of the package, respectively, thus avoiding the need for alignment between the inner and outer pads. Precise molding is achieved directly through electroplating, which greatly improves the alignment accuracy between the outer and inner pads of the package, thereby enhancing the structural stability and reliability of the package. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the packaging method for the packaged body provided by the present invention;

[0018] Figure 2 This is a schematic flowchart of another embodiment of the packaging method for the packaged body provided by the present invention;

[0019] Figure 3 yes Figure 2 A schematic diagram of the structure of an embodiment following the fabrication of the conductive protrusion;

[0020] Figure 4 yes Figure 2 A schematic diagram of a subsequent embodiment with a release liner for resisting coating provided in this example;

[0021] Figure 5 yes Figure 2 A schematic diagram of the structure of a subsequent embodiment after the preparation of the pads in the example;

[0022] Figure 6 yes Figure 2 A schematic diagram of the structure of the latter embodiment of the encapsulation in the example;

[0023] Figure 7 yes Figure 2 A schematic diagram of the structure of a later embodiment of the preparation of the connector in the examples;

[0024] Figure 8 yes Figure 2 A schematic diagram of another embodiment after the pads are prepared in the example;

[0025] Figure 9 This is a schematic diagram of the structure of an embodiment of the package provided by the present invention;

[0026] Figure 10 This is a schematic diagram of another embodiment of the package provided by the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0029] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0030] Please see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the encapsulation method for the encapsulated body provided by the present invention.

[0031] Step S11: Obtain a carrier plate with multiple conductive protrusions formed on at least one side, and provide a release coating on at least one side of the carrier plate, exposing each conductive protrusion.

[0032] A carrier plate with multiple conductive protrusions formed on at least one side is obtained. In one specific application scenario, a carrier plate with multiple conductive protrusions formed on one side can be obtained. In another specific application scenario, a carrier plate with multiple conductive protrusions formed on both opposite sides can also be obtained.

[0033] A release film is provided on at least one side of the carrier plate, exposing each conductive protrusion. That is, a release film is applied to the side of the carrier plate where the conductive protrusions are formed, but the conductive protrusions are exposed, so that the release film protects the area of ​​the carrier plate where the conductive protrusions are formed, except for the conductive protrusions, from plating.

[0034] Among them, release coating refers to a coating that can be completely removed later.

[0035] Step S12: Electroplating at least one side of the carrier board to prepare pads on the side of each conductive bump away from the carrier board; wherein the pads include a first pad and a second pad.

[0036] Electroplating is performed on at least one side of the carrier board. Since the release coating has protected the side of the carrier board where the conductive bosses are formed except for the conductive bosses, during electroplating, only the conductive bosses are plated with metal ions, so that pads are formed on the side of each conductive boss away from the carrier board.

[0037] The pads prepared in this step include a first pad and a second pad. The first pad is the one subsequently used for chip mounting. The second pad is the one not subsequently used for chip mounting, but for transmitting chip signals. The first and second pads have different functions, but their structure in this step can be the same.

[0038] Step S13: Mount the chip onto the side of the first pad furthest from the carrier board and encapsulate the chip.

[0039] The chip is mounted onto the side of the first pad furthest from the carrier board, and then encapsulated. The encapsulation material may specifically include one or more of the following: epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic-based materials. No specific limitations are specified here.

[0040] In a specific scenario, a carrier board can have multiple first pads, which are used to mount multiple chips to form a multi-chip package. The multiple chips can be independent of each other or connected. The specific settings can be set according to actual needs and are not limited here. When the multiple chips are set independently, the package can be cut later to obtain multiple single-chip packages.

[0041] In another specific application scenario, a single first pad can be formed on the carrier board to mount a single chip, forming a single-chip package.

[0042] Step S14: Prepare connectors on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board, and electrically connect the chip and the second pad through the connectors.

[0043] In a specific application scenario, when the chip is packaged and the entire chip is surrounded, when preparing the connector in this step, holes can be drilled first on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board to expose the chip and the second pad. Then the connector is prepared to electrically connect the chip and the second pad.

[0044] In another specific application scenario, when only the side of the chip is packaged during encapsulation, the connector can be directly fabricated during the board fabrication process to electrically connect the chip and the second pad.

[0045] The connector for connecting the chip and the second pad can be prepared by electroplating or welding a metal substrate.

[0046] Step S15: Remove the carrier plate and release coating to prepare the package.

[0047] After the connector is formed, the carrier plate and release coating are removed, thereby exposing the conductive bosses and forming the external pads of the package.

[0048] At this point, electrodes can be led out from one side of the chip through the first pad and conductive bump, and electrodes can be led out from the other side through the connector, the second pad and conductive bump, thereby realizing external signal connection.

[0049] In this embodiment, the pads are fabricated by electroplating after exposing the conductive bumps on the carrier board with a release film. This process ultimately allows the conductive bumps and pads to form the outer and inner pads of the package, respectively, thus avoiding the need for proper alignment of the inner and outer pads. Precise molding is achieved directly through electroplating, significantly improving the alignment accuracy between the outer and inner pads of the package.

[0050] Through the above steps, the packaging method of this embodiment involves obtaining a carrier plate with multiple conductive protrusions formed on at least one side, setting a release liner on at least one side of the carrier plate, and exposing each conductive protrusion; electroplating at least one side of the carrier plate to prepare pads on the side of each conductive protrusion away from the carrier plate; mounting a chip to the side of the first pad away from the carrier plate and encapsulating the chip; preparing a connector to electrically connect the chip and the second pad; and removing the carrier plate and the release liner to prepare the package. By setting a release liner and exposing the conductive protrusions before electroplating to prepare the pads, the conductive protrusions and pads ultimately form the outer and inner pads of the package, respectively, thus avoiding the process of aligning the inner and outer pads. Precise molding is achieved directly through electroplating, which greatly improves the alignment accuracy between the outer and inner pads of the package, thereby enhancing the structural stability and reliability of the package.

[0051] Please see Figure 2 , Figure 2 This is a schematic flowchart of another embodiment of the encapsulation method for the encapsulated body provided by the present invention. This embodiment describes the encapsulation of the encapsulated body by taking the example of having conductive protrusions prepared on both opposite sides of the carrier plate. When conductive protrusions are prepared on one side of the carrier plate, the preparation method is similar and is not limited here.

[0052] Step S21: Obtain a carrier plate and prepare multiple conductive protrusions on opposite sides of the carrier plate; set release coatings on opposite sides of the carrier plate and expose each conductive protrusion.

[0053] A carrier board is obtained, wherein copper layers can be formed on opposite sides of the carrier board, so that when fabricating conductive bumps on opposite sides of the carrier board, the copper layers can be used as a base to form conductive bumps. The copper layers may include peelable copper foil for easy subsequent removal.

[0054] In one specific application scenario, a protective layer can be applied to the copper layer at locations other than those corresponding to the conductive bumps, and then the substrate can be electroplated to form the conductive bumps at these locations. In another specific application scenario, a metal substrate can be directly soldered or bonded to the locations corresponding to the conductive bumps to form the conductive bumps. The method of forming the conductive bumps is not limited here.

[0055] Please see Figure 3 , Figure 3 yes Figure 2 A schematic diagram of the structure of an embodiment following the fabrication of the conductive protrusion in the examples.

[0056] The carrier plate 100 of this embodiment includes a base layer 101 and a copper layer 102, wherein the two copper layers 102 are respectively attached to two pairs of sides of the base layer 101.

[0057] Multiple conductive bumps 103 are formed on the copper layers 102 on opposite sides of the carrier board 100. The number of conductive bumps 103 on each side can be multiple, and the specific number can be set according to actual needs, and is not limited here.

[0058] After forming conductive bosses on opposite sides of the carrier plate, a release liner is applied to opposite sides of the carrier plate, exposing each conductive boss. The thickness of the conductive bosses is the same as the thickness of the release liner.

[0059] The release coating can be applied to opposite sides of a carrier substrate using screen printing or other lamination methods. The release coating refers to a coating that can be completely removed subsequently, including removable adhesive or removable epoxy materials.

[0060] Please see Figure 4 , Figure 4 yes Figure 2 A schematic diagram of the structure of an embodiment after setting the release anti-coating stage is shown in the example.

[0061] This embodiment is in Figure 3 Based on the implementation method, a release coating 104 is provided on the side of the copper layer 102 of the carrier plate 100 away from the base layer 101, and the release coating 104 exposes each conductive boss 103. The thickness of the conductive boss 103 is the same as the thickness of the release coating 104 to protect the side of the conductive boss 103.

[0062] Step S22: Electroplating is performed on opposite sides of the carrier board to prepare pads on the side of each conductive boss away from the carrier board, wherein the pads include a first pad and a second pad.

[0063] After applying the release liner, electroplating is performed on opposite sides of the carrier board to create pads on the side of each conductive bump away from the carrier board. In a specific application scenario, before electroplating, residual material on the conductive bumps can be cleaned using laser or chemical methods to completely expose the side of the conductive bump away from the carrier board, facilitating electroplating adhesion. The specific cleaning method depends on the application method of the release liner and is not limited here.

[0064] The pads include a first pad and a second pad. The first pad is the one subsequently used for chip mounting. The second pad is the one not subsequently used for chip mounting, but for transmitting chip signals. The first and second pads have different functions, but their structure in this step can be the same. In this embodiment, the first and second pads can be determined manually or based on experience.

[0065] Please see Figure 5 , Figure 5 yes Figure 2A schematic diagram of the structure of an embodiment following the preparation of the pads in the example.

[0066] This embodiment is in Figure 4 Based on the implementation method, pads 105 are prepared on the side of each conductive boss 103 away from the carrier plate 100. The pads 105 may include a first pad and a second pad.

[0067] In this embodiment, the conductive protrusion 103 is used to form the outer pad of the package, and the pad 105 is used to form the inner pad of the package. In this step, the contact between the inner and outer pads is achieved by electroplating and the adsorption of metal ions, thereby avoiding the subsequent steps of positioning and connecting the inner and outer pads, and greatly improving the alignment accuracy and connection stability between the inner and outer pads of the package.

[0068] Step S23: Attach or solder the chip to the side of each first pad away from the carrier board; encapsulate the chip to form an encapsulation layer that wraps around the chip and fills the gap between the chip and the release liner.

[0069] The chip is attached or soldered to the side of each first pad furthest from the carrier board. This step does not process the second pads. In one specific application scenario, the chip can be soldered to the side of each first pad furthest from the carrier board using solder paste or other soldering materials. In another specific application scenario, the chip can also be attached to the first pads using conductive adhesive, including silver paste, copper paste, etc., which are not limited here. The above methods achieve both chip fixation and electrical connection to the first pads.

[0070] In this embodiment, the chip can be mounted either upright or flip-chip. Therefore, it can meet the requirements for small-size packages with single or multiple chips and multiple pads.

[0071] After the chip is installed, it is encapsulated to form an encapsulation layer that surrounds the chip and fills the gap between the chip and the release liner. This encapsulation layer can be a dielectric layer, specifically including one or more of the following: epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic substrate.

[0072] Please see Figure 6 , Figure 6 yes Figure 2 A schematic diagram of the structure of the latter embodiment of the encapsulation in the example.

[0073] This embodiment is in Figure 5Based on the implementation method, the chip 106 is mounted onto each of the first pads 1051, the second pad 1052 is not mounted with a chip, and the encapsulation layer 107 wraps around each chip 106 and fills the gap between the chip 106 and the release liner 104. The first pads 1051 and the second pads 1052 together form the pad 105.

[0074] Step S24: Prepare connectors on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board, and electrically connect the chip and the second pad through the connectors.

[0075] After packaging, connectors are prepared on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board, and the chip and the second pad are electrically connected through the connectors.

[0076] Specifically, based on the positions of each chip and each second pad, holes can be drilled in the packaging layer from the side away from the carrier board to form first blind vias exposing each chip and second blind vias exposing each second pad. The drilling can be performed using mechanical drilling or laser drilling, and is not limited here.

[0077] After drilling, the side of the encapsulation layer away from the carrier board is electroplated to fill the first blind hole and the second blind hole to form the first conductive hole and the second conductive hole respectively, and a second conductive layer is formed on the side of the encapsulation layer away from the carrier board.

[0078] In a specific application scenario, electroplating can be performed on the entire board. A second conductive layer is formed on the side of the encapsulation layer furthest from the carrier board, filling the first and second blind vias to form corresponding first and second conductive vias. The thickness of the second conductive layer can be between 30-40µm, specifically 30µm, 34µm, 35µm, 36µm, 40µm, etc., depending on actual performance requirements and is not limited here.

[0079] The second conductive layer is etched, retaining the second conductive layer between the first conductive hole and the second conductive hole, and the other second conductive layers are removed to form a connector.

[0080] Please see Figure 7 , Figure 7 yes Figure 2 A schematic diagram of the structure of a subsequent embodiment of the preparation of the connector.

[0081] This embodiment is in Figure 6Based on the implementation method, a connector 108 is formed on the side of the encapsulation layer 107 away from the carrier board 100. The connector 108 includes a first conductive hole 1081, a second conductive layer 1082, and a second conductive hole 1083. The two ends of the first conductive hole 1081 are connected to the chip 106 and the second conductive layer 1082, respectively. The two ends of the second conductive layer 1082 are connected to the first conductive hole 1081 and the second conductive hole 1083, respectively. The two ends of the second conductive hole 1083 are connected to the second conductive layer 1082 and the second pad 1052, respectively.

[0082] Thus, one side of the chip 106 is electrically connected to the first pad 1051 and the conductive boss in sequence, and the other side is electrically connected to the connector 108, the second pad 1052 and the conductive boss in sequence.

[0083] In a specific application scenario, after the connector is fabricated, a second rigid component can be pressed onto the side of the encapsulation layer away from the carrier plate to enhance the structural rigidity of the encapsulation, thereby improving the structural stability and reliability of the encapsulation.

[0084] The second rigid component may include a prepreg or other rigid components, which are not limited here.

[0085] Step S25: Remove the carrier plate and release coating to prepare the package.

[0086] Since there are encapsulation bodies on both sides of the carrier plate in this embodiment, the carrier plate is split to remove the carrier plate and the release coating, thus obtaining two encapsulation bodies.

[0087] In a specific application scenario, after the board is separated, since the opposite sides of the carrier board are covered with copper layers, the copper layers can be removed by etching to expose the conductive bumps and release coating. Then, the release coating is removed by chemical or thermal methods, thereby exposing the exposed conductive bumps and forming the outer pads of the package.

[0088] In a specific application scenario, before separating the boards, a solder resist layer can be applied to the side of the second rigid component away from the carrier board to improve the insulation and protection of the package surface.

[0089] Furthermore, a coating layer can be applied to the exposed surface of the conductive protrusion to ensure the corpus luteum storage period of the branch tube. This coating layer can include conductive, oxidation-resistant materials such as electroless gold or nickel-gold. No specific limitations are imposed.

[0090] Finally, when multiple single-chip packages are fabricated on the entire substrate, the entire board can be cut to obtain multiple independent single-chip packages.

[0091] Through the above steps, the packaging method of this embodiment obtains a carrier board and prepares multiple conductive protrusions on opposite sides of the carrier board; a release liner is applied to opposite sides of the carrier board, exposing each conductive protrusion; then electroplating is performed on opposite sides of the carrier board to prepare pads on the side of each conductive protrusion away from the carrier board. By preparing pads through electroplating after applying the release liner and exposing the conductive protrusions, the conductive protrusions and pads ultimately form the outer and inner pads of the package, respectively, thus avoiding the process of aligning the inner and outer pads. Precise molding is achieved directly through electroplating, greatly improving the alignment accuracy between the outer and inner pads of the package. This enhances the structural stability and reliability of the package.

[0092] In other embodiments, the step of electroplating at least one side of the carrier board to prepare pads on the side of each conductive boss away from the carrier board may further include:

[0093] First, the first rigid component is pressed onto the side of the release liner away from the carrier plate; wherein, the first rigid component may include a prepreg or other rigid component.

[0094] Based on the position of each conductive boss, holes are drilled in the first rigid member to form through holes that expose each conductive boss.

[0095] Electroplating is performed on the side of the first rigid component away from the carrier plate until all through holes are filled and a first conductive layer is formed on the side of the first rigid component away from the carrier plate; wherein, the thickness of the first conductive layer can be 25±5μm, and the specific thickness can be set according to actual needs, and is not limited here.

[0096] Finally, the first conductive layer is etched based on the position of each conductive bump to form each pad.

[0097] Please see Figure 8 , Figure 8 yes Figure 2 A schematic diagram of another embodiment after the pads are prepared in the example.

[0098] This embodiment is in Figure 4 Based on the implementation method, a first rigid member 109 is pressed onto the side of each conductive boss 103 away from the carrier plate 100. The first rigid member 109 has through holes corresponding to the positions of each conductive boss 103, and conductive elements 111 are formed inside the holes by electroplating. A solder pad 110 is formed on the side of the through hole away from the carrier plate 100 by electroplating. One end of the conductive element 111 contacts the conductive boss 103, and the other end contacts the solder pad 110.

[0099] This embodiment, by adding a first rigid component and correspondingly changing the preparation method of the solder pads, can further enhance the structural rigidity of the package, thereby improving the structural stability and reliability of the package.

[0100] The subsequent preparation steps of the package in this embodiment are the same as those in the previous embodiment. Figure 2 The implementation methods are the same; please refer to the previous text, and will not be repeated here.

[0101] Please see Figure 9 , Figure 9 This is a schematic diagram of a package embodiment provided by the present invention. This embodiment is illustrated using a single-chip package as an example. When the package is a multi-chip package, its structure is similar and will not be described in detail here.

[0102] The package 200 of this embodiment includes multiple pads, chips 201, connectors 203, and multiple conductive bumps 205. The multiple pads are disposed on the same horizontal plane, including a first pad 204 and a second pad 206. Each chip 201 is mounted on one side of the first pad 204; one end of the connector 203 is electrically connected to the side of the chip 201 away from the first pad 204, and the other end of the connector 203 is electrically connected to one side of the second pad 206; the conductive bumps 205 are electrically connected to the other side of their respective pads.

[0103] That is, one side of the chip 201 is electrically connected to the first pad 204 and the conductive bump 205 in sequence, and the other side is electrically connected to the connector 203, the second pad 206, and the conductive bump 205 in sequence, thereby achieving external connection of the package 200 through the conductive bump 205. The connector 203 of the chip 201 can be electrically connected to multiple second pads 206, thereby leading out multiple electrodes. The specific number can be set based on actual needs and is not limited here.

[0104] The package 200 of this embodiment can be prepared by any of the package preparation methods described above.

[0105] With the above structure, the external and internal pads of the package in this embodiment are formed by electroplating after setting a release liner and exposing conductive bosses on the carrier plate, thereby avoiding the alignment process of the internal and external pads. Precise forming is achieved directly through electroplating, which greatly improves the alignment accuracy between the external and internal pads of the package, enhancing the structural stability and reliability of the package.

[0106] In other embodiments, the package 200 further includes a package layer 202 that encapsulates the chip 201.

[0107] The connector 203 includes a first conductive hole, a second conductive layer, and a second conductive hole. The chip 201 and the corresponding second pad 206 are electrically connected in sequence through the first conductive hole, the second conductive layer, and the second conductive hole.

[0108] The encapsulation layer 202 encapsulates the chip 201, the first conductive hole, the second conductive hole, and the side of the pad. The second conductive layer is attached to one side of the encapsulation layer 202, thereby encapsulating to obtain the package 200.

[0109] In other embodiments, the package 200 further includes a second rigid member 208, which is attached to the side of the package layer 202 away from the conductive protrusion 205 and wraps around the second conductive member to improve the structural rigidity of the package 200 and enhance the stability and reliability of the package 200.

[0110] In other embodiments, the package 200 further includes a solder resist layer 209, which is attached to the side of the second rigid member 208 away from the conductive boss 205 to provide insulation protection for the package 200.

[0111] Please see Figure 10 , Figure 10 This is a schematic diagram of another embodiment of the package provided by the present invention. The package of this embodiment can be constructed using the above-described... Figure 8 The package was prepared using the method described in this embodiment.

[0112] The positions and connections of the chip, connector, second rigid component, solder mask layer, and encapsulation layer in the package 300 of this embodiment are all consistent with... Figure 9 The package 200 in the embodiment is the same, please refer to the previous text, and will not be repeated here.

[0113] The encapsulation body 200 in this embodiment further includes, compared to the previous embodiment, a first rigid member 307.

[0114] The first rigid member 307 is attached to the side of the encapsulation layer 302 away from the connector 303. A through-hole is formed on the first rigid member 307 corresponding to each pad, and a conductive member 308 is formed within the through-hole. One end of each conductive member 308 is electrically connected to the corresponding pad, and the other end of each conductive member 308 is electrically connected to the corresponding conductive boss 305. This achieves electrical connection between the pad and the conductive boss 305.

[0115] At this time, one side of chip 301 is connected to the outside through the first pad 304, conductive element 308 and conductive boss 305, and the other side is connected to the outside through connector 303, second pad 306, conductive element 308 and conductive boss 305.

[0116] With the above structure, the external and internal pads of the package in this embodiment are formed by electroplating after setting a release liner and exposing conductive bosses on the carrier plate, thereby avoiding the alignment process of the internal and external pads. Precise forming is achieved directly through electroplating, which greatly improves the alignment accuracy between the external and internal pads of the package, enhancing the structural stability and reliability of the package.

[0117] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for packaging a package, characterized in that, The encapsulation method of the package includes: A carrier plate with multiple conductive protrusions formed on at least one side is obtained, and a release film is provided on at least one side of the carrier plate, exposing each of the conductive protrusions; wherein the thickness of the release film is the same as the thickness of the conductive protrusions. Electroplating is performed on at least one side of the carrier plate to prepare pads on the side of each conductive bump away from the carrier plate; wherein the pads include a first pad and a second pad; the conductive bumps are used to form the outer pads of the package, and the pads are used to form the inner pads of the package; The chip is mounted onto the side of the first pad away from the carrier board, and the chip is then packaged. A connector is fabricated on the side of the chip away from the carrier board and on the side of the second pad away from the carrier board, and the chip and the second pad are electrically connected through the connector; Remove the carrier plate and the release coating to prepare the package.

2. The packaging method of the package according to claim 1, characterized in that, The step of electroplating at least one side of the carrier plate to prepare pads on the side of each of the conductive bosses away from the carrier plate includes: The first rigid member is pressed onto the side of the release coating away from the carrier plate; Based on the position of each of the conductive protrusions, the first rigid member is drilled to form through holes that expose each of the conductive protrusions. Electroplating is performed on the side of the first rigid member away from the carrier plate until all the through holes are filled and a first conductive layer is formed on the side of the first rigid member away from the carrier plate. The first conductive layer is etched based on the position of each of the conductive bosses to form each of the pads.

3. The packaging method of the package according to claim 1 or 2, characterized in that, The step of mounting the chip onto the side of the first pad away from the carrier board and encapsulating the chip includes: The chip is attached or soldered to the side of each of the first pads away from the carrier board; The chip is packaged to form an encapsulation layer that encapsulates the chip and fills the gap between the chip and the release liner.

4. The packaging method of the package according to claim 3, characterized in that, The step of fabricating a connector on the side of the chip away from the carrier and on the side of the second pad away from the carrier, and electrically connecting the chip and the second pad through the connector, includes: Based on the positions of each chip and each second pad, holes are drilled in the packaging layer from the side away from the carrier board to form first blind holes exposing each chip and second blind holes exposing each second pad; Electroplating is performed on the side of the encapsulation layer away from the carrier plate to fill the first blind hole and the second blind hole to form the first conductive hole and the second conductive hole respectively, and a second conductive layer is formed on the side of the encapsulation layer away from the carrier plate. The second conductive layer is etched, and the second conductive layer between the first conductive hole and the second conductive hole is retained to form the connector.

5. The packaging method of the package according to claim 3, characterized in that, After the step of fabricating a connector on the side of the chip away from the carrier and on the side of the second pad away from the carrier, and electrically connecting the chip and the second pad through the connector, the method further includes: A second rigid member is pressed onto the side of the encapsulation layer away from the carrier plate.

6. The packaging method of the package according to claim 1 or 2, characterized in that, The step of obtaining a carrier plate with multiple conductive protrusions formed on at least one side, and providing a release coating on at least one side of the carrier plate, exposing each of the conductive protrusions, includes: A carrier plate is obtained, and multiple conductive protrusions are prepared on opposite sides of the carrier plate; Release films are provided on opposite sides of the carrier plate, exposing each of the conductive bosses; The step of electroplating at least one side of the carrier plate to prepare pads on the side of each of the conductive bosses away from the carrier plate includes: Electroplating is performed on opposite sides of the carrier plate to prepare pads on the side of each conductive boss away from the carrier plate; The step of removing the carrier plate and the release coating to prepare the package includes: The carrier plate is split into two plates, and the release coating is removed to prepare two packages.

Images