An IGBT device with reverse conduction characteristics and a manufacturing method thereof

Abstract

The present invention discloses an IGBT device with reverse conduction characteristics and a manufacturing method thereof, relating to the field of semiconductor device manufacturing, which includes the following steps: A. Preparation of an epitaxial layer, specifically including providing a semiconductor substrate, forming a first epitaxial layer on the surface of the semiconductor substrate, fabricating a reverse conduction region on the first epitaxial layer, and forming a second epitaxial layer on the first epitaxial layer; B. Preparation of a front-end terminal structure; C. Preparation of a front-end high-density trench MOSFET structure; D. Preparation of a circuit connection layer and a passivation layer; E. Preparation of the back side of the wafer. The present invention does not require a backside lithography process, saving costs, and the backside process reduces the risk of fragmentation. The front-end structure of the present invention can achieve a very high trench density, reducing the degree of wafer warping and enabling the production of high-density trench IGBTs on large wafer sizes.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and particularly to an IGBT device with reverse conduction characteristics and a preparation method thereof. Background Art

[0002] For the back electric field cutoff layer of the existing traditional IGBT, high-energy ion implantation is often used and realized through thermal annealing or laser annealing. For example, when phosphorus or arsenic is used, the implantation depth is 2 - 3 um, and through laser annealing, a depth range of 3 - 6 um and a concentration range of 1e16 - 1e17 / cm-3 can be achieved; when light ions such as protons and helium are used, the implantation depth can be 2 - 40 um, and through thermal annealing, a depth range of 3 - 40 um and a concentration range of 1e16 - 1e17 / cm-3 can be achieved. Such high-energy implantation machine tools have high costs and also have high requirements for annealing, and it is necessary to improve the activation rate as much as possible under the condition of a lower activation temperature.

[0003] For the existing traditional IGBT (RC-IGBT) device with reverse conduction characteristics, a dedicated wafer backside lithography machine is often used. After spin-coating photoresist, exposure and development are carried out, and then an ion implantation method is used to implant trivalent elements (P-type IGBT) or pentavalent elements (N-type IGBT) on the back of the IGBT, and the implanted impurities are thermally activated to form the reverse conduction ability. Such dedicated machine tools have high costs, and when performing complex backside processes on thin wafers, there are high risks of fragmentation and warping. Summary of the Invention

[0004] To solve the defects in the prior art, the purpose of the present invention is to provide a preparation method of an IGBT device with reverse conduction characteristics.

[0005] The purpose of the present invention is achieved through the following technical solutions: A preparation method of an IGBT device with reverse conduction characteristics includes the following steps:

[0006] A. Preparation of an epitaxial layer, specifically including providing a semiconductor substrate, forming a first epitaxial layer on the surface of the semiconductor substrate, fabricating a reverse conduction region on the first epitaxial layer, and forming a second epitaxial layer on the first epitaxial layer;

[0007] B. Preparation of a front terminal structure;

[0008] C. Preparation of a front high-density trench MOSFET structure;

[0009] D. Preparation of a circuit connection layer and a passivation layer;

[0010] E. Preparation of the wafer backside.

[0011] Further, step A specifically includes the following steps:

[0012] S1. A first epitaxial layer is grown on the upper surface of a semiconductor substrate by chemical vapor deposition, and the first epitaxial layer is doped with a trivalent element or a pentavalent element;

[0013] On the first epitaxial layer, photoresist is spin-coated, and the pattern on the mask is defined on the photoresist by exposure using a photolithography machine. Then, ion implantation is performed to obtain a reverse-conducting region. The impurities implanted in the reverse-conducting region include a pentavalent element or a trivalent element, and the implanted impurities are thermally activated to form a reverse-conduction channel of the IGBT device;

[0014] S2. A second epitaxial layer is grown on the first epitaxial layer by chemical vapor deposition, and the second epitaxial layer is doped with a trivalent element or a pentavalent element.

[0015] Further, the first epitaxial layer is a buffer layer, and the second epitaxial layer is a breakdown voltage layer. The polarity of the element doped in the second epitaxial layer is the same as that of the element doped in the first epitaxial layer. The trivalent element includes boron, and the pentavalent elements include arsenic and phosphorus.

[0016] Further, step B specifically includes the following steps:

[0017] S3. Silicon dioxide is deposited on the second epitaxial layer to obtain a thick oxide layer;

[0018] S4. A first photoresist layer is spin-coated on the thick oxide layer, and the circuit pattern on the mask is defined on the first photoresist layer by exposure using a photolithography machine;

[0019] S5. The circuit pattern is transferred to the thick oxide layer by dry etching or wet etching, and the first photoresist layer is removed;

[0020] S6. Ion implantation is performed on the second epitaxial layer to obtain a termination region. The impurities implanted include a trivalent element or a pentavalent element, and the implanted impurities are thermally activated to obtain a termination implantation region; the number of ion implantation times is one or more.

[0021] Further, step C specifically includes the following steps:

[0022] S7. A hard film is fabricated on the upper surface of the second epitaxial layer. The material of the hard film is silicon dioxide, and it is obtained by low-temperature chemical vapor deposition or high-temperature furnace tube process;

[0023] S8. A second photoresist layer is spin-coated on the hard film, and the pattern of high-density trenches on the mask is defined on the second photoresist layer by exposure using a photolithography machine;

[0024] S9. After forming a circuit pattern on the second photoresist layer, transfer the circuit pattern to the hard mask of silicon dioxide by dry etching, and remove the second photoresist layer;

[0025] S10. After forming a circuit pattern on the hard mask, form a plurality of high-density trenches on the second epitaxial layer by dry etching, and remove the hard mask;

[0026] S11. Through a furnace tube thermal oxidation process, grow a sacrificial oxide layer on the sidewalls of the trenches;

[0027] S12. Remove the sacrificial oxide layer by wet etching, and then grow a gate oxide layer through a high-temperature furnace tube thermal oxidation process;

[0028] S13. Deposit a layer of polysilicon on the high-density trenches and above the second epitaxial layer by low-pressure chemical vapor deposition;

[0029] S14. Spin-coat a third photoresist layer on the polysilicon, define the trench pattern on the mask on the third photoresist layer by exposure with a lithography machine, and use dry etching to transfer the trench pattern to the polysilicon, and then remove the third photoresist layer;

[0030] S15. Fabricate a body region and a dicing channel implantation region by performing body region ion implantation on the second epitaxial layer. The impurities implanted include trivalent elements or pentavalent elements, and perform thermal activation on the implanted impurities;

[0031] S16. Spin-coat a fourth photoresist layer on the upper surface of the epitaxial wafer, and define the active region pattern on the mask on the fourth photoresist layer by exposure with a lithography machine, so as to form the active region pattern;

[0032] S17. Fabricate an active region by performing active region implantation on the second epitaxial layer. The impurities implanted include trivalent elements or pentavalent elements, and perform thermal activation on the implanted impurities;

[0033] S18. Grow a silicon dioxide insulating layer on the surface of the epitaxial wafer.

[0034] Further, the high-density trenches in step S10 include a plurality of cell active trenches, cell dummy trenches, and dicing channel trenches. The cell active trenches and cell dummy trenches are located in the middle, and the dicing channel trenches are located on both sides;

[0035] The cell dummy trenches include cell floating dummy trenches, cell source dummy trenches, and cell gate dummy trenches.

[0036] Further, the step D specifically includes the following steps:

[0037] S19. Spin-coat a fifth photoresist layer on the surface of the silicon dioxide insulating layer, and define the contact hole pattern on the mask plate on the fifth photoresist layer through exposure by a lithography machine; the contact holes include gate contact holes, emitter contact holes, and terminal contact holes;

[0038] S20. After the gate contact holes, emitter contact holes, and terminal contact hole patterns are formed on the fifth photoresist layer, transfer the patterns to the silicon dioxide by dry etching;

[0039] S21. Dope high-concentration impurities into the bottoms of the gate contact holes, emitter contact holes, and terminal contact holes by ion implantation, and anneal to activate the impurities to fabricate an ohmic contact layer;

[0040] S22. Deposit metal titanium as a bonding layer by chemical vapor deposition, form a silicide by rapid thermal annealing, then deposit metal tungsten isotropically, and remove the metal tungsten outside the contact holes by dry etching to form tungsten plugs;

[0041] S23. Deposit metal by sputtering, spin-coat a sixth photoresist layer, form a circuit connection layer by dry or dry-wet mixing after exposure, and remove the sixth photoresist layer;

[0042] S24. Deposit a passivation layer, and open the pad area through photolithography and etching processes.

[0043] Further, the step E specifically includes the following steps:

[0044] S25. Thin the back silicon substrate of the IGBT device until it is thinned to the first epitaxial layer;

[0045] S26. Inject a trivalent or pentavalent element with low energy and low dose into the back of the IGBT device by ion implantation, with the energy range of 10 - 40 k and the dose range of 1e12 - 1e13 / cm2, and form a collector and a reverse conduction channel after activation; the polarity of the reverse conduction channel after activation is opposite to that of the collector;

[0046] S27. Alloy the back of the IGBT device by evaporation or sputtering, and achieve ohmic contact after annealing to form back metal.

[0047] An IGBT device with reverse conduction characteristics, and the IGBT device with reverse conduction characteristics is prepared according to the preparation method of the IGBT device with reverse conduction characteristics.

[0048] Further, the device includes a terminal region, a dicing channel region, and an active region, and a plurality of trench structures are provided in the dicing channel region and the active region.

[0049] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0050] (1) The IGBT device with reverse conduction characteristics of the present invention does not require a backside lithography process, saving costs;

[0051] (2) The formation of the back buffer layer of the IGBT device of the present invention does not require high-energy implantation and annealing, reducing the risk of fragmentation brought by this process step during the backside process;

[0052] (3) The depth and concentration of the back buffer layer of the IGBT device of the present invention can be easily adjusted. Therefore, both the back injection efficiency and the transport coefficient of the IGBT can be adjusted, enabling different turn-off characteristics to meet the requirements of different application scenarios.

[0053] (4) The front structure of the device of the present invention can achieve a very high trench density. Different front-side technologies, including injection enhancement, carrier storage, etc., can be adopted without increasing the process cost, and the capacitance composition ratio of the device of the present invention can be easily adjusted to meet the requirements of different application scenarios;

[0054] (5) The IGBT device of the present invention adds the same trench structure as the active region in the scribe lane, reducing the degree of wafer warping and enabling the production of high-density trench IGBTs on large wafer sizes. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0056] Figure 1 is a top view of an IGBT device with reverse conduction characteristics;

[0057] Figure 2 is a processing schematic diagram of specific step S1 in step A of a method for manufacturing an IGBT device with reverse conduction characteristics;

[0058] Figure 3 is a processing schematic diagram of specific step S2 in step A of a method for manufacturing an IGBT device with reverse conduction characteristics;

[0059] Figure 4 is a processing schematic diagram of specific step S3 in step B of a method for manufacturing an IGBT device with reverse conduction characteristics;

[0060] Figure 5 is a processing schematic diagram of specific step S4 in step B of a method for manufacturing an IGBT device with reverse conduction characteristics;

[0061] Figure 6 Schematic diagram of the processing of specific step S5 in step B of a preparation method for an IGBT device with reverse conduction characteristics;

[0062] Figure 7 Schematic diagram of the processing of specific step S6 in step B of a preparation method for an IGBT device with reverse conduction characteristics;

[0063] Figure 8 Schematic diagram of the processing of specific step S7 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0064] Figure 9 Schematic diagram of the processing of specific step S8 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0065] Figure 10 Schematic diagram of the processing of specific step S9 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0066] Figure 11 Schematic diagram of the processing of specific step S10 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0067] Figure 12 Schematic diagram of the processing of specific step S11 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0068] Figure 13 Schematic diagram of the processing of specific step S12 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0069] Figure 14 Schematic diagram of the processing of specific step S13 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0070] Figure 15 Schematic diagram of the processing of specific step S14 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0071] Figure 16 Schematic diagram of the processing of specific step S15 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0072] Figure 17 Schematic diagram of the processing of specific step S16 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0073] Figure 18 Schematic diagram of the processing of specific step S17 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0074] Figure 19 Schematic diagram of the processing of specific step S18 in step C of a preparation method for an IGBT device with reverse conduction characteristics;

[0075] Figure 20 Schematic diagram of the processing of specific step S19 in step D of a preparation method for an IGBT device with reverse conduction characteristics;

[0076] Figure 21 Schematic diagram of the processing of specific step S20 in step D of a preparation method for an IGBT device with reverse conduction characteristics;

[0077] Figure 22 Schematic diagram of the processing of specific step S21 in step D of a preparation method for an IGBT device with reverse conduction characteristics;

[0078] Figure 23 Schematic diagram of the processing of specific step S22 in step D of a preparation method for an IGBT device with reverse conduction characteristics;

[0079] Figure 24 Schematic diagram of the processing of specific step S23 in step D of a preparation method for an IGBT device with reverse conduction characteristics;

[0080] Figure 25 Schematic diagram of the processing of specific step S24 in step E of a preparation method for an IGBT device with reverse conduction characteristics;

[0081] Figure 26 Schematic diagram of the processing of specific step S25 in step E of a preparation method for an IGBT device with reverse conduction characteristics;

[0082] Figure 27 Schematic diagram of the processing of specific step S26 in step E of a preparation method for an IGBT device with reverse conduction characteristics;

[0083] Figure 28 Schematic diagram of the processing of specific step S27 in step E of a preparation method for an IGBT device with reverse conduction characteristics;

[0084] Figure 29 For Figure 1 the schematic cross-sectional view along A-A;

[0085] Reference numerals:

[0086] 1. Silicon substrate; 2. First epitaxial layer; 201. Reverse conduction region; 3. Second epitaxial layer; 4. Thick oxide layer; 5. First photoresist layer; 6. Terminal region; 7. Hard mask; 8. Second photoresist layer; 9. Cell active trench; 10. Cell floating dummy trench; 101. Cell source dummy trench; 102. Cell gate dummy trench; 11. Dicing street trench; 12. Sacrificial oxide layer; 13. Gate oxide layer; 14. Polysilicon; 15. Third photoresist layer; 16. Body region; 161. Terminal implantation region; 162. Dicing street implantation region; 17. Fourth photoresist layer; 18. Active region; 19. Insulating layer; 20. Fifth photoresist layer; 21. Gate contact hole; 211. Ohmic contact layer; 22. Emitter contact hole; 23. Terminal contact hole; 24. Metal; 241. Terminal metal mask; 25. Sixth photoresist layer; 26. Gate; 27. Emitter; 28. Passivation layer; 29. Collector; 291. Reverse conduction channel; 30. Back metal; 31. Dicing street region; 32. Active region. Detailed implementation manners

[0087] The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. For those of ordinary skill in the art, without departing from the concept of the present invention, several changes and improvements can still be made, and these all belong to the protection scope of the present invention. In the ranges disclosed herein, the endpoints and any values are not limited to the exact ranges or values. These ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed herein. The present invention will be described in detail below in conjunction with specific embodiments:

[0088] An embodiment of the present invention provides a method for manufacturing an IGBT device with reverse conduction characteristics as shown in Figure 1 , Figure 29 . In a specific embodiment, this method is used to reduce the risks of chips and warping during the manufacturing process of an IGBT device with reverse conduction characteristics, and specifically includes the following steps:

[0089] Step A: Preparation of the epitaxial layer, specifically including providing a semiconductor substrate, forming a first epitaxial layer 2 on the surface of the semiconductor substrate, fabricating a reverse conduction region 201 on the first epitaxial layer 2, and forming a second epitaxial layer 3 on the first epitaxial layer 2.

[0090] Step B: Preparation of the front-end terminal structure.

[0091] Step C: Preparation of the front-end high-density trench MOSFET structure.

[0092] Step D, preparation of the circuit connection layer and the passivation layer 28.

[0093] Step E, preparation of the back side of the wafer.

[0094] As a specific implementation manner, step A may specifically include:

[0095] Step S1, as Figure 2 shown, grow the first epitaxial layer 2 on the upper surface of the semiconductor substrate by means of vapor deposition as the buffer layer of the device described in the present invention. In this embodiment, the semiconductor substrate is specifically a silicon substrate 1. According to the different polarities of the devices, trivalent elements (boron) can be selected for doping to prepare P-type devices or pentavalent elements (arsenic, phosphorus) for doping to prepare N-type devices.

[0096] The thickness and concentration of the first epitaxial layer 2 will vary according to the depth and concentration of the buffer layer required by the application scenario; on the first epitaxial layer 2, photoresist is spin-coated, and the pattern on the mask is defined on the photoresist through the exposure of a lithography machine, and then ion implantation is performed to obtain Figure 2 shown, three reverse conduction regions 201 in the middle of the first epitaxial layer 2, wherein the impurities implanted by ion implantation include pentavalent elements (N-type RC-IGBT) or trivalent elements (P-type RC-IGBT), and the implanted impurities are thermally activated to form the reverse conduction channel of the IGBT device.

[0097] Step S2, as Figure 3 shown, grow the second epitaxial layer 3 on the first epitaxial layer 2 by means of vapor deposition as the voltage withstand layer of the device described in the present invention. According to the different polarities of the devices, trivalent elements (boron) can be selected for doping to prepare P-type devices or pentavalent elements (arsenic, phosphorus) for doping to prepare N-type devices, and the polarity of the doped elements is the same as the polarity of the doping of the first epitaxial layer 2. The depth and concentration of the second epitaxial layer 3 can vary according to the requirements of the application scenario.

[0098] As a specific implementation manner, step B may specifically include:

[0099] Step S3, as Figure 4 shown, deposit silicon dioxide on the second epitaxial layer 3 as the thick oxide layer 4 required for the terminal structure.

[0100] Step S4, as Figure 5 shown, spin-coat the first photoresist layer 5 on the thick oxide layer 4, and define the circuit pattern on the mask on the first photoresist layer 5 through the exposure of a lithography machine.

[0101] Step S5, as Figure 6As shown, the circuit pattern is transferred onto the thick oxide layer 4 by dry or wet etching, and the photoresist is removed. On both sides of the second epitaxial layer 3, a set of two strip-shaped thick oxide layers 4 are obtained respectively.

[0102] Step S6: As Figure 7 shown, the terminal regions 6 are fabricated by ion-implanting the regions of the second epitaxial layer 3 between two sets of two strip-shaped thick oxide layers 4 respectively (as Figure 29 shown). The impurities for ion implantation include trivalent elements (N-type MOSFET) or pentavalent elements (P-type MOSFET). After thermal activation of the implanted impurities, two terminal implanted regions 161 are obtained. In particular, the ion implantation for the terminal implanted regions 161 can be repeated once or multiple times to achieve different breakdown voltages.

[0103] As a specific implementation manner, step C may specifically include:

[0104] Step S7: As Figure 8 shown, a silicon dioxide thin film is deposited on the second epitaxial layer 3 as the hard mask 7 required for trench etching. The hard mask 7 can be prepared by low-temperature chemical vapor deposition or high-temperature furnace tube process.

[0105] Step S8: As Figure 9 shown, a second photoresist layer 8 is spin-coated on the hard mask 7. The pattern of the high-density trenches corresponding to those in step S10 on the mask is defined on the second photoresist layer 8 through exposure by a lithography machine.

[0106] Step S9: As Figure 10 shown, after the circuit pattern is formed on the second photoresist layer 8, the circuit diagram is transferred onto the silicon dioxide hard mask 7 by dry etching, and the second photoresist layer 8 is removed.

[0107] Step S10: As Figure 11 shown, after the circuit pattern is formed on the hard mask 7, high-density trenches are formed on the second epitaxial layer 3 by dry etching, and the hard mask 7 is removed.

[0108] In particular, as a specific implementation manner, this method needs to define three types of trenches simultaneously. The high-density trenches include cell active trenches 9, cell dummy trenches, and dicing channel trenches 11. The cell active trenches 9 and cell dummy trenches are located in the middle, and the dicing channel trenches 11 are located on both sides.

[0109] Two cell active trenches 9 are located in the center of the second epitaxial layer 3 for the conduction effect of the actual transistor. The cell pseudo-trenches include two cell floating pseudo-trenches 10 respectively located on both sides of the cell active trench 9, one cell source pseudo-trench 101 located on the side of the cell floating pseudo-trench 10 away from the cell active trench 9, and one cell gate pseudo-trench 102 located on the side of the cell floating pseudo-trench 10 away from the cell source pseudo-trench 101. By means of selective floating, connection to the gate 26 and the emitter 27, the cell pseudo-trenches can achieve the effects of improving breakdown voltage, capacitance adjustment, and carrier distribution adjustment during conduction. Two groups of dicing channel trenches 11 are respectively located on both sides of the second epitaxial layer 3, and the number of each group of dicing channel trenches 11 is 2, which is beneficial to reducing the warpage degree of large-size wafers. As Figure 1 shown, there are trenches with the same density parallel or perpendicular to the main chip in the dicing channel area 31, so as to achieve high-density trenches.

[0110] Step S11, as Figure 12 shown, using a furnace tube thermal oxidation process, a sacrificial oxide layer 12 is grown on the sidewalls of the high-density trenches.

[0111] Step S12, as Figure 13 shown, through wet etching, the sacrificial oxide layer 12 is removed, and then a gate oxide layer 13 is grown using a high-temperature furnace tube thermal oxidation process.

[0112] Step S13, as Figure 14 shown, a layer of polysilicon 14 is deposited on the high-density trenches and the second epitaxial layer 3 by low-pressure chemical vapor deposition.

[0113] Step S14, as Figure 15 shown, a third photoresist layer 15 is spin-coated on the polysilicon 14, and the trench pattern on the mask is defined on the third photoresist layer 15 as shown in Figure 16 shown by exposure with a lithography machine. After the trench pattern is transferred to the polysilicon 14 by dry etching, the third photoresist layer 15 is removed. In particular, the polysilicon 14 retained by this method can connect the gate 26 trenches together and can also be used as the field plate structure of the terminal region 6.

[0114] Step S15, as Figure 16 shown, by performing ion implantation on the second epitaxial layer 3, the middle body region 16 and the dicing channel implantation regions 162 on both sides are fabricated. The impurities implanted include trivalent elements (N-type MOSFET) or pentavalent elements (P-type MOSFET), and the implanted impurities are thermally activated.

[0115] Step S16, as Figure 17As shown, a fourth photoresist layer 17 is spin-coated on the upper surface of the epitaxial wafer, and the active region 18 pattern on the mask plate is defined on the fourth photoresist layer 17 through exposure by a lithography machine, thereby realizing the active region 18 pattern.

[0116] Step S17: As Figure 18 shown, the active region 18 between two cell active trenches 9 is fabricated by implanting the active region 18 into the second epitaxial layer 3. The impurities implanted by ion implantation include trivalent elements (P-type MOSFET) or pentavalent elements (N-type MOSFET), and the implanted impurities are thermally activated.

[0117] Step S18: As Figure 19 shown, a silicon dioxide insulating layer 19 is grown on the upper surface of the epitaxial wafer.

[0118] As a specific implementation manner, step D may specifically include:

[0119] Step S19: As Figure 20 shown, a fifth photoresist layer 20 is spin-coated on the surface of the silicon dioxide insulating layer 19, and the contact hole pattern on the mask plate is defined on the fifth photoresist layer 20 through exposure by a lithography machine. The contact holes include the gate contact hole 21, the emitter contact hole 22, and the terminal contact hole 23 corresponding to Figure 23 the above.

[0120] Step S20: As Figure 21 shown, after the contact hole pattern is realized on the fifth photoresist layer 20, the pattern is transferred to the silicon dioxide insulating layer 19 by dry etching.

[0121] Step S21: As Figure 22 shown, high-concentration impurities are doped into the bottoms of the gate contact hole 21, the emitter contact hole 22, and the terminal contact hole 23 corresponding to Figure 23 the above by ion implantation, and the impurities are annealed and activated to fabricate the ohmic contact layer 211 of the contact hole.

[0122] Step S22: As Figure 23 shown, a metal titanium is deposited as a bonding layer by chemical vapor deposition, and a silicide is formed by rapid thermal annealing. Subsequently, a metal tungsten is deposited isotropically, and the metal tungsten outside the contact hole is removed by dry etching to form tungsten plugs in the gate contact hole 21, the emitter contact hole 22, and the terminal contact hole 23.

[0123] Step S23: As Figure 24 shown, a metal 24 aluminum is deposited by sputtering, and then a sixth photoresist layer 25 is spin-coated. After exposure, a circuit connection layer is formed by dry or dry-wet mixing methods, and the sixth photoresist layer 25 is removed. In particular, this method defines a terminal metal field plate 241 and two electrodes, one of which is the gate 26 and the other is the emitter 27.

[0124] Step S24: As shown in Figure 25 , deposit a passivation layer 28, and use photolithography and etching processes to open the pad areas of the gate 26 and the emitter 27.

[0125] As a specific implementation, step E may specifically include:

[0126] Step S25: As shown in Figure 26 , thin the back silicon substrate 1 of the IGBT device until it is thinned to within the range of the first epitaxial layer 2.

[0127] Step S26: As shown in Figure 27 , use ion implantation to inject low-energy and low-dose particles into the back of the IGBT device, including trivalent elements (N-type IGBT) or pentavalent elements (P-type IGBT), with an energy range of 10 - 40 k and a dose range of 1e12 - 1e13 / cm2. Activate the implanted impurities, and then form the collector 29 and the reverse conduction channel 291. The reason for the formation of the reverse conduction channel 291 is that the concentration of the reverse conduction region 201 is greater than that of the collector 29. After activation, the polarity of the reverse conduction channel 291 is opposite to that of the collector 29.

[0128] Step S27: As shown in Figure 28 , use evaporation or sputtering to alloy the back of the IGBT device, and perform annealing to achieve ohmic contact and form the back metal 30.

[0129] The embodiment of the present invention also proposes an IGBT device with reverse conduction characteristics. As shown in Figure 1 , Figure 29 , it includes a terminal region 6, a dicing street region 31, and an active region 32. The dicing street region 31 and the active region 32 of the IGBT device are provided with trench structures. Among them, the terminal region 6 can have different repetition times according to different voltage levels; the dicing street region 31 can have different repetition times according to different widths; the active region 32 can have different repetition times according to different current specifications.

[0130] The area of a 12-inch wafer is 2.25 times that of an 8-inch wafer and 4 times that of a 6-inch wafer. Therefore, at the same production efficiency, for a larger wafer, the chip yield increases exponentially. The present invention can alleviate the warping problem when manufacturing IGBT devices on large-size wafers; at the same time, through the present invention, when manufacturing IGBTs with reverse conduction characteristics on large-size wafers, no dedicated exposure machine is required, and the depth and concentration of the buffer layer are easy to adjust. Finally, it is possible to manufacture IGBT devices with reverse conduction characteristics on large-size wafers.

[0131] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for manufacturing an IGBT device with reverse conduction characteristics, characterized in that, It includes the following steps: A. Preparation of the epitaxial layer, specifically including providing a semiconductor substrate, forming a first epitaxial layer (2) on the surface of the semiconductor substrate, fabricating a reverse-conducting region (201) on the first epitaxial layer (2), and forming a second epitaxial layer (3) on the first epitaxial layer (2); B. Preparation of the front-end terminal structure; C. Preparation of the front-end high-density trench MOSFET structure; D. Preparation of the circuit connection layer and the passivation layer (28); E. Preparation of the back surface of the wafer; The step E specifically includes the following steps: S25. Thinning the back semiconductor substrate of the IGBT device until it is thinned to the first epitaxial layer (2); S26. By means of ion implantation, a trivalent element or a pentavalent element with low energy and low dose is implanted into the back surface of the IGBT device, the energy range is 10 - 40 keV, and the dose range is 1e12 - 1e13 / cm 2 After activation, a collector (29) and a reverse conduction channel (291) are formed; after activation, the polarity of the reverse conduction channel (291) is opposite to that of the collector (29); S27. Alloying the back surface of the IGBT device by evaporation or sputtering, and annealing to achieve ohmic contact to form the back metal (30).

2. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 1, characterized in that, The step A specifically includes the following steps: S1. Growing the first epitaxial layer (2) on the upper surface of the semiconductor substrate by chemical vapor deposition, and doping the first epitaxial layer (2) with a trivalent element or a pentavalent element; On the first epitaxial layer (2), spin-coating photoresist, exposing through a lithography machine to define the pattern on the mask on the photoresist, and performing ion implantation to fabricate the reverse-conducting region (201). The impurities implanted in the reverse-conducting region (201) include a pentavalent element or a trivalent element, and thermally activating the implanted impurities to form the reverse-conducting channel of the IGBT device; S2. Growing the second epitaxial layer (3) on the first epitaxial layer (2) by chemical vapor deposition, and doping the second epitaxial layer (3) with a trivalent element or a pentavalent element.

3. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 2, characterized in that The first epitaxial layer (2) is a buffer layer, and the second epitaxial layer (3) is a breakdown voltage layer. The polarity of the element doped in the second epitaxial layer (3) is the same as that of the element doped in the first epitaxial layer (2). The trivalent element includes boron, and the pentavalent elements include arsenic and phosphorus.

4. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 1, characterized in that, The step B specifically includes the following steps: S3. Depositing silicon dioxide on the second epitaxial layer (3) to obtain a thick oxide layer (4); S4. Spin-coating a first photoresist layer (5) on the thick oxide layer (4), and exposing through a lithography machine to define the circuit pattern on the mask on the first photoresist layer (5); S5. Transferring the circuit pattern to the thick oxide layer (4) by dry or wet etching, and removing the first photoresist layer (5); S6. Performing ion implantation on the second epitaxial layer (3) to obtain a terminal region (6). The impurities implanted include a trivalent element or a pentavalent element, and thermally activating the implanted impurities to obtain a terminal implanted region (161). The number of ion implantation times is one or more.

5. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 4, characterized in that, The step C specifically includes the following steps: S7. Fabricating a hard mask (7) on the upper surface of the second epitaxial layer (3). The material of the hard mask (7) is silicon dioxide, which is obtained by low-temperature chemical vapor deposition or high-temperature furnace tube process; S8. Spin-coating a second photoresist layer (8) on the hard mask (7), and exposing through a lithography machine to define the pattern of the high-density trenches on the mask on the second photoresist layer (8); S9. After forming a circuit pattern on the second photoresist layer (8), transfer the circuit pattern to the hard mask (7) of silicon dioxide by dry etching, and remove the second photoresist layer (8); S10. After forming a circuit pattern on the hard mask (7), use dry etching to form a plurality of high-density trenches on the second epitaxial layer (3), and remove the hard mask (7); S11. Through a furnace tube thermal oxidation process, grow a sacrificial oxide layer (12) on the sidewalls of the trenches; S12. Remove the sacrificial oxide layer (12) by wet etching, and then grow a gate oxide layer (13) through a high-temperature furnace tube thermal oxidation process; S13. Deposit a layer of polysilicon (14) on the high-density trenches and above the second epitaxial layer (3) by low-pressure chemical vapor deposition; S14. Spin coat a third photoresist layer (15) on the polysilicon (14), define the trench pattern on the mask on the third photoresist layer (15) by exposure with a lithography machine, and use dry etching to transfer the trench pattern to the polysilicon (14), then remove the third photoresist layer (15); S15. By performing body region (16) ion implantation on the second epitaxial layer (3), obtain a body region (16) and a dicing channel implantation region (162). The impurities implanted include trivalent elements or pentavalent elements, and thermally activate the implanted impurities; S16. Spin coat a fourth photoresist layer (17) on the upper surface of the epitaxial wafer, and define the active region (18) pattern on the mask on the fourth photoresist layer (17) by exposure with a lithography machine, thereby realizing the active region (18) pattern; S17. By performing active region (18) implantation on the second epitaxial layer (3), obtain an active region (18). The impurities implanted include trivalent elements or pentavalent elements, and thermally activate the implanted impurities; S18. Grow a silicon dioxide insulating layer (19) on the surface of the epitaxial wafer.

6. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 5, characterized in that, The high-density trenches described in step S10 include a plurality of cell active trenches (9), cell dummy trenches, and dicing channel trenches (11). The cell active trenches (9) and cell dummy trenches are located in the middle, and the dicing channel trenches (11) are located on both sides; The cell dummy trenches include cell floating dummy trenches (10), cell source dummy trenches (101), and cell gate dummy trenches (102).

7. The manufacturing method of the IGBT device with reverse conduction characteristics according to claim 5, characterized in that, The step D specifically includes the following steps: S19. Spin coat a fifth photoresist layer (20) on the surface of the silicon dioxide insulating layer (19), and define the contact hole pattern on the mask on the fifth photoresist layer (20) by exposure with a lithography machine; the contact holes include gate contact holes (21), emitter contact holes (22), and terminal contact holes (23); S20. After realizing the patterns of the gate contact holes (21), emitter contact holes (22), and terminal contact holes (23) on the fifth photoresist layer (20), transfer the patterns to the silicon dioxide by dry etching; S21. Dope high-concentration impurities into the bottoms of the gate contact holes (21), emitter contact holes (22), and terminal contact holes by ion implantation, and anneal to activate the impurities to fabricate an ohmic contact layer (211); S22: Deposit titanium metal as a bonding layer by chemical vapor deposition, form a silicide using rapid thermal annealing, then deposit tungsten metal isotropically, and remove the tungsten metal outside the contact holes by dry etching to form a tungsten plug. S23: Deposit metal (24) by sputtering, spin-coat a sixth photoresist layer (25), form a circuit connection layer by dry or dry-wet mixing after exposure, and remove the sixth photoresist layer (25). S24: Deposit a passivation layer (28), and open the pad area through photolithography and etching processes.

8. An IGBT device with reverse conduction characteristics, characterized in that, The IGBT device with reverse conduction characteristics is prepared according to the preparation method of the IGBT device with reverse conduction characteristics described in any one of claims 1-7.

9. The IGBT device with reverse conduction characteristics according to claim 8, characterized in that, The device includes a terminal region (6), a dicing street region (31), and an active region (32), and a plurality of trench structures are provided in the dicing street region (31) and the active region (32).

Images