Semiconductor transistor structure with low contact resistance and method of fabrication thereof

Abstract

A semiconductor transistor structure with low contact resistance and a method of fabricating the same are disclosed. The semiconductor transistor structure with low contact resistance includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a two-dimensional electron gas layer located at an interface between the barrier layer and the channel layer, a recess disposed in a contact region, wherein the recess passes through the barrier layer and extends into the channel layer, and an ohmic contact metal disposed in the recess, wherein the ohmic contact metal is in direct contact with a vertical side of the barrier layer in the recess and in direct contact with the two-dimensional electron gas layer and an inclined side of the channel layer in the recess.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor transistor structure with lower contact resistance. BACKGROUND

[0002] Gallium nitride, aluminum nitride, indium nitride and other materials made of nitride semiconductors have wide bandgaps and can be used as high-output electronic devices, such as high electron mobility transistors (HEMTs). HEMTs can achieve high current, high voltage and low on resistance (Ron) operation, and thus are suitable for high-output / high-efficiency amplifiers and high-power switching devices.

[0003] In gallium nitride-based HEMTs (GaN-HEMTs), AlGaN / GaN-HEMTs using gallium nitride as an electron transport layer and aluminum gallium nitride as an electron supply layer have received attention. In AlGaN / GaN-HEMTs, distortion occurs in AlGaN, which originates from the difference in lattice constants between gallium nitride and aluminum gallium nitride. Piezo polarization is generated from the distortion and spontaneous polarization of aluminum gallium nitride, and a high concentration of two-dimensional electron gas (2DEG) can be obtained.

[0004] For the power consumption and heating of the element, the on resistance (Ron) is a very critical factor. The on resistance can be the sum of the drain contact resistance, the drain resistance, the source contact resistance, the source resistance and the channel resistance. As the element size is scaled down, the proportion of the contact resistance (Rc) to the overall on resistance also increases, affecting the operating performance of the element. Therefore, in this technical field, there is still a need for an improved semiconductor transistor structure with lower contact resistance while maintaining high two-dimensional electron gas density. SUMMARY

[0005] The main purpose of the present application is to provide a semiconductor transistor structure and a manufacturing method thereof to solve the above-mentioned problems and shortcomings of the prior art.

[0006] One aspect of the present application provides a semiconductor transistor structure with low contact resistance, comprising: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a two-dimensional electron gas layer located at an interface between the barrier layer and the channel layer; a recess disposed in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an ohmic contact metal disposed in the recess, wherein the ohmic contact metal directly contacts a vertical side of the barrier layer in the recess and directly contacts a slanted side of the two-dimensional electron gas layer and the channel layer in the recess.

[0007] According to an embodiment of the present application, the slanted side is slanted at an angle of 60 degrees to 80 degrees with respect to a horizontal plane.

[0008] According to an embodiment of the present application, the channel layer comprises a gallium nitride layer.

[0009] According to an embodiment of the present application, the barrier layer comprises an aluminum gallium nitride layer.

[0010] According to an embodiment of the present application, the barrier layer further comprises an aluminum nitride layer.

[0011] According to an embodiment of the present application, the semiconductor transistor structure further comprises: a passivation layer disposed on the barrier layer.

[0012] According to an embodiment of the present application, the recess has a depth of 10 nm below a bottom surface of the barrier layer.

[0013] According to an embodiment of the present application, the ohmic contact metal comprises titanium and aluminum.

[0014] Another aspect of the present application provides a semiconductor transistor structure with low contact resistance, comprising: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a two-dimensional electron gas layer located at an interface between the barrier layer and the channel layer; a recess disposed in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an ohmic contact metal disposed in the recess, wherein the ohmic contact metal directly contacts a vertical side of the barrier layer and the two-dimensional electron gas layer in the recess and directly contacts a slanted side of the channel layer in the recess.

[0015] According to an embodiment of the present application, the slanted side is slanted at an angle of 60 degrees to 80 degrees with respect to a horizontal plane.

[0016] According to an embodiment of the present application, the channel layer comprises a gallium nitride layer.

[0017] According to an embodiment of the present application, the barrier layer comprises an aluminum gallium nitride layer.

[0018] According to an embodiment of the present application, the barrier layer further comprises an aluminum nitride layer.

[0019] According to an embodiment of the present application, further comprising: a passivation layer disposed on the barrier layer.

[0020] According to an embodiment of the present application, the recess has a depth of 10 nm below a bottom surface of the barrier layer.

[0021] According to an embodiment of the present application, the ohmic contact metal comprises titanium and aluminum.

[0022] Yet another aspect of the present application discloses a method of forming a semiconductor transistor structure with lower contact resistance, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer, thereby forming a two-dimensional electron gas layer at an interface between the barrier layer and the channel layer; forming a recess in a contact region, wherein the recess passes through the barrier layer and extends into the channel layer, wherein the recess has a vertical sidewall profile in the barrier layer and an angled sidewall profile in the channel layer; and forming an ohmic contact metal in the recess, wherein the ohmic contact metal is in direct contact with the barrier layer, the two-dimensional electron gas layer and the channel layer in the recess.

[0023] According to an embodiment of the present application, the angled sidewall profile in the channel layer comprises a sloped side that is inclined at an angle of 60 degrees to 80 degrees with respect to a horizontal plane.

[0024] According to an embodiment of the present application, the angled sidewall profile is also formed in the two-dimensional electron gas layer.

[0025] According to an embodiment of the present application, the vertical sidewall profile is also formed in the two-dimensional electron gas layer. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1 to 4 A schematic view of a method of forming a semiconductor transistor structure with lower contact resistance according to an embodiment of the present application;

[0027] Figure 5 A schematic view of a semiconductor structure according to another embodiment of the present application;

[0028] Figure 6 A schematic view of an angled sidewall profile also formed in a two-dimensional electron gas layer;

[0029] Figure 7 A schematic view of a vertical sidewall profile also formed in a two-dimensional electron gas layer.

[0030] KEY

[0031] 1 Semiconductor transistor structure

[0032] 100 base

[0033] 110 channel layer

[0034] 110s tilt side

[0035] 120 Barrier Layer

[0036] 120b bottom surface

[0037] 120s vertical side

[0038] 122 aluminum nitride layer

[0039] 130 passivation layer

[0040] 150 ohm contact metal

[0041] 200 contact area

[0042] 2DEG Two-dimensional electron gas

[0043] h Predetermined depth

[0044] HL horizontal plane

[0045] OP1 First Opening

[0046] OP2 Second opening

[0047] PR photoresist pattern

[0048] POP opening

[0049] R groove

[0050] S1 Vertical sidewall profile

[0051] S2 Angled sidewall profile

[0052] θ angle DETAILED DESCRIPTION

[0053] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable one skilled in the art to implement them.

[0054] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0055] Referring to Figures 1 to 4 which is a schematic diagram of a method of forming a semiconductor transistor structure 1 with a low contact resistance according to an embodiment of the present application. First, as shown in Figure 1 , a substrate 100, for example, a sapphire, silicon carbide (SiC), gallium nitride (GaN) or silicon (Si) substrate, but not limited to, is provided. Next, a channel layer 110, for example, the channel layer 110 can include a gallium nitride (GaN) layer, but not limited to, is formed on the substrate 100 in an epitaxial manner. Then, a barrier layer 120, for example, an aluminum gallium nitride (AlGaN) layer, is formed on the channel layer 110 in an epitaxial manner, so as to form a two-dimensional electron gas layer 2DEG at the interface between the barrier layer 120 and the channel layer 110. Next, a passivation layer 130, for example, silicon nitride or silicon oxide, but not limited to, can be formed on the barrier layer 120. A contact region 200 is provided on the substrate 100 for forming a contact electrode.

[0056] The present application is not limited to the above-mentioned stack structure. For example, according to other embodiments of the present application, as shown in Figure 5 , the barrier layer 120 can also include an aluminum nitride layer 122, which is directly located on the channel layer 110.

[0057] As shown in Figure 2 , next, a photoresist pattern PR is formed on the passivation layer 130 with an opening POP exposing the contact region 200 by a photolithography process, and a first opening OP1 is formed in the passivation layer 130 and the barrier layer 120 in the contact region 200 by an anisotropic dry etching process through the opening POP, the first opening OP1 penetrates through the barrier layer 120, but the above-mentioned etching process is controlled to stop at the surface of the channel layer 110. At this time, the first opening OP1 exposes the vertical side surface 120s of the barrier layer 120.

[0058] Next, as shown in Figure 3 , another etching process is performed to etch the channel layer 110 downward through the first opening OP1 to a predetermined depth h below the bottom surface 120b of the barrier layer 120, for example, the predetermined depth h can be about 10 nm, but not limited to, so as to form a tapered second opening OP2. Wherein, the first opening OP1 and the tapered second opening OP2 constitute a recess R. The recess R penetrates through the barrier layer 120 and extends into the channel layer 110. The recess R is composed of a vertical side wall profile S1 by the vertical side surface 120s of the barrier layer 120 and an angled side wall profile S2 by the inclined side surface 110s of the channel layer 110.

[0059] According to an embodiment of the present invention, for example, the inclined side surface 110s of the channel layer 110 is inclined with respect to a horizontal plane HL at an angle θ between 60 and 80 degrees, preferably between 65 and 75 degrees. Forming the inclined side surface 110s of the channel layer 110 at the angle θ between 60 and 80 degrees can ensure a minimum dangling bond density.

[0060] like Figure 4 As shown, an ohmic contact metal 150 is then formed in the groove R, wherein the ohmic contact metal 150 is in direct contact with the barrier layer 120, the two-dimensional electron gas layer 2DEG, and the channel layer 110 in the groove R. According to an embodiment of the present invention, the ohmic contact metal 150 may include titanium and aluminum. According to an embodiment of the present invention, the ohmic contact metal 150 may include titanium or aluminum, but is not limited thereto.

[0061] like Figure 6 As shown, according to an embodiment of the present invention, the angled sidewall profile S2 is also formed in the two-dimensional electron gas layer 2DEG.

[0062] like Figure 7 As shown, according to another embodiment of the present invention, the vertical sidewall profile S1 is also formed in the two-dimensional electron gas layer 2DEG. In this example, the ohmic contact metal 150 is in direct contact with the barrier layer 120 in the groove R and the vertical side surface 120s of the two-dimensional electron gas layer 2DEG, and is also in direct contact with the inclined side surface 110s of the channel layer 110 in the groove R.

[0063] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor transistor structure with low contact resistance, characterized in that: Include: substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on the channel layer; a two-dimensional electron gas layer located at the interface between the barrier layer and the channel layer; a groove provided in the contact region, wherein the groove passes through the barrier layer and extends into the channel layer; as well as An ohmic contact metal is arranged in the groove, wherein the ohmic contact metal is in direct contact with the vertical side surface of the barrier layer in the groove, and is in direct contact with the inclined side surfaces of the two-dimensional electron gas layer and the channel layer in the groove, the inclined side surfaces are inclined at an angle of 60 to 80 degrees to the horizontal plane, and the portion of the groove located in the two-dimensional electron gas layer and the channel layer has a profile that tapers from top to bottom.

2. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: The two-dimensional electron gas layers directly contact the ohmic contact metal at opposite sides of the ohmic contact metal.

3. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: The channel layer includes a gallium nitride layer.

4. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: The barrier layer includes an aluminum gallium nitride layer.

5. The semiconductor transistor structure with lower contact resistance according to claim 4, wherein: The barrier layer further includes an aluminum nitride layer.

6. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: Also includes: The passivation layer is disposed on the barrier layer.

7. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: The depth of the groove is 10 nm below the bottom surface of the barrier layer.

8. The semiconductor transistor structure with low contact resistance according to claim 1, wherein: The ohmic contact metal includes titanium and aluminum.

9. A semiconductor transistor structure with low contact resistance, characterized in that: Include: substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on the channel layer; a two-dimensional electron gas layer located at the interface between the barrier layer and the channel layer; a groove provided in the contact region, wherein the groove passes through the barrier layer and extends into the channel layer; as well as An ohmic contact metal is arranged in the groove, wherein the ohmic contact metal is in direct contact with the vertical side surfaces of the barrier layer and the two-dimensional electron gas layer in the groove, and is in direct contact with an inclined side surface of the channel layer in the groove, the inclined side surface is inclined at an angle of 60 to 80 degrees to the horizontal plane, and the portion of the groove located in the channel layer has a profile that tapers from top to bottom.

10. The semiconductor transistor structure with lower contact resistance according to claim 9, wherein: The two-dimensional electron gas layers directly contact the ohmic contact metal at opposite sides of the ohmic contact metal.

11. The semiconductor transistor structure with lower contact resistance according to claim 9, wherein: The channel layer includes a gallium nitride layer.

12. The semiconductor transistor structure with low contact resistance according to claim 9, wherein: The barrier layer includes an aluminum gallium nitride layer.

13. The semiconductor transistor structure with lower contact resistance according to claim 12, wherein: The barrier layer further includes an aluminum nitride layer.

14. The semiconductor transistor structure with low contact resistance according to claim 9, wherein: Also includes: The passivation layer is disposed on the barrier layer.

15. The semiconductor transistor structure with low contact resistance according to claim 9, wherein: The depth of the groove is 10 nm below the bottom surface of the barrier layer.

16. The semiconductor transistor structure with lower contact resistance according to claim 9, wherein: The ohmic contact metal includes titanium and aluminum.

17. A method for forming a semiconductor transistor structure having low contact resistance, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer, thereby forming a two-dimensional electron gas layer at the interface between the barrier layer and the channel layer; forming a groove in the contact region, wherein the groove passes through the barrier layer and extends into the channel layer, wherein the groove has a vertical sidewall profile in the barrier layer and an angled sidewall profile in the channel layer; and An ohmic contact metal is formed in the groove, wherein the ohmic contact metal is in direct contact with the barrier layer, the two-dimensional electron gas layer and the channel layer in the groove, the angled sidewall profile in the channel layer includes an inclined side surface, and the inclined side surface is inclined at an angle of 60 to 80 degrees to a horizontal plane, and the portion of the groove having the angled sidewall profile has a profile that tapers from top to bottom.

18. The method according to claim 17, wherein The two-dimensional electron gas layers directly contact the ohmic contact metal at opposite sides of the ohmic contact metal.

19. The method according to claim 17, wherein The angled sidewall profile is also formed in the two-dimensional electron gas layer.

20. The method according to claim 17, wherein The vertical sidewall profile is also formed in the two-dimensional electron gas layer.

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