Silicon carbide mosfet structure for optimizing short circuit current tolerance

Abstract

The application belongs to the technical field of power semiconductor, and relates to a silicon carbide MOSFET structure, which comprises a metallized drain, a high-doped first-conductivity-type semiconductor substrate, a first-conductivity-type semiconductor epitaxial layer, a second-conductivity-type semiconductor well, a high-doped second-conductivity-type semiconductor ohmic contact region, a high-doped first-conductivity-type semiconductor source contact region, a high-doped first-conductivity-type semiconductor current guide layer, a first-conductivity-type semiconductor JFET region, a metallized source, a gate oxide layer, a Schottky metal region, a polysilicon gate electrode, an oxide layer and an N+ polysilicon short circuit layer. The application adopts a split gate structure, integrates a Schottky contact in the middle of the gate, and sets a current guide layer in the JFET region. With the increase of the drain voltage, the Schottky contact makes the JFET region quickly deplete and clamp off in advance, thereby reducing the saturation current of the device. The current guide layer provides a current path, which can improve the short circuit current resistance of the device and reduce the on-resistance of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a silicon carbide MOSFET structure with optimized short-circuit current withstand capability. Background Technology

[0002] Power semiconductor devices are indispensable fundamental components of modern power electronic systems. Their applications span numerous fields, including power grid systems, medical devices, military facilities, new energy vehicles, home appliances, communication equipment, and smartphones. Silicon carbide, as a representative of third-generation wide-bandgap semiconductors, possesses many excellent properties such as a high critical breakdown electric field, excellent thermal conductivity, and high electron saturation drift velocity. Given the current limitations in significantly improving the performance of silicon-based power semiconductor devices, silicon carbide has become a crucial breakthrough direction for advancing the performance of power semiconductor devices.

[0003] In practical applications of silicon carbide (SiC) power MOSFETs, short-circuit protection design is often crucial. SiC power MOSFETs typically operate under high voltage and high current conditions. If a short circuit occurs, the instantaneous overcurrent surge can damage not only the power device itself but also critical components in the circuit system, such as magnetic elements, resistors, and capacitors. Given these potentially severe consequences, short-circuit protection modules are often designed to protect the entire circuit system when SiC power MOSFETs are used. While short-circuit protection modules can act quickly in a short-circuit state to protect the device, they cannot falsely trigger protection against transient overcurrents under normal operating conditions. This necessitates that the SiC power MOSFET itself possess a certain tolerance to short-duration short-circuit overcurrents before the short-circuit protection module is triggered.

[0004] For silicon carbide (SiC) power MOSFETs, they are generally considered to operate in the saturation region when a short circuit occurs. Therefore, the key to improving the short-circuit characteristics of SiC power MOSFETs is to reduce the current Idsat when operating in the saturation region. One method to improve the short-circuit characteristics is to reduce the gate voltage Vgs during operation. In the saturation region, the saturation current Idsat of a SiC power MOSFET is related to the gate voltage Vgs; the smaller Vgs is, the smaller the saturation current Idsat is, and the better the short-circuit characteristics of the SiC power MOSFET. However, when designing the drive for a SiC power MOSFET, the drive voltage is usually not set too low, as an excessively low drive voltage will increase switching and conduction losses under normal operating conditions. This necessitates reducing the saturation current Idsat while keeping the gate voltage Vgs constant. Another method to improve the short-circuit characteristics is to reduce the doping concentration in the JFET region. A low-doped JFET region causes the device to pinch off earlier, entering the saturation region, and simultaneously achieving a lower saturation current Idsat. However, in the actual manufacturing process of silicon carbide power MOSFET devices, the doping concentration in the JFET region needs to be increased to obtain a smaller specific on-resistance Ron,sp. In summary, there is a contradiction between improving short-circuit characteristics and reducing on-resistance; simultaneously optimizing both is quite challenging. Summary of the Invention

[0005] This invention addresses the problem that existing methods for improving the short-circuit capability of silicon carbide power MOSFET devices by reducing the driving voltage and the doping concentration in the JFET region introduce additional conduction losses and increase the on-resistance of the device. It provides a silicon carbide MOSFET structure that optimizes short-circuit current withstand capability. By introducing a Schottky contact and a current-conducting layer design in the JFET region, the device saturates earlier, thereby achieving a lower saturation current without sacrificing the driving voltage and on-resistance, thus improving the short-circuit withstand capability of the device.

[0006] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0007] A silicon carbide MOSFET structure with optimized short-circuit current withstand capability includes a metallized drain 1, a highly doped first conductivity type semiconductor substrate 2 located above the metallized drain 1, and a first conductivity type semiconductor epitaxial layer 3 located above the highly doped first conductivity type semiconductor epitaxial layer 2. A second conductivity type semiconductor well 4 and a first conductivity type semiconductor JFET region 8 are located on the upper part of the first conductivity type semiconductor epitaxial layer 3. The top of the second conductivity type semiconductor well 4 has a highly doped second conductivity type semiconductor ohmic contact region 5 and a highly doped first conductivity type semiconductor source contact region 6, and the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are completely surrounded by the second conductivity type semiconductor well 4. The first conductivity type semiconductor JFET region 8 is located between the two second conductivity type semiconductor wells 4. Highly doped first conductivity type semiconductor conductive layers 7 are located on both sides of the top of the first conductivity type semiconductor JFET region 8, and the highly doped first conductivity type semiconductor conductive layers 7 are connected to the second conductivity type semiconductor wells 4. The sidewalls of the electrical type semiconductor well 4 are in direct contact; the upper surfaces of the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are in direct contact with the metallized source 9; the upper surface of the region in the second conductivity type semiconductor well 4 without the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 is covered by the gate oxide layer 10, which also covers part of the highly doped first conductivity type semiconductor source contact region 6 and part of the highly doped first conductivity type semiconductor current-conducting layer 7; the Schottky metal region 11 is located on the upper surface of the first conductivity type semiconductor JFET region 8, which covers part of the highly doped first conductivity type semiconductor current-conducting layer 7, and the Schottky metal region 11 is in contact with the side of the gate oxide layer 10; the polysilicon gate electrode 12 is located on the gate oxide layer 10, and the polysilicon gate electrode 12 and the metallized source 9, as well as the polysilicon gate electrode 12 and the Schottky metal region 11, are electrically isolated by the oxide layer 13.

[0008] This invention also provides a second silicon carbide MOSFET structure with optimized short-circuit current withstand capability, comprising a metallized drain 1, a highly doped first conductivity type semiconductor substrate 2 located above the metallized drain 1, and a first conductivity type semiconductor epitaxial layer 3 located above the highly doped first conductivity type semiconductor substrate 2. A second conductivity type semiconductor well 4 and a first conductivity type semiconductor JFET region 8 are located on the upper part of the first conductivity type semiconductor epitaxial layer 3. The top of the second conductivity type semiconductor well 4 has a highly doped second conductivity type semiconductor ohmic contact region 5 and a highly doped first conductivity type semiconductor source contact region 6, and the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are completely surrounded by the second conductivity type semiconductor well 4. The first conductivity type semiconductor JFET region 8 is located between the two second conductivity type semiconductor wells 4. Highly doped first conductivity type semiconductor conductive layers 7 are located on both sides of the top of the first conductivity type semiconductor JFET region 8. The electrical type semiconductor conductive layer 7 is in direct contact with the sidewall of the second conductivity type semiconductor well 4; the upper surfaces of the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are in direct contact with the metallized source 9; the upper surface of the area in the second conductivity type semiconductor well 4 without the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 is covered by the gate oxide layer 10, which also covers part of the highly doped first conductivity type semiconductor source contact region 6 and part of the highly doped first conductivity type semiconductor conductive layer 7; the Schottky metal region 11 is located on the upper surface of the first conductivity type semiconductor JFET region 8, which covers part of the highly doped first conductivity type semiconductor conductive layer 7, and the Schottky metal region 11 is in contact with the side of the gate oxide layer 10; the polysilicon gate electrode 12 is located on the gate oxide layer 10, and the polysilicon gate electrode 12 and the metallized source 9 are electrically isolated by the oxide layer 13;

[0009] When the P+ polysilicon gate electrode 12 is connected to the Schottky metal region 11, an N+ polysilicon short-circuit layer 14 is covered above the Schottky metal region 11. The N+ polysilicon short-circuit layer 14 is connected to the P+ polysilicon gate electrode 12, thereby forming a diode structure between the P+ polysilicon gate electrode 12 and the Schottky metal region 11 to prevent non-ideal conduction of the device in the blocking operation state; the oxide layer 13 covers the polysilicon gate electrode 12 and the N+ polysilicon short-circuit layer 14.

[0010] As a preferred embodiment, the depth of the highly doped first conductivity type semiconductor conductive layer 7 is less than the junction depth of the second conductivity type semiconductor well 4, and simultaneously greater than... Where D is the minimum depth of the highly doped first conductivity type semiconductor conductive layer 7, and q is the electron charge quantity 1.6 × 10⁻¹⁰. -19C, ε s Where is the dielectric constant of silicon carbide, N is the doping concentration in the JFET region, and Vds is the expected operating voltage of the device. This design of the depth of the highly doped first conductivity type semiconductor current-conducting layer 7 ensures that the current passes through from below the current-conducting layer and diffuses into the drift region in all directions, thereby obtaining a small on-resistance, without causing a decrease in the overall breakdown voltage capability of the device due to the current-conducting layer depth exceeding the second conductivity type semiconductor well 4.

[0011] As a preferred method, the doping concentration of highly doped materials is greater than 1E15cm. -3 .

[0012] As a preferred embodiment, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.

[0013] The beneficial effects of this invention are: it effectively improves the short-circuit tolerance of silicon carbide MOSFET devices, protecting the circuit system and preventing other electronic components from failing when a short circuit occurs. It also effectively improves the on-resistance of silicon carbide MOSFET devices, thereby reducing switching losses during operation. Attached Figure Description

[0014] Figure 1 The silicon carbide MOSFET structure with optimized short-circuit current withstand capability according to Embodiment 1 of the present invention operates in the state where the Schottky electrode and the source electrode are connected.

[0015] Figure 2 The silicon carbide MOSFET structure with optimized short-circuit current withstand capability according to Embodiment 2 of the present invention operates in the state where the Schottky electrode and the gate electrode are connected.

[0016] Figure 3 It is a conventional silicon carbide MOSFET structure.

[0017] Figure 4 This is a schematic diagram showing the flow direction of current in the semiconductor current-conducting layer within the JFET region of this invention.

[0018] 1 is a metallized drain, 2 is a highly doped first conductivity type semiconductor substrate, 3 is a first conductivity type semiconductor epitaxial layer, 4 is a second conductivity type semiconductor well, 5 is a highly doped second conductivity type semiconductor ohmic contact region, 6 is a highly doped first conductivity type semiconductor source contact region, 7 is a highly doped first conductivity type semiconductor current-carrying layer, 8 is a first conductivity type semiconductor JFET region, 9 is a metallized source, 10 is a gate oxide layer, 11 is a Schottky metal region, 12 is a polysilicon gate electrode, 13 is an oxide layer, and 14 is an N+ polysilicon short-circuit layer. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Example 1

[0021] like Figure 1 As shown, this embodiment provides a silicon carbide MOSFET structure with optimized short-circuit current withstand capability, including a metallized drain 1, a highly doped first conductivity type semiconductor substrate 2 located above the metallized drain 1, and a first conductivity type semiconductor epitaxial layer 3 located above the highly doped first conductivity type semiconductor substrate 2. A second conductivity type semiconductor well 4 and a first conductivity type semiconductor JFET region 8 are located on the upper part of the first conductivity type semiconductor epitaxial layer 3. The top of the second conductivity type semiconductor well 4 has a highly doped second conductivity type semiconductor ohmic contact region 5 and a highly doped first conductivity type semiconductor source contact region 6, and the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are completely surrounded by the second conductivity type semiconductor well 4. The first conductivity type semiconductor JFET region 8 is located between the two second conductivity type semiconductor wells 4. Highly doped first conductivity type semiconductor conductive layers 7 are located on both sides of the top of the first conductivity type semiconductor JFET region 8. 7 is in direct contact with the sidewall of the second conductivity type semiconductor well 4; the upper surfaces of the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are in direct contact with the metallized source 9; the upper surface of the area in the second conductivity type semiconductor well 4 without the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 is covered by the gate oxide layer 10, which also covers part of the highly doped first conductivity type semiconductor source contact region 6 and part of the highly doped first conductivity type semiconductor current-conducting layer 7; the Schottky metal region 11 is located on the upper surface of the first conductivity type semiconductor JFET region 8, which covers part of the highly doped first conductivity type semiconductor current-conducting layer 7, and the Schottky metal region 11 is in contact with the side of the gate oxide layer 10; the polysilicon gate electrode 12 is located on the gate oxide layer 10, and the polysilicon gate electrode 12 and the metallized source 9, as well as the polysilicon gate electrode 12 and the Schottky metal region 11, are electrically isolated by the oxide layer 13.

[0022] The depth of the highly doped first conductivity type semiconductor conductive layer 7 is less than the junction depth of the second conductivity type semiconductor well 4, and simultaneously greater than... Where D is the minimum depth of the highly doped first conductivity type semiconductor conductive layer 7, and q is the electron charge quantity 1.6 × 10⁻¹⁰. -19 C, ε s Where is the dielectric constant of silicon carbide, N is the doping concentration in the JFET region, and Vds is the expected operating voltage of the device. This design of the depth of the highly doped first conductivity type semiconductor current-conducting layer 7 ensures that the current passes through from below the current-conducting layer and diffuses into the drift region in all directions, thereby obtaining a small on-resistance, without causing a decrease in the overall breakdown voltage capability of the device due to the current-conducting layer depth exceeding the second conductivity type semiconductor well 4.

[0023] Highly doped doping concentration is greater than 1E15cm -3 .

[0024] The first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.

[0025] The working principle of this example is as follows:

[0026] Traditional silicon carbide MOSFET structures, such as Figure 3 As shown. To improve its short-circuit withstand capability, it is necessary to reduce the driving voltage Vgs or reduce the doping concentration in the JFET region to cause the device to pinch off earlier. Reducing the driving voltage Vgs will increase the conduction loss of the device, while reducing the doping concentration in the JFET region will increase the on-resistance. In this embodiment, by adding a Schottky contact in the JFET region, when the drain voltage Vds is low, due to the presence of a highly doped first conductivity type semiconductor conductive layer 7, and the depth of the highly doped first conductivity type semiconductor conductive layer 7 is greater than... The depletion region of the Schottky contact is small, less than the depth of the highly doped first conductivity type semiconductor conductive layer 7. Therefore, the current mainly flows through the highly doped first conductivity type semiconductor conductive layer 7, and the depletion region introduced by the Schottky contact does not significantly increase the on-resistance.

[0027] When a short circuit occurs, under a high drain voltage Vds, the depletion region of the Schottky contact expands rapidly, exceeding the depth of the JFET region. This causes a rapid increase in the device's on-resistance, effectively reducing the saturation current Idsat when the device is on. Since the device operates in the saturation region when a short circuit occurs, the low saturation current Idsat effectively enhances the device's short-circuit capability.

[0028] On the other hand, the depth of the highly doped first conductivity type semiconductor current-conducting layer 7 is smaller than that of the second conductivity type semiconductor well 4, which will not cause a decrease in the reverse breakdown voltage of the device.

[0029] Example 2

[0030] like Figure 2 As shown, this embodiment provides a silicon carbide MOSFET structure with optimized short-circuit current withstand capability, including a metallized drain 1, a highly doped first conductivity type semiconductor substrate 2 located above the metallized drain 1, and a first conductivity type semiconductor epitaxial layer 3 located above the highly doped first conductivity type semiconductor substrate 2. A second conductivity type semiconductor well 4 and a first conductivity type semiconductor JFET region 8 are located on the upper part of the first conductivity type semiconductor epitaxial layer 3. The top of the second conductivity type semiconductor well 4 has a highly doped second conductivity type semiconductor ohmic contact region 5 and a highly doped first conductivity type semiconductor source contact region 6, and the highly doped second conductivity type semiconductor ohmic contact region 5 and the highly doped first conductivity type semiconductor source contact region 6 are completely surrounded by the second conductivity type semiconductor well 4. The first conductivity type semiconductor JFET region 8 is located between the two second conductivity type semiconductor wells 4. The top sides of the first conductivity type semiconductor JFET region 8 have highly doped first conductivity type semiconductor epitaxial layers. The first conductive semiconductor current-conducting layer 7 is in direct contact with the sidewall of the second conductive semiconductor well 4. The upper surfaces of the highly doped second conductive semiconductor ohmic contact region 5 and the highly doped first conductive semiconductor source contact region 6 are in direct contact with the metallized source 9. The upper surface of the region in the second conductive semiconductor well 4 without the highly doped second conductive semiconductor ohmic contact region 5 and the highly doped first conductive semiconductor source contact region 6 is covered by the gate oxide layer 10, which also covers part of the highly doped first conductive semiconductor source contact region 6 and part of the highly doped first conductive semiconductor current-conducting layer 7. The Schottky metal region 11 is located on the upper surface of the first conductive semiconductor JFET region 8, and the Schottky metal region 11 covers part of the highly doped first conductive semiconductor current-conducting layer 7, thereby forming a low-resistance current path in the highly doped first conductive semiconductor current-conducting layer 7 during conduction. The Schottky metal region 11 is in contact with the side of the gate oxide layer 10, the polysilicon gate electrode 12 is located on the gate oxide layer 10, and the polysilicon gate electrode 12 and the metallized source electrode 9 are electrically isolated through the oxide layer 13.

[0031] When the P+ polysilicon gate electrode 12 is connected to the Schottky metal region 11, an N+ polysilicon short-circuit layer 14 is covered above the Schottky metal region 11. The N+ polysilicon short-circuit layer 14 is connected to the P+ polysilicon gate electrode 12, thereby forming a diode structure between the P+ polysilicon gate electrode 12 and the Schottky metal region 11 to prevent non-ideal conduction of the device in the blocking operation state; the oxide layer 13 covers the polysilicon gate electrode 12 and the N+ polysilicon short-circuit layer 14.

[0032] The depth of the highly doped first conductivity type semiconductor conductive layer 7 is less than the junction depth of the second conductivity type semiconductor well 4, and simultaneously greater than... Where D is the minimum depth of the highly doped first conductivity type semiconductor conductive layer 7, and q is the electron charge (1.6 x 10). -19 C), ε s Where is the dielectric constant of silicon carbide, N is the doping concentration in the JFET region, and Vds is the expected operating voltage of the device. This design of the depth of the highly doped first conductivity type semiconductor current-conducting layer 7 ensures that the current passes through from below the current-conducting layer and diffuses into the drift region in all directions, thereby obtaining a small on-resistance, without causing a decrease in the overall breakdown voltage capability of the device due to the current-conducting layer depth exceeding the second conductivity type semiconductor well 4.

[0033] Highly doped doping concentration is greater than 1E15cm -3 .

[0034] The first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.

[0035] The working principle of this embodiment is as follows:

[0036] Based on Example 1, this example constructs a diode structure above the Schottky metal region 11 between highly doped polysilicon of the first conductivity type and highly doped polysilicon of the second conductivity type at the gate. In the forward blocking state, the diode isolates the source potential of the Schottky diode from the gate, thereby preventing the device from turning on due to the increased potential of the Schottky diode under high blocking voltage, which would drive the gate potential connected to it to increase.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A silicon carbide MOSFET structure with optimized short-circuit current withstand capability, comprising a metallized drain (1), a highly doped first conductivity type semiconductor substrate (2) above the metallized drain (1), a first conductivity type semiconductor epitaxial layer (3) above the highly doped first conductivity type semiconductor substrate (2), a second conductivity type semiconductor well (4) and a first conductivity type semiconductor JFET region (8) on the upper part of the first conductivity type semiconductor epitaxial layer (3), and a highly doped second conductivity type semiconductor ohmic contact region (5) and a highly doped first conductivity type semiconductor JFET region (8) on the top of the second conductivity type semiconductor well (4). The first conductive type semiconductor source contact region (6) and the highly doped second conductive type semiconductor ohmic contact region (5) and the highly doped first conductive type semiconductor source contact region (6) are completely surrounded by the second conductive type semiconductor well (4); the first conductive type semiconductor JFET region (8) is located between the two second conductive type semiconductor wells (4); the top two sides of the first conductive type semiconductor JFET region (8) have highly doped first conductive type semiconductor conductive layers (7), and the highly doped first conductive type semiconductor conductive layers (7) are in direct contact with the sidewalls of the second conductive type semiconductor wells (4); the highly doped second conductive type semiconductor source contact region (6) is ...). The upper surfaces of the semiconductor ohmic contact region (5) and the highly doped first conductivity type semiconductor source contact region (6) are in direct contact with the metallized source (9); the upper surface of the region in the second conductivity type semiconductor well (4) without the highly doped second conductivity type semiconductor ohmic contact region (5) and the highly doped first conductivity type semiconductor source contact region (6) is covered by a gate oxide layer (10), which also covers part of the highly doped first conductivity type semiconductor source contact region (6) and part of the highly doped first conductivity type semiconductor current-conducting layer (7); the Schottky metal region (11) is located in the first conductivity type semiconductor On the upper surface of the JFET region (8), the Schottky metal region (11) covers a portion of the highly doped first conductivity type semiconductor conductive layer (7). The Schottky metal region (11) is in contact with the side of the gate oxide layer (10). The polysilicon gate electrode (12) is located above the gate oxide layer (10). The polysilicon gate electrode (12) and the metallized source (9), as well as the polysilicon gate electrode (12) and the Schottky metal region (11), are electrically isolated through the oxide layer (13). The depth of the highly doped first conductivity type semiconductor conductive layer (7) is less than the junction depth of the second conductivity type semiconductor well (4), and greater than... Where D is the minimum depth of the highly doped first conductivity type semiconductor conductive layer (7), and q is the electron charge 1.6 × 10 -19 C, ε s is the dielectric constant of silicon carbide, N is the doping concentration in the JFET region, and Vds is the expected operating voltage of the device.

2. A silicon carbide MOSFET structure with optimized short-circuit current withstand capability, characterized in that, The device includes a metallized drain (1), a highly doped first conductivity type semiconductor substrate (2) located above the metallized drain (1), and a first conductivity type semiconductor epitaxial layer (3) located above the highly doped first conductivity type semiconductor epitaxial layer (2). A second conductivity type semiconductor well (4) and a first conductivity type semiconductor JFET region (8) are located on the upper part of the first conductivity type semiconductor epitaxial layer (3). A highly doped second conductivity type semiconductor ohmic contact region (5) and a highly doped first conductivity type semiconductor source contact region (6) are located on the top of the second conductivity type semiconductor well (4). The highly doped second conductivity type semiconductor ohmic contact region (5) and the highly doped... The first conductivity type semiconductor source contact region (6) is completely surrounded by the second conductivity type semiconductor well (4); the first conductivity type semiconductor JFET region (8) is located between the two second conductivity type semiconductor wells (4); the top two sides of the first conductivity type semiconductor JFET region (8) have highly doped first conductivity type semiconductor current guiding layers (7), and the highly doped first conductivity type semiconductor current guiding layers (7) are in direct contact with the sidewalls of the second conductivity type semiconductor wells (4); the upper surfaces of the highly doped second conductivity type semiconductor ohmic contact region (5) and the highly doped first conductivity type semiconductor source contact region (6) are in direct contact with the metallized source (9); The upper surface of the region of the second conductivity type semiconductor well (4) without highly doped second conductivity type semiconductor ohmic contact region (5) and highly doped first conductivity type semiconductor source contact region (6) is covered by gate oxide layer (10). The gate oxide layer (10) also covers part of the highly doped first conductivity type semiconductor source contact region (6) and part of the highly doped first conductivity type semiconductor current-conducting layer (7). The Schottky metal region (11) is located on the upper surface of the first conductivity type semiconductor JFET region (8). The Schottky metal region (11) covers part of the highly doped first conductivity type semiconductor current-conducting layer (7). The Schottky metal region (11) is in contact with the side of the gate oxide layer (10). The polysilicon gate electrode (12) is located on the gate oxide layer (10). The polysilicon gate electrode (12) and the metallized source electrode (9) are electrically isolated by oxide layer (13). When the P+ polysilicon gate electrode (12) is connected to the Schottky metal region (11), an N+ polysilicon short-circuit layer (14) is covered above the Schottky metal region (11). The N+ polysilicon short-circuit layer (14) is connected to the P+ polysilicon gate electrode (12), thereby forming a diode structure between the P+ polysilicon gate electrode (12) and the Schottky metal region (11) to prevent non-ideal conduction of the device in the blocking operation state. An oxide layer (13) is covered above the polysilicon gate electrode (12) and the N+ polysilicon short-circuit layer (14). The depth of the highly doped first conductivity type semiconductor current-conducting layer (7) is less than the junction depth of the second conductivity type semiconductor well (4), and greater than the junction depth of the first conductivity type semiconductor well (4). Where D is the minimum depth of the highly doped first conductivity type semiconductor conductive layer (7), and q is the electron charge 1.6 × 10 -19 C, ε s is the dielectric constant of silicon carbide, N is the doping concentration in the JFET region, and Vds is the expected operating voltage of the device.

3. A silicon carbide MOSFET structure with optimized short-circuit current withstand capability according to claim 1 or 2, characterized in that: Highly doped doping concentration is greater than 1E15cm -3 .

4. A silicon carbide MOSFET structure with optimized short-circuit current withstand capability according to claim 1 or 2, characterized in that: The first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.

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