A vertical diode device and a method of fabricating the same

Abstract

The application belongs to the technical field of semiconductors, and provides a vertical diode device and a preparation method thereof. The vertical diode device comprises a cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer, an anode metal layer and a P-type doped region. The width of the intrinsic semiconductor layer is less than the width of the N-type semiconductor layer. The P-type doped region is located on the N-type semiconductor layer and is arranged on both sides of the intrinsic semiconductor layer. The thickness of the P-type doped region is less than the thickness of the intrinsic semiconductor layer. By arranging the P-type doped region on both sides of the intrinsic semiconductor layer, the P-type doped region and the intrinsic semiconductor layer form a depletion region, so that the electric field inside the intrinsic semiconductor layer is modulated, the electric field is more uniformly distributed in the intrinsic semiconductor layer, and the reverse breakdown voltage of the diode is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a vertical diode device and a preparation method thereof. BACKGROUND

[0002] PIN diode is a kind of photodiode commonly used in optical communication. As a kind of special microwave semiconductor element, PIN diode is widely used in the design of microwave and radio frequency circuit, and has many excellent characteristics, such as fast switching speed, large controllable power, low loss, high reverse breakdown voltage and the like. In addition, PIN diode can obtain similar short circuit and open circuit whether it is biased in forward direction or reverse direction. Therefore, PIN diode has become an important component in various electronic devices.

[0003] However, the intrinsic semiconductor layer thickness of the existing PIN diode is not easy to improve from the process, which greatly limits the improvement of the reverse breakdown voltage of the PIN diode. SUMMARY

[0004] In order to solve the above technical problems, the embodiments of the present application provide a vertical diode device and a preparation method thereof, which can solve the problem of low reverse breakdown voltage of the existing PIN diode.

[0005] The embodiments of the present application provide a vertical diode device, which comprises:

[0006] A cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer and an anode metal layer are sequentially stacked from bottom to top; wherein the width of the intrinsic semiconductor layer is less than the width of the N-type semiconductor layer.

[0007] A P-type doped region is located on the N-type semiconductor layer and is arranged on both sides of the intrinsic semiconductor layer; wherein the thickness of the P-type doped region is less than the thickness of the intrinsic semiconductor layer.

[0008] In an embodiment, the vertical diode device further comprises:

[0009] A buried oxygen layer is arranged on the P-type doped region and contacts the intrinsic semiconductor layer and the P-type semiconductor layer respectively.

[0010] In an embodiment, the structure of the P-type doped region is symmetrical.

[0011] In an embodiment, the P-type doped region is in a trapezoidal structure, the lower surface of the trapezoidal structure contacts the N-type semiconductor layer, and the area of the lower surface of the trapezoidal structure is greater than the area of the upper surface of the trapezoidal structure.

[0012] In one embodiment, the ladder-shaped structure comprises a plurality of stacked step structures, and a distance between each of the step structures and the N-type semiconductor layer is inversely proportional to a width of each of the step structures.

[0013] In one embodiment, the P-type doped region is a triangular structure, wherein a first straight angle side of the triangular structure is in contact with the N-type semiconductor layer, and a second straight angle side of the triangular structure is in contact with the intrinsic semiconductor layer.

[0014] In one embodiment, a doping concentration of the ladder-shaped structure gradually increases from an upper surface to a lower surface.

[0015] In one embodiment, the ladder-shaped structure comprises a plurality of stacked step structures, and a distance between each of the step structures and the N-type semiconductor layer is inversely proportional to a doping concentration of each of the step structures.

[0016] In one embodiment, a width of the P-type doped region and a width of the intrinsic semiconductor layer are equal to a width of the N-type semiconductor layer.

[0017] A second aspect of the embodiments of the present application provides a preparation method of a vertical diode device, comprising:

[0018] forming a photoresist film on an anode metal layer of a diode device; wherein the diode device comprises a cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer, and an anode metal layer which are sequentially stacked from bottom to top;

[0019] forming a plurality of etching grooves by etching the diode device under the protection of the photoresist film, so as to divide the P-type semiconductor layer into a plurality of P-type semiconductor units and divide the intrinsic semiconductor layer into a plurality of intrinsic semiconductor units;

[0020] filling P-type semiconductor material in the plurality of etching grooves, and etching the P-type semiconductor material to form a P-type doped region; wherein the P-type doped region is located on the N-type semiconductor layer and is arranged on both sides of the intrinsic semiconductor layer; wherein a thickness of the P-type doped region is less than a thickness of the intrinsic semiconductor layer;

[0021] cutting along a center position in the etching grooves to form a plurality of vertical diode devices.

[0022] Compared with the prior art, the embodiment of the present application has the beneficial effect that: in the embodiment, the width of the intrinsic semiconductor layer is smaller than the width of the N-type semiconductor layer, the P-type doped region is arranged on both sides of the intrinsic semiconductor layer, the P-type doped region and the intrinsic semiconductor layer form a depletion region, the electric field in the intrinsic semiconductor layer is modulated, the electric field is more uniformly distributed in the intrinsic semiconductor layer, and the reverse breakdown voltage of the diode is improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structure diagram of a vertical diode device provided by an embodiment of the present application Figure One ;

[0024] Figure 2 is an electric field intensity distribution diagram of a prior vertical diode device

[0025] Figure 3 is a structure diagram of a vertical diode device provided by an embodiment of the present application Figure Two ;

[0026] Figure 4 is an electric field intensity distribution diagram of a vertical diode device provided by an embodiment of the present application

[0027] Figure 5 is a structure diagram of a vertical diode device provided by an embodiment of the present application Figure Three ;

[0028] Figure 6 is a structure diagram of a vertical diode device provided by an embodiment of the present application Figure Four ;

[0029] Figure 7 is a structure diagram of a vertical diode device provided by an embodiment of the present application Figure Five ;

[0030] Figure 8 is a structure diagram of a vertical diode device provided by an embodiment of the present application

[0031] Figure 9 is a structure diagram of a vertical diode device provided by an embodiment of the present application

[0032] Figure 10 is a structure diagram of a vertical diode device provided by an embodiment of the present application

[0033] Figure 11 (a) is a structure diagram of a vertical diode device provided by an embodiment of the present application

[0034] Figure 11 (b) is a schematic view of forming a P-type doped region according to an embodiment of the present application

[0035] Figure 12 (a) is a schematic view of cutting along the center position in the etching trench according to an embodiment of the present application;

[0036] Figure 12 (b) is a schematic view of forming a vertical diode device according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0038] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0039] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0040] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is one or more than one, unless otherwise specifically limited.

[0041] PIN diode is a kind of photodiode commonly used in optical communication. As a kind of special microwave semiconductor element, PIN diode is widely used in the design of microwave and radio frequency circuit, and has many excellent characteristics, such as: fast switching speed, large controllable power, low loss, high reverse breakdown voltage, etc. In addition, PIN diode can be obtained similar to short circuit and open circuit whether it is forward or reverse biased. Therefore, PIN diode has become an important part of various electronic devices.

[0042] However, the thickness of the intrinsic semiconductor layer of the existing PIN diode is difficult to increase in process, which greatly limits the increase of the reverse breakdown voltage of the PIN diode.

[0043] To solve the above technical problems, the embodiments of the present application provide a vertical diode device, as shown in Figure 1 The vertical diode device includes a cathode metal layer 10, an N-type semiconductor layer 20, an intrinsic semiconductor layer 30, a P-type semiconductor layer 40, an anode metal layer 50, and a P-type doped region 60.

[0044] Specifically, the cathode metal layer 10, the N-type semiconductor layer 20, the intrinsic semiconductor layer 30, the P-type semiconductor layer 40, and the anode metal layer 50 are sequentially stacked from bottom to top; wherein the width of the intrinsic semiconductor layer 30 is less than the width of the N-type semiconductor layer 20; the P-type doped region 60 is located on the N-type semiconductor layer 20, and the P-type doped region 60 is arranged on both sides of the intrinsic semiconductor layer 30; wherein the thickness of the P-type doped region 60 is less than the thickness of the intrinsic semiconductor layer 30.

[0045] As shown in Figure 2 The electric field intensity of the existing vertical diode device gradually decreases from the first end to the second end of the intrinsic semiconductor layer 30, resulting in a low breakdown voltage of the device, wherein the first end is the end of the intrinsic semiconductor layer 30 close to the P-type semiconductor layer 40, and the second end is the end of the intrinsic semiconductor layer 30 close to the N-type semiconductor layer 20, as shown in Figure 4 As shown in By arranging the P-type doped region 60 on both sides of the intrinsic semiconductor layer 30, the P-type doped region 60 and the intrinsic semiconductor layer 30 form a depletion region, which can modulate the electric field intensity of the diode and obtain a uniformly distributed electric field, thereby increasing the reverse breakdown voltage of the diode.

[0046] In the embodiment, the thickness of the P-type doped region 60 is less than the thickness of the intrinsic semiconductor layer 30. This is because the electric field intensity of the intrinsic semiconductor layer 30 is still large near the P-type semiconductor layer 40. Therefore, the P-type doped region 60 only needs to be arranged at the position of the intrinsic semiconductor layer 30 where the electric field intensity is small. In this way, the P-type doped region 60 can better form a depletion region with the intrinsic semiconductor layer 30, better modulate the electric field intensity of the diode, and further improve the reverse breakdown voltage of the diode. If the thickness of the P-type doped region 60 is similar to or equal to the thickness of the intrinsic semiconductor layer 30, the depletion region formed by the P-type doped region 60 and the intrinsic semiconductor layer 30 is close to the electric field peak formed between the P-type semiconductor layer 40 and the intrinsic semiconductor layer 30. The electric field peaks of the two regions intersect, resulting in a larger electric field peak and causing the device to break down prematurely. If the thickness of the P-type doped region 60 is much smaller than the thickness of the intrinsic semiconductor layer 30, for example, the thickness of the P-type doped region 60 is less than 1 / 2 of the thickness of the intrinsic semiconductor layer 30, the P-type doped region 60 cannot effectively modulate the electric field intensity of the diode, greatly reducing the gain effect.

[0047] In a specific application, the thickness of the P-type doped region 60 is 2 / 3 of the thickness of the intrinsic semiconductor layer 30. In this way, the P-type doped region 60 can form a depletion region with the intrinsic semiconductor layer 30 to achieve the purpose of uniform distribution of the electric field in the intrinsic semiconductor layer 30, and at the same time, the edge current is gathered to the inside of the device, solving the problem that the current is close to the surface of the device with high dislocation density in the traditional PIN diode, causing premature breakdown and reducing the reverse breakdown voltage.

[0048] In an embodiment, as shown in FIG. 7, the vertical diode device further includes a buried oxide layer 70. Figure 3

[0049] The buried oxide layer 70 is arranged on the P-type doped region 60, and the buried oxide layer 70 is in contact with the intrinsic semiconductor layer 30 and the P-type semiconductor layer 40, respectively.

[0050] In the embodiment, the buried oxide layer 70 is arranged on the P-type doped region 60. For example, the P-type doped region 60 is arranged on both sides of the intrinsic semiconductor layer 30. Correspondingly, the buried oxide layer 70 is arranged on the P-type doped region 60 on both sides of the intrinsic semiconductor layer 30. The buried oxide layer 70 can be filled with a UID (unintentionally doped semiconductor) or air. Since the buried oxide layer is in contact with the intrinsic semiconductor layer 30 and the P-type semiconductor layer 40, respectively, the buried oxide layer can form a depletion region with the P-type semiconductor layer 40 and the intrinsic semiconductor layer 30, respectively, thereby weakening the electric field peak and further improving the reverse breakdown voltage of the device.

[0051] In a specific application, as shown in FIG. 7, the thickness of the buried oxide layer 70 is 1 / 3 of the thickness of the intrinsic semiconductor layer 30. In this way, the buried oxide layer 70 can form a depletion region with the P-type semiconductor layer 40 and the intrinsic semiconductor layer 30, respectively, thereby weakening the electric field peak and further improving the reverse breakdown voltage of the device. Figure 4 ​As shown, by setting the P-type doped region 60 on both sides of the intrinsic semiconductor layer 30, the P-type doped region 60 and the intrinsic semiconductor layer 30 form a depletion region, which modulates the electric field intensity of the diode, so that the electric field intensity distribution in the intrinsic semiconductor layer 30 is more uniform, thereby improving the reverse breakdown voltage of the diode. By setting the buried oxide layer 70 in contact with the intrinsic semiconductor layer 30 and the P-type semiconductor layer 40 respectively, the buried oxide region can weaken the electric field peak, further improve the reverse breakdown voltage of the device, and make the performance of the device more stable.

[0052] In one embodiment, the structure of the P-type doped region 60 is symmetrical.

[0053] In this embodiment, the structure of the P-type doped region 60 is symmetrical, specifically, the P-type doped regions 60 on both sides of the intrinsic semiconductor layer 30 have the same structure, so that the P-type doped regions 60 on both sides of the intrinsic semiconductor layer 30 can form a depletion region with the intrinsic semiconductor layer 30, which can better modulate the electric field in the intrinsic semiconductor layer 30 more uniformly to make the electric field more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0054] In one embodiment, referring to Figure 5 As shown, the P-type doped region 60 has a trapezoidal structure, the lower surface of the trapezoidal structure is in contact with the N-type semiconductor layer 20, and the area of the lower surface of the trapezoidal structure is greater than the area of the upper surface of the trapezoidal structure.

[0055] In this embodiment, the P-type doped region 60 has a trapezoidal structure, specifically, the right-angled side of the trapezoidal structure is in contact with the intrinsic semiconductor layer 30, and the area of the trapezoidal structure is less than the area of the lower surface, for example, the cross-sectional width of the upper surface of the trapezoidal structure is less than the cross-sectional width of the lower surface. Because the electric field intensity in the intrinsic semiconductor gradually decreases from the P-type doped layer to the N-type semiconductor layer 20, the P-type doped region 60 is set to have a trapezoidal structure. Because the P-type doped region 60 has a larger area, its electric field modulation capability for the intrinsic semiconductor layer 30 is stronger. By setting the area of the lower surface of the trapezoidal structure to be greater than the area of the upper surface of the trapezoidal structure, the region with smaller electric field intensity in the intrinsic semiconductor layer 30 can be modulated more strongly, so that the process and materials are saved, and the electric field in the intrinsic semiconductor layer 30 is modulated more uniformly to make the electric field more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0056] In one embodiment, referring to Figure 6 As shown, the trapezoidal structure includes a plurality of stacked step structures 61, and the distance between each step structure 61 and the N-type semiconductor layer 20 is inversely proportional to the width thereof.

[0057] In the embodiment, the distance between each step structure 61 and the N-type semiconductor layer 20 is inversely proportional to the width of the step structure 61. Specifically, the closer the step structure 61 to the N-type semiconductor layer 20, the greater the width of the step structure 61, and the farther the step structure 61 from the N-type semiconductor layer 20, the smaller the width of the step structure 61. Because the electric field intensity inside the intrinsic semiconductor gradually decreases from the P-type doped layer to the N-type semiconductor layer 20, the greater the width of the step structure 61 of the P-type doped region 60, the stronger the electric field modulation capability of the step structure 61 on the intrinsic semiconductor layer 30. The closer the step structure 61 to the N-type semiconductor layer 20, the greater the width of the step structure 61, and the stronger the modulation on the region of the intrinsic semiconductor layer 30 with a smaller electric field intensity. Therefore, the distance between each step structure 61 and the N-type semiconductor layer 20 is inversely proportional to the width of the step structure 61, which can more uniformly modulate the electric field inside the intrinsic semiconductor layer 30, so that the electric field is more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0058] In one embodiment, referring to FIG. 6, the P-type doped region 60 is a triangular structure; wherein the first straight side of the triangular structure is in contact with the N-type semiconductor layer 20, and the second straight side of the triangular structure is in contact with the intrinsic semiconductor layer 30. Figure 7

[0059] In the embodiment, the P-type doped region 60 is a triangular structure. Specifically, the closer the P-type doped region 60 to the N-type semiconductor layer 20, the greater the width of the P-type doped region 60, and the farther the P-type doped region 60 from the N-type semiconductor layer 20, the smaller the width of the P-type doped region 60. Because the electric field intensity inside the intrinsic semiconductor gradually decreases from the P-type doped layer to the N-type semiconductor layer 20, the P-type doped region 60 is set to be a triangular structure, which can more uniformly modulate the electric field inside the intrinsic semiconductor layer 30, so that the electric field is more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0060] In one embodiment, the doping concentration of the trapezoidal structure gradually increases from the upper surface to the lower surface.

[0061] ​Specifically, the P-type doped region 60 is doped with P-type ion material, the closer the distance between the P-type doped region 60 and the N-type semiconductor layer 20, the greater the doping concentration, the farther the distance between the P-type doped region 60 and the N-type semiconductor layer 20, the smaller the doping concentration, because the electric field strength inside the intrinsic semiconductor gradually decreases from the P-type doped layer to the N-type semiconductor layer 20, the greater the doping concentration of the P-type doped region 60, the stronger the electric field modulation ability of the intrinsic semiconductor layer 30, the closer the distance between the P-type doped region 60 and the N-type semiconductor layer 20, the greater the doping concentration, so that the area with smaller electric field strength in the intrinsic semiconductor layer 30 can be modulated more strongly, therefore, the P-type doped region 60 is set to a trapezoidal structure, and the doping concentration of the trapezoidal structure gradually increases from the upper surface to the lower surface, which can more uniformly modulate the electric field inside the intrinsic semiconductor layer 30, so that the electric field is more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0062] In one embodiment, referring to FIG. 1, the P-type doped region 60 is a rectangular structure. Figure 1 As shown in FIG. 1, the first side of the rectangular structure is in contact with the N-type semiconductor layer 20, and the second side of the rectangular structure is in contact with the intrinsic semiconductor layer 30, by setting the P-type doped region 60 to a rectangular structure, the P-type doped region 60 and the intrinsic semiconductor layer 30 can better form a depletion region, and the electric field inside the intrinsic semiconductor layer 30 can be more uniformly modulated, so that the electric field is more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0063] In one embodiment, referring to FIG. 1, the P-type doped region 60 is a trapezoidal structure. Figure 6 As shown in FIG. 1, the trapezoidal structure includes a plurality of stacked step structures 61, and the distance between each step structure 61 and the N-type semiconductor layer 20 is inversely proportional to the doping concentration thereof.

[0064] In this embodiment, the distance between each step structure 61 and the N-type semiconductor layer 20 is inversely proportional to the doping concentration thereof, specifically, the closer the distance between the step structure 61 and the N-type semiconductor layer 20, the greater the doping concentration of the step structure 61, and the farther the distance between the step structure 61 and the N-type semiconductor layer 20, the smaller the doping concentration of the step structure 61, because the electric field strength inside the intrinsic semiconductor gradually decreases from the P-type doped layer to the N-type semiconductor layer 20, therefore, the distance between each step structure 61 and the N-type semiconductor layer 20 is set to be inversely proportional to the doping concentration thereof, which can more uniformly modulate the electric field inside the intrinsic semiconductor layer 30, so that the electric field is more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0065] In one embodiment, referring to FIG. 1, the width of the P-type doped region 60 and the width of the intrinsic semiconductor layer 30 are equal to the width of the N-type semiconductor layer 20. Figure 1 As shown in FIG. 1, the width of the P-type doped region 60 and the width of the intrinsic semiconductor layer 30 are equal to the width of the N-type semiconductor layer 20.

[0066] In this embodiment, the sum of the width of the P-type doped region 60 on the N-type semiconductor layer 20 and the width of the intrinsic semiconductor layer 30 is equal to the width of the N-type semiconductor layer 20. This allows the P-type doped region 60 and the intrinsic semiconductor layer 30 to better form a depletion region, and enables more uniform modulation of the electric field inside the intrinsic semiconductor layer 30, resulting in a more uniform distribution of the electric field within the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0067] This application also provides a method for fabricating a vertical diode device, referencing... Figure 8 As shown, the preparation method includes steps S100 to S400.

[0068] In step S100, refer to Figure 9 As shown, a photolithography film is formed on the anode metal layer 50 of the diode device; wherein, the diode device includes a cathode metal layer 10, an N-type semiconductor layer 20, an intrinsic semiconductor layer 30, a P-type semiconductor layer 40 and an anode metal layer 50 stacked sequentially from bottom to top.

[0069] In this embodiment, the diode device includes a cathode metal layer 10, an N-type semiconductor layer 20, an intrinsic semiconductor layer 30, a P-type semiconductor layer 40, and an anode metal layer 50. The diode device can be fabricated by: depositing P-type dopant ions on the upper surface of the intrinsic semiconductor layer 30 to form the P-type semiconductor layer 40, and selectively etching the upper surface of the P-type semiconductor layer 40 to form the anode metal layer 50; depositing N-type dopant ions on the lower surface of the intrinsic semiconductor layer 30 to form the N-type semiconductor layer 20, and etching the lower surface of the N-type semiconductor layer 20 to form the cathode metal layer 10. In this embodiment, the intrinsic semiconductor layer 30 is doped with N-type dopant ions, and the doping is light; for example, the N-type dopant ions can be nitrogen ions or phosphorus ions, and the P-type dopant ions can be aluminum ions.

[0070] In step S200, refer to Figure 10 As shown, the diode device is etched under the protection of the photolithography film to form multiple etching trenches, so as to divide the P-type semiconductor layer 40 into multiple P-type semiconductor units 41 and the intrinsic semiconductor layer 30 into multiple intrinsic semiconductor units 31.

[0071] In this embodiment, multiple etching trenches are located in adjacent anode metal units, adjacent P-type semiconductor units, and adjacent intrinsic semiconductor units, respectively. By forming multiple trenches, preparation is made for filling the trenches with P-type doped ions to form a P-type doped region 60.

[0072] In step S300, the P-type semiconductor material is filled in the plurality of etching grooves, and the P-type semiconductor material is etched to form the P-type doped region 60, as shown in reference Figure 11 (a), and the P-type semiconductor material is etched to form the P-type doped region 60, as shown in reference Figure 11 (b); wherein the P-type doped region 60 is located on the N-type semiconductor layer 20 and is arranged on both sides of the intrinsic semiconductor layer 30; wherein the thickness of the P-type doped region 60 is less than the thickness of the intrinsic semiconductor layer 30.

[0073] In the embodiment, by filling the P-type semiconductor material in the plurality of etching grooves, and etching the P-type semiconductor material to form the P-type doped region 60, the P-type doped region 60 on both sides of the intrinsic semiconductor layer 30 forms a depletion region with the intrinsic semiconductor layer 30, which can better modulate the electric field inside the intrinsic semiconductor layer 30 to make the electric field more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0074] In step S400, the center position of the etching groove is cut, as shown in reference Figure 12 (a), to form a plurality of vertical diode devices, as shown in reference Figure 12 (b).

[0075] In the embodiment, the center position of the etching groove is cut (for example, the cutting line L), which can make a plurality of vertical diode devices at one time, and the performance of diodes made in the same batch is generally similar, which improves the yield of vertical diode and improves the speed of making vertical diode.

[0076] The embodiment of the present application provides a vertical diode device and a preparation method thereof. The vertical diode device comprises a cathode metal layer 10, an N-type semiconductor layer 20, an intrinsic semiconductor layer 30, a P-type semiconductor layer 40, an anode metal layer 50, and a P-type doped region 60. The width of the intrinsic semiconductor layer 30 is less than the width of the N-type semiconductor layer 20. The P-type doped region 60 is located on the N-type semiconductor layer 20 and is arranged on both sides of the intrinsic semiconductor layer 30. The thickness of the P-type doped region 60 is less than the thickness of the intrinsic semiconductor layer 30. By arranging the P-type doped region 60 on both sides of the intrinsic semiconductor layer 30, the P-type doped region 60 forms a depletion region with the intrinsic semiconductor layer 30, thereby modulating the electric field inside the intrinsic semiconductor layer 30 to make the electric field more uniformly distributed in the intrinsic semiconductor layer 30, thereby improving the reverse breakdown voltage of the diode.

[0077] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0078] The units described as separate components may or may not be physically separate, and the components displaying data as units may or may not be physical units, i.e., may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0079] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A vertical diode device, characterized in that, The vertical diode device includes: A cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer, and an anode metal layer are stacked sequentially from bottom to top; wherein the width of the intrinsic semiconductor layer is smaller than the width of the N-type semiconductor layer. A P-type doped region is located on the N-type semiconductor layer and is disposed on both sides of the intrinsic semiconductor layer; wherein the thickness of the P-type doped region is less than the thickness of the intrinsic semiconductor layer.

2. The vertical diode device as described in claim 1, characterized in that, The vertical diode device also includes: A buried oxide layer is disposed on the P-type doped region and is in contact with the intrinsic semiconductor layer and the P-type semiconductor layer, respectively.

3. The vertical diode device as described in claim 1, characterized in that, The structure of the P-type doped region is symmetrical about the intrinsic semiconductor layer.

4. The vertical diode device as described in claim 1, characterized in that, The P-type doped region has a trapezoidal structure, the lower surface of which is in contact with the N-type semiconductor layer, and the area of ​​the lower surface of the trapezoidal structure is greater than the area of ​​the upper surface of the trapezoidal structure.

5. The vertical diode device as described in claim 4, characterized in that, The trapezoidal structure includes multiple stacked stepped structures, and the distance between each stepped structure and the N-type semiconductor layer is inversely proportional to its width.

6. The vertical diode device as described in claim 3, characterized in that, The P-type doped region has a triangular structure; wherein, the first right-angled side of the triangular structure is in contact with the N-type semiconductor layer, and the second right-angled side of the triangular structure is in contact with the intrinsic semiconductor layer.

7. The vertical diode device as described in claim 4, characterized in that, The doping concentration of the trapezoidal structure gradually increases from the upper surface to the lower surface.

8. The vertical diode device as described in claim 4, characterized in that, The trapezoidal structure includes multiple stacked stepped structures, and the distance between each stepped structure and the N-type semiconductor layer is inversely proportional to its doping concentration.

9. The vertical diode device as described in claim 1, characterized in that, The sum of the width of the P-type doped region and the width of the intrinsic semiconductor layer is equal to the width of the N-type semiconductor layer.

10. A method for fabricating a vertical diode device, characterized in that, include: A photolithography film is formed on the anode metal layer of a diode device; wherein the diode device includes a cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer and an anode metal layer stacked sequentially from bottom to top; Under the protection of the photolithography film, the diode device is etched to form multiple etching trenches, so as to divide the P-type semiconductor layer into multiple P-type semiconductor units and the intrinsic semiconductor layer into multiple intrinsic semiconductor units. P-type semiconductor material is filled into the plurality of etching trenches, and the P-type semiconductor material is etched to form P-type doped regions; wherein the P-type doped regions are located on the N-type semiconductor layer and are disposed on both sides of the intrinsic semiconductor layer; wherein the thickness of the P-type doped regions is less than the thickness of the intrinsic semiconductor layer. The vertical diode devices are formed by cutting along the center position of the etched trench.

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