Light-emitting diode epitaxial wafer and preparation method thereof

Abstract

The present invention provides a light-emitting diode epitaxial wafer and a preparation method thereof. The light-emitting diode epitaxial wafer is formed by growing a first sublayer on a Si substrate. Since the first sublayer is a low-temperature InN layer, its rough surface can annihilate some dislocations and reduce the dislocation density. Then, a second sublayer is grown. The second sublayer is a high-temperature InN layer and can fill the first sublayer to make the surface smooth, thereby improving the crystal quality of the InN layer. Finally, an InGaN layer is grown in which the In component gradually decreases along the direction of epitaxial growth. This can reduce the lattice mismatch between the InN layer and the subsequent GaN epitaxial layer, reduce the generation of defects, and ultimately achieve the purpose of improving the crystal quality of the epitaxial layer.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and in particular to a light-emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] Due to its advantages such as low heat generation efficiency, radiation resistance, high breakdown voltage, large electron saturation drift velocity and small dielectric constant, GaN materials have been widely used in electronic devices, light-emitting diodes (LEDs) and semiconductor lasers (LDs), and have become a hot topic of current research. With the development of III-nitride epitaxial growth technology and the advancement of device preparation processes, in order to meet the requirements of high-performance and high-power GaN-based optoelectronic devices and power electronic devices, it is necessary and challenging to prepare higher-quality GaN materials.

[0003] At present, the commonly used substrates for epitaxial growth of GaN films are sapphire (Al2O3), silicon carbide (SiC) and silicon (Si). Among them, epitaxial growth of GaN films on sapphire substrates and silicon carbide substrates is very mature, but they are relatively expensive, especially the high price of silicon carbide substrates, which greatly increases the production cost. Although sapphire substrates are relatively cheap, sapphire itself has poor heat dissipation effect, making it difficult to achieve large-scale epitaxial growth. It is worth noting that although GaN films epitaxially grown on silicon substrates have good thermal conductivity and can achieve large-scale epitaxy, especially 6-inch, 8-inch and 12-inch epitaxial wafers, which can reduce production costs and have great market competitiveness, the lattice mismatch and thermal mismatch of GaN epitaxial layers grown on silicon substrates are large, and the defect density is high. In order to grow high-quality, low-dislocation-density epitaxial wafers, a good substrate material needs to have a good match with the epitaxial material in terms of lattice constant, crystal structure and thermal expansion coefficient.

[0004] In the existing silicon-based GaN LED epitaxial growth process, low-temperature AlN or low-temperature GaN is usually used as a buffer layer between the Si substrate and the GaN epitaxial layer to reduce the lattice mismatch between the substrate and the GaN epitaxial layer, lower the dislocation density, and improve the crystal quality of the epitaxial layer. However, due to the significant differences in the lattice constant (0.5431nm) and bandgap (1.12eV) of silicon and those of GaN and AlN, the crystal quality of the epitaxial layer grown on the low-temperature AlN or low-temperature GaN buffer layer is not high. The lattice constant and bandgap of GaN are 0.3189nm and 3.4eV, respectively, and the lattice constant and bandgap of AlN are 0.3112nm and 6.2eV, respectively. Therefore, it is necessary to find an epitaxial buffer layer with a lattice constant and bandgap that better matches the silicon substrate to further reduce the dislocation density and improve the crystal quality of the epitaxial layer. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a light-emitting diode epitaxial wafer and a preparation method thereof, aiming to solve the problem in the prior art that when the light-emitting diode epitaxial wafer substrate is a Si substrate, the dislocation density in the epitaxial layer is high and the crystal quality is poor.

[0006] According to an embodiment of the present invention, a light-emitting diode epitaxial wafer is characterized by comprising a buffer layer, wherein the buffer layer comprises a first sublayer, a second sublayer, and a third sublayer epitaxially grown in sequence, wherein the first sublayer and the second sublayer are both InN layers, and the third sublayer is an InGaN layer;

[0007] The growth temperature of the first sub-layer is lower than the growth temperature of the second sub-layer, and the In component of the third sub-layer gradually decreases along the direction of epitaxial growth.

[0008] Furthermore, the growth temperature of the first sub-layer is 400-600°C, the growth temperature of the second sub-layer is 600-700°C, and the growth temperature of the third sub-layer is 700-900°C.

[0009] Furthermore, the growth mode of the first sub-layer is a three-dimensional growth mode, and the V / III ratio ranges from 300 to 600.

[0010] Furthermore, the growth mode of the second sub-layer is a two-dimensional growth mode, and the V / III ratio ranges from 30 to 60.

[0011] Furthermore, the In composition of the third sub-layer gradually decreases from 1 to 0 along the direction of epitaxial growth.

[0012] Furthermore, the thickness of the first sub-layer is 10-30 nm, the thickness of the second sub-layer is 20-50 nm, and the thickness of the third sub-layer is 20-30 nm.

[0013] Furthermore, the light-emitting diode epitaxial wafer further includes a substrate, an undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer;

[0014] The buffer layer, the undoped GaN layer, the N-type doped GaN layer, the multi-quantum well layer, the electron blocking layer, the P-type doped GaN layer and the contact layer are epitaxially grown in sequence on the substrate.

[0015] Furthermore, the substrate is a Si substrate.

[0016] According to an embodiment of the present invention, a method for preparing a light-emitting diode epitaxial wafer is characterized in that, when growing a buffer layer of the light-emitting diode epitaxial wafer, the method comprises:

[0017] Using H2 and N2 as carrier gases and introducing sources required for growth, an InN layer is grown at a first preset temperature to prepare a first sublayer of the buffer layer;

[0018] growing an InN layer on the first sublayer at a second preset temperature to prepare a second sublayer of the buffer layer, wherein the first preset temperature is lower than the second preset temperature;

[0019] An InGaN layer is grown on the second sub-layer to prepare the third sub-layer of the buffer layer, wherein the In component of the third sub-layer is controlled to gradually decrease along the direction of epitaxial growth.

[0020] Furthermore, before growing the buffer layer of the light-emitting diode epitaxial wafer, the method further includes:

[0021] Providing a substrate required for epitaxial growth, on which the buffer layer is grown;

[0022] After growing the buffer layer of the light-emitting diode epitaxial wafer, the method further comprises:

[0023] An undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer are epitaxially grown in sequence on the buffer layer.

[0024] Compared with the existing technology: by growing the first sublayer, since the first sublayer is a low-temperature InN layer, its rough surface can annihilate some dislocations and reduce the dislocation density, and then growing the second sublayer, which is a high-temperature InN layer, can fill the first sublayer and make the surface smooth, thereby improving the crystal quality of the InN layer. Finally, growing an InGaN layer in which the In component gradually decreases along the direction of epitaxial growth can reduce the lattice mismatch between the InN layer and the subsequent GaN epitaxial layer, reduce the generation of defects, and ultimately achieve the purpose of improving the crystal quality of the epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the structure of the light-emitting diode epitaxial wafer in the first embodiment of the present invention. DETAILED DESCRIPTION

[0026] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] Example 1

[0030] See also Figure 1 , shown is a light-emitting diode epitaxial wafer in Example 1 of the present invention, including a substrate, and a buffer layer, an undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer epitaxially grown on the substrate in sequence.

[0031] In this embodiment, the substrate is a Si substrate, and the buffer layer is a composite buffer layer. Specifically, the buffer layer includes a first sublayer, a second sublayer, and a third sublayer that are epitaxially grown in sequence, wherein the first sublayer and the second sublayer are both InN layers. It should be noted that the lattice constant of Si is 0.5431 nm, the bandgap width is 1.12 eV, and the bandgap width of InN is 0.7 eV, and the lattice constant is 0.354 nm. It can be found that the lattice constants and bandgap widths of Si and InN are relatively matched, which can reduce dislocations caused by lattice mismatch, thereby improving the crystal quality of the epitaxial layer growth.

[0032] Specifically, during the growth of the first sublayer and the second sublayer, the growth temperature of the first sublayer is lower than the growth temperature of the second sublayer. The purpose of this setting is that, since the first sublayer is grown through a three-dimensional growth mode in a low-temperature environment, the V / III ratio range is 300-600, so that the first sublayer can form a rough surface to annihilate some dislocations and reduce the dislocation density. Then, the second sublayer grown through a two-dimensional growth model in a high-temperature environment is grown on the first sublayer, with a V / III ratio range of 30-60. This can fill the three-dimensionally grown first sublayer and make the surface smooth, thereby obtaining an InN layer with better crystal quality. Among them, the growth temperature of the first sublayer is 400-600°C, and the growth temperature of the second sublayer is 600-700°C.

[0033] Furthermore, after the InN layer is grown, a third sublayer is epitaxially grown on the InN layer. The third sublayer is an InGaN layer. During the growth of the InGaN layer, the In component gradually decreases along the direction of epitaxial growth, which can reduce the lattice mismatch between the InN layer and the subsequent GaN epitaxial layer, reduce the generation of defects, and further improve the crystal quality of the epitaxial layer. The growth temperature of the third sublayer is 700-900°C, and the In component gradually decreases from 1 to 0 along the direction of epitaxial growth.

[0034] In some preferred implementations of this embodiment, the first sublayer is a low-temperature InN layer, and the second sublayer is a high-temperature InN layer. Specifically, the growth temperature of the first sublayer can be 500°C, and the V / III ratio can be 400. The growth temperature of the second sublayer can be 650°C, and the V / III ratio can be 40. The third sublayer is an InGaN layer, wherein the growth temperature of the third sublayer can be 900°C, and the V / III ratio can be 100.

[0035] In some preferred embodiments, the total thickness of the buffer layer is 50-110 nm, the thickness of the first sublayer is 10-30 nm, the thickness of the second sublayer is 20-50 nm, and the thickness of the third sublayer is 20-30 nm.

[0036] On the other hand, this embodiment further provides a method for preparing a light-emitting diode epitaxial wafer, which is used to prepare the light-emitting diode epitaxial wafer in this embodiment. The preparation method includes the following steps:

[0037] Step S11: providing a substrate required for epitaxial growth, and performing high-temperature annealing treatment on the substrate at a temperature of 1000-1200° C. and a pressure of 150-500 Torr in an H 2 atmosphere for 5-10 minutes.

[0038] The substrate is preferably a Si substrate with a (111) crystal orientation.

[0039] Step S12: After annealing is completed, a first sublayer and a second sublayer are sequentially deposited on the Si substrate by MOCVD deposition equipment, wherein the first sublayer is an InN layer grown in a low-temperature environment, and the second sublayer is an InN layer grown in a high-temperature environment. Specifically, the thickness of the first sublayer is 10 to 30 nm, the growth temperature is 400 to 600 ° C, the growth pressure is 200 to 300 torr, and the V / III ratio during growth is in the range of 300 to 600, which is a three-dimensional growth mode. The thickness of the second sublayer is 20 to 50 nm, the growth temperature is 600 to 700 ° C, the growth pressure is 100 to 200 torr, and the V / III ratio during growth is in the range of 30 to 60, which is a two-dimensional growth mode. It should be noted that growing the InN layer in the three-dimensional growth mode and the two-dimensional growth mode in sequence is beneficial to improving the crystal quality of the InN layer.

[0040] After the growth of the second sublayer is completed, the third sublayer is deposited on the second sublayer. The third sublayer is an InGaN layer, and the InGaN layer is a gradient layer in which the In component gradually decreases from high to low along the direction of epitaxial growth. The thickness of the third sublayer is between 20 and 30 nm, the growth temperature is 700 to 900°C, the growth pressure is 100 to 200 torr, and the gradient range of the In component from high to low along the direction of epitaxial growth can be from 1 to 0.

[0041] In this embodiment, trimethylaluminum (TMAl), trimethylgallium or triethylgallium (TMGa or TEGa) and ammonia are used as precursors of group III sources and group V sources, respectively; silane and bismuth magnesium are used as precursors of N-type dopants and P-type dopants, respectively; and nitrogen and hydrogen are used as carrier gases.

[0042] Step S13: growing an undoped GaN layer on the buffer layer at a growth temperature of 1050-1200° C. and a growth pressure of 100-300 Torr.

[0043] Exemplarily, the undoped GaN layer is grown to a thickness of about 1 to 3 μm.

[0044] Step S14: growing an N-type doped GaN layer on the undoped GaN layer at a growth temperature of 1100-1200° C. and a growth pressure of 100-300 Torr.

[0045] For example, the N-type doped GaN layer is a Si-doped GaN layer with a thickness of about 1 to 3 μm and a Si doping concentration of 10 19 cm -3 ~10 20 cm -3 .

[0046] Step S15: growing a multi-quantum well layer on the N-type GaN layer.

[0047] Optionally, the multi-quantum well layer is composed of 5 to 12 periods of InGaN / GaN, wherein the InGaN layer is a well layer and the GaN layer is a barrier layer. Specifically, the thickness of a single InGaN well layer in the multi-quantum well layer is 2 to 4 nm, the growth temperature is 800 to 900° C., and the growth pressure is 100 to 300 torr; the thickness of a single GaN barrier layer in the multi-quantum well layer is 8 to 20 nm, the growth temperature is 900 to 1000° C., and the growth pressure is 100 to 300 torr.

[0048] Step S16: growing an electron blocking layer on the multi-quantum well layer, with the reaction chamber temperature being 950-1100° C. and the growth pressure being 50-100 Torr.

[0049] For example, the electron blocking layer may be an AlGaN layer, the thickness of the AlGaN layer is 20-50 nm, the growth temperature is 950-1100° C., the growth pressure is 50-100 Torr, and the Al composition is 0.1-0.5.

[0050] Step S17: growing a P-type doped GaN layer on the electron blocking layer at a growth temperature of 950-1050° C. and a growth pressure of 100-600 Torr.

[0051] For example, the P-type doped GaN layer is a Mg-doped GaN layer with a thickness of about 30 to 200 nm and a Mg doping concentration of 10 19 cm -3 ~10 20 cm -3 .

[0052] Step S18: growing a GaN contact layer on the P-type doped GaN layer.

[0053] For example, the GaN contact layer may be grown at a temperature of 1000-1100° C., at a pressure of 100-300 Torr, and have a thickness of 10-50 nm.

[0054] Step S19: After the GaN contact layer is grown, the temperature of the reaction chamber is lowered and annealing is performed in a nitrogen atmosphere at a temperature of 650-850° C. for 5-15 minutes. The temperature is then lowered to room temperature, and the epitaxial growth is terminated.

[0055] Example 2

[0056] The second embodiment of the present invention also provides a light-emitting diode epitaxial wafer and a method for manufacturing the same. The light-emitting diode epitaxial wafer and the method for manufacturing the same in this embodiment differ from the light-emitting diode epitaxial wafer and the method for manufacturing the same in the first embodiment in that:

[0057] The thickness of the first sublayer is 20nm, the growth temperature is 500℃, the growth pressure is 300torr, the In component is 1, and the V / III ratio is 400; the thickness of the second sublayer is 50nm, the growth temperature is 650℃, the growth pressure is 100torr, the In component is 1, and the V / III ratio is 40; the thickness of the third sublayer is 30nm, the growth temperature is 900℃, the growth pressure is 100torr, the In component gradually changes from 1 to 0 along the direction of epitaxial growth, and the V / III ratio is 100.

[0058] Example 3

[0059] The third embodiment of the present invention also provides a light-emitting diode epitaxial wafer and a method for manufacturing the same. The light-emitting diode epitaxial wafer and the method for manufacturing the same in this embodiment differ from the light-emitting diode epitaxial wafer and the method for manufacturing the same in the first embodiment in that:

[0060] The thickness of the first sublayer is 20nm, the growth temperature is 550℃, the growth pressure is 300torr, the In component is 1, and the V / III ratio is 400; the thickness of the second sublayer is 50nm, the growth temperature is 700℃, the growth pressure is 100torr, the In component is 1, and the V / III ratio is 40; the thickness of the third sublayer is 30nm, the growth temperature is 950℃, the growth pressure is 100torr, the In component gradually changes from 1 to 0 along the direction of epitaxial growth, and the V / III ratio is 100.

[0061] Example 4

[0062] The fourth embodiment of the present invention also provides a light-emitting diode epitaxial wafer and a method for manufacturing the same. The light-emitting diode epitaxial wafer and the method for manufacturing the same in this embodiment differ from the light-emitting diode epitaxial wafer and the method for manufacturing the same in the first embodiment in that:

[0063] The thickness of the first sublayer is 20nm, the growth temperature is 600℃, the growth pressure is 300torr, the In component is 1, and the V / III ratio is 400; the thickness of the second sublayer is 50nm, the growth temperature is 750℃, the growth pressure is 100torr, the In component is 1, and the V / III ratio is 40; the thickness of the third sublayer is 30nm, the growth temperature is 1000℃, the growth pressure is 100torr, the In component gradually changes from 1 to 0 along the direction of epitaxial growth, and the V / III ratio is 100.

[0064] Example 5

[0065] The fifth embodiment of the present invention also provides a light-emitting diode epitaxial wafer and a method for manufacturing the same. The light-emitting diode epitaxial wafer and the method for manufacturing the same in this embodiment differ from the light-emitting diode epitaxial wafer and the method for manufacturing the same in the first embodiment in that:

[0066] The thickness of the first sublayer is 30nm, the growth temperature is 500℃, the growth pressure is 300torr, the In component is 1, and the V / III ratio is 400; the thickness of the second sublayer is 75nm, the growth temperature is 650℃, the growth pressure is 100torr, the In component is 1, and the V / III ratio is 40; the thickness of the third sublayer is 45nm, the growth temperature is 900℃, the growth pressure is 100torr, the In component gradually changes from 1 to 0 along the direction of epitaxial growth, and the V / III ratio is 100.

[0067] Example 6

[0068] The sixth embodiment of the present invention also provides a light-emitting diode epitaxial wafer and a method for manufacturing the same. The light-emitting diode epitaxial wafer and the method for manufacturing the same in this embodiment differ from the light-emitting diode epitaxial wafer and the method for manufacturing the same in the first embodiment in that:

[0069] The thickness of the first sublayer is 40nm, the growth temperature is 500℃, the growth pressure is 300torr, the In component is 1, and the V / III ratio is 400; the thickness of the second sublayer is 100nm, the growth temperature is 650℃, the growth pressure is 100torr, the In component is 1, and the V / III ratio is 40; the thickness of the third sublayer is 60nm, the growth temperature is 900℃, the growth pressure is 100torr, the In component gradually changes from 1 to 0 along the direction of epitaxial growth, and the V / III ratio is 100.

[0070] Comparative Example 1

[0071] Among them, the comparative example 1 of the present invention also proposes a light-emitting diode epitaxial wafer and a preparation method thereof. The light-emitting diode epitaxial wafer and the preparation method thereof in this embodiment differ from the light-emitting diode epitaxial wafer and the preparation method thereof in Example 1 in that:

[0072] In Comparative Example 1, the buffer layer is an AlN layer, that is, not a composite layer of an InN layer and an InGaN layer. The thickness of the AlN layer is 200 nm, the growth temperature is 1100° C., the growth pressure is 50 torr, and the V / III ratio is 200.

[0073] Please refer to Table 1 below, which shows the parameters corresponding to the above-mentioned Examples 2 to 6 and Comparative Example 1 of the present invention, as well as the corresponding test data under the same parameters.

[0074] Table 1:

[0075]

[0076] In actual applications, corresponding light-emitting diodes were produced using the corresponding preparation methods and parameters of Examples 2 to 6 and Comparative Example 1, respectively. The wavelength, forward / reverse voltage, electroluminescence intensity, and light output power of the light-emitting diodes produced in each example were tested. The test data are shown in Table 2 below. It should be noted that, to ensure the reliability of the verification results, the light-emitting diodes produced in Examples 2 to 6 and Comparative Example 1, except for the above-mentioned parameters, should be identical in all other respects. For example, the preparation processes and parameters of all layers except the buffer layer should remain consistent.

[0077] Table 2:

[0078]

[0079] Combining the data in Tables 1 and 2 above, it can be clearly seen that the embodiment of the present invention adopts a buffer layer composed of a first sublayer, a second sublayer and a third sublayer. At the same time, the first sublayer and the second sublayer are both InN layers, and the third sublayer is an InGaN layer. The growth temperature of the first sublayer is lower than the growth temperature of the second sublayer, and the In component of the third sublayer gradually decreases along the direction of epitaxial growth, which significantly improves the electroluminescence intensity and light output power of the prepared light-emitting diode.

[0080] In summary, the light-emitting diode epitaxial wafer and its preparation method in the embodiment of the present invention grows a first sublayer. Since the first sublayer is a low-temperature InN layer, its rough surface can annihilate some dislocations and reduce the dislocation density. Then, a second sublayer is grown. The second sublayer is a high-temperature InN layer, which can fill the first sublayer and make the surface flat, thereby improving the crystal quality of the InN layer. Finally, an InGaN layer with a gradually decreasing In component along the direction of epitaxial growth is grown, which can reduce the lattice mismatch between the InN layer and the subsequent GaN epitaxial layer, reduce the generation of defects, and ultimately achieve the purpose of improving the crystal quality of the epitaxial layer.

[0081] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that: The buffer layer includes a first sublayer, a second sublayer, and a third sublayer that are sequentially epitaxially grown, wherein the first sublayer and the second sublayer are both InN layers, and the third sublayer is an InGaN layer; The growth temperature of the first sub-layer is lower than the growth temperature of the second sub-layer, and the In component of the third sub-layer gradually decreases along the direction of epitaxial growth; The growth mode of the first sublayer is a three-dimensional growth mode, and the V / III ratio ranges from 300 to 600; The growth mode of the second sublayer is a two-dimensional growth mode, and the V / III ratio ranges from 30 to 60.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The growth temperature of the first sub-layer is 400-600° C., the growth temperature of the second sub-layer is 600-700° C., and the growth temperature of the third sub-layer is 700-900° C.

3. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The In composition of the third sub-layer gradually decreases from 1 to 0 along the direction of epitaxial growth.

4. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the first sublayer is 10-30 nm, the thickness of the second sublayer is 20-50 nm, and the thickness of the third sublayer is 20-30 nm.

5. The light emitting diode epitaxial wafer according to any one of claims 1 to 4, characterized in that: The light-emitting diode epitaxial wafer further includes a substrate, an undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer; The buffer layer, the undoped GaN layer, the N-type doped GaN layer, the multi-quantum well layer, the electron blocking layer, the P-type doped GaN layer and the contact layer are epitaxially grown in sequence on the substrate.

6. The light emitting diode epitaxial wafer according to claim 5, characterized in that: The substrate is a Si substrate.

7. A method for preparing a light-emitting diode epitaxial wafer, characterized in that: For preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, when growing the buffer layer of the light-emitting diode epitaxial wafer, the preparation method comprises: Using H2 and N2 as carrier gases and introducing sources required for growth, an InN layer is grown at a first preset temperature to prepare a first sublayer of the buffer layer; growing an InN layer on the first sublayer at a second preset temperature to prepare a second sublayer of the buffer layer, wherein the first preset temperature is lower than the second preset temperature; An InGaN layer is grown on the second sub-layer to prepare the third sub-layer of the buffer layer, wherein the In component of the third sub-layer is controlled to gradually decrease along the direction of epitaxial growth.

8. The method for preparing a light emitting diode epitaxial wafer according to claim 7, wherein: Before growing the buffer layer of the light emitting diode epitaxial wafer, the method further comprises: Providing a substrate required for epitaxial growth, on which the buffer layer is grown; After growing the buffer layer of the light-emitting diode epitaxial wafer, the method further comprises: An undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer are epitaxially grown in sequence on the buffer layer.

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