A vertical structure LED chip and its preparation method

Abstract

This application discloses a vertically structured LED chip and its fabrication method. The vertically structured LED chip is sequentially provided with a substrate layer, an adhesive layer, a bonding layer, a first barrier layer, an N-electrode layer, an insulating layer, a protective layer, a conductive layer, a second barrier layer, an epitaxial layer, and a P-electrode layer. By providing a conductive layer made of indium tin oxide in the LED chip, the conductivity and transparency of the LED chip are enhanced, and the overall current structure of the LED chip is improved. As a result, an LED lamp based on the vertically structured LED chip according to the embodiment of the present invention has higher luminous flux and better light distribution uniformity. The present invention can be widely applied in the field of semiconductor technology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical structure LED chip and a preparation method thereof. Background Art

[0002] A light-emitting diode (LED) is a solid-state semiconductor device that converts electrical energy into visible light. With the development of the LED industry, high-power LEDs are becoming increasingly popular. Vertically structured LED chips offer advantages such as high current carrying capacity and excellent light output. Consequently, major LED manufacturers are increasingly focusing on the development of vertically structured LED chips. However, current vertically structured LED chip technology remains immature, suffering from low conductivity and luminescence efficiency. Summary of the Invention

[0003] To solve the above technical problems, an embodiment of the present invention provides a vertical structure LED chip and a method for manufacturing the same.

[0004] The technical solution adopted in one aspect of the embodiment of the present invention is:

[0005] A vertical structure LED chip, comprising:

[0006] substrate layer;

[0007] an adhesive layer, disposed on one side of the substrate layer;

[0008] A bonding layer is provided on a side of the adhesive layer away from the substrate layer;

[0009] a first barrier layer, disposed on a side of the bonding layer away from the adhesive layer;

[0010] An N-electrode layer is provided on a side of the first barrier layer away from the bonding layer;

[0011] an insulating layer, disposed on a side of the N-electrode layer away from the first barrier layer;

[0012] a protective layer, disposed on a side of the insulating layer away from the N-electrode layer;

[0013] a conductive layer, disposed on a side of the protective layer away from the insulating layer, wherein the conductive layer is made of indium tin oxide;

[0014] a second barrier layer, disposed on a side of the conductive layer away from the protective layer;

[0015] an epitaxial layer, arranged on a side of the second barrier layer away from the conductive layer, the epitaxial layer comprising a metal reflective layer, a p-GaN layer, a multi-quantum well layer, and an n-GaN layer, wherein the metal reflective layer is arranged on a side of the second barrier layer away from the conductive layer, the p-GaN layer is arranged on a side of the metal reflective layer away from the second barrier layer, the multi-quantum well layer is arranged on a side of the p-GaN layer away from the metal reflective layer, and the n-GaN layer is arranged on a side of the multi-quantum well layer away from the p-GaN layer;

[0016] The P electrode layers are respectively arranged on both sides of the epitaxial layer.

[0017] As an optional implementation manner, a passivation layer is further provided on a side of the epitaxial layer away from the second barrier layer.

[0018] As an optional implementation manner, the metal reflective layer is made of Ag and Ni.

[0019] As an optional embodiment, the first barrier layer and the second barrier layer are made of SiN x And SiO2.

[0020] As an optional implementation manner, the P electrode layer is prepared by using any one of Cr, Ti, Al, Pt and Au.

[0021] As an optional implementation manner, the bonding layer is prepared using any one of Cr, Ni, Sn, Pt and Au.

[0022] As an optional implementation manner, the bonding layer is prepared using any one of Ni, Sn and Au.

[0023] Another aspect of the present invention is to adopt the following technical solutions:

[0024] A method for preparing a vertical structure LED chip comprises the following steps:

[0025] An n-GaN layer, a multi-quantum well layer, a p-GaN layer, and a metal reflective layer are sequentially grown on a silicon substrate to form an epitaxial layer;

[0026] Using a photolithography process to form a mark point and an N-electrode hole pattern on a side of the epitaxial layer away from the silicon substrate, and performing inductively coupled plasma etching on the side of the epitaxial layer away from the silicon substrate based on the mark point and the N-electrode hole pattern, until the etching depth reaches the n-GaN layer;

[0027] forming a second barrier layer on a side of the epitaxial layer away from the silicon substrate;

[0028] A conductive layer is formed on a side of the second barrier layer away from the epitaxial layer, wherein the conductive layer is formed of indium tin oxide;

[0029] preparing a protective layer on a side of the conductive layer away from the second barrier layer;

[0030] An insulating layer, an N-electrode layer, a first barrier layer and a bonding layer are sequentially formed on a side of the protective layer away from the conductive layer;

[0031] preparing a bonding layer on the substrate layer;

[0032] aligning and bonding the adhesive layer and the bonding layer;

[0033] removing the silicon substrate, and roughening the surface of the epitaxial layer from which the silicon substrate is removed;

[0034] P electrode layers are prepared on both sides of the epitaxial layer to complete the preparation of the vertical structure LED chip.

[0035] As an optional embodiment, the preparation method further comprises:

[0036] Fabricating a photolithographic pattern on the vertical structure LED chip;

[0037] The epitaxial layer is corroded based on the photolithography pattern to obtain the light-emitting surface of the vertical structure LED chip.

[0038] As an optional embodiment, the preparation method further comprises:

[0039] A passivation layer is deposited on a side of the epitaxial layer away from the second barrier layer.

[0040] The vertical structure LED chip and its preparation method of the embodiment of the present invention enhance the conductivity and transparency of the LED chip and improve the overall current structure of the LED chip by setting a conductive layer made of indium tin oxide in the LED chip, thereby enabling the LED lamp based on the vertical structure LED chip of the embodiment of the present invention to have higher luminous flux and better light distribution uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a schematic structural diagram of a vertically structured LED chip according to an embodiment of the present invention;

[0042] Figure 2 This is a flow chart of a method for preparing a vertical structure LED chip according to an embodiment of the present invention;

[0043] Figure 3 Schematic diagram of the structure of a vertical structure LED chip in comparative example.

[0044] Figure numerals: 1. substrate layer; 2. adhesive layer; 3. bonding layer; 4. first barrier layer; 5. N-electrode layer; 6. insulating layer; 7. protective layer; 8. conductive layer; 9. second barrier layer; 10. metal reflective layer; 11. p-GaN layer; 12. multi-quantum well layer; 13. n-GaN layer; 14. passivation layer; 15. P-electrode layer. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0046] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order. In addition, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0047] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] Current vertical LED chip technology is still immature, suffering from low conductivity and luminescence. To address this issue, embodiments of the present invention provide a vertical LED chip and its fabrication method. By incorporating a conductive layer made of indium tin oxide into the LED chip, the chip's conductivity and transparency are enhanced, improving the chip's overall current structure. This results in an LED lamp based on the vertical LED chip having higher luminous flux and better light distribution uniformity.

[0049] like Figure 1 As shown, an embodiment of the present invention provides a vertical structure LED chip, and the vertical structure LED chip includes:

[0050] substrate layer 1;

[0051] an adhesive layer 2, disposed on one side of the substrate layer 1;

[0052] The bonding layer 3 is arranged on a side of the adhesive layer 2 away from the substrate layer 1;

[0053] A first barrier layer 4 is provided on a side of the bonding layer 3 away from the adhesive layer 2;

[0054] N-electrode layer 5, arranged on a side of the first barrier layer 4 away from the bonding layer 3;

[0055] an insulating layer 6, disposed on a side of the N-electrode layer 5 away from the first barrier layer 4;

[0056] a protective layer 7, disposed on a side of the insulating layer 6 away from the N-electrode layer 5;

[0057] The conductive layer 8 is provided on a side of the protective layer 7 away from the insulating layer 6, and the conductive layer 8 is made of indium tin oxide;

[0058] a second barrier layer 9, arranged on a side of the conductive layer 8 away from the protective layer 7;

[0059] an epitaxial layer, disposed on a side of the second barrier layer 9 away from the conductive layer 8, wherein the epitaxial layer includes a metal reflective layer 10, a p-GaN layer 11, a multi-quantum well layer 12, and an n-GaN layer 13, wherein the metal reflective layer 10 is disposed on a side of the second barrier layer 9 away from the conductive layer 8, the p-GaN layer 11 is disposed on a side of the metal reflective layer 10 away from the second barrier layer 9, the multi-quantum well layer 12 is disposed on a side of the p-GaN layer 11 away from the metal reflective layer 10, and the n-GaN layer 13 is disposed on a side of the multi-quantum well layer 12 away from the p-GaN layer 11;

[0060] The P-electrode layers 15 are respectively provided on both sides of the epitaxial layer.

[0061] In the embodiment of the present invention, the conductive layer 8 is connected to the protective layer 7 , the second barrier layer 9 and the metal reflective layer 10 .

[0062] The first blocking layer 4 and the second blocking layer 9 are current blocking layers. The second blocking layer 9 is used to isolate the N-electrode layer 5 from the P-electrode layer 15 .

[0063] The protective layer 7 is a BAR protective layer. In one embodiment of the present invention, the protective layer 7 may be a composite structure of Ti, Cr, Au, and Pt, with a thickness of 1000-1500 nm.

[0064] The multi-quantum well layer 12 is an InGaN / GaN multi-quantum well layer.

[0065] As an optional implementation, a passivation layer 14 is further provided on the side of the epitaxial layer away from the second barrier layer 9 .

[0066] As an optional implementation, the metal reflective layer 10 is made of Ag and Ni.

[0067] As an optional embodiment, the first barrier layer 4 and the second barrier layer 9 are made of SiN x And SiO2.

[0068] Optionally, in one embodiment of the present invention, the thickness of the first barrier layer 4 and the second barrier layer 9 is 0.2 μm.

[0069] As an optional implementation manner, the P-electrode layer 15 is made of any one of Cr, Ti, Al, Pt and Au.

[0070] Optionally, in one embodiment of the present invention, the thickness of the P-electrode layer 15 is 3200 nm.

[0071] As an optional embodiment, the bonding layer 2 is prepared by using any one of Cr, Ni, Sn, Pt and Au.

[0072] Optionally, in one embodiment of the present invention, the thickness of the adhesive layer 2 is 1500 nm.

[0073] As an optional implementation manner, the bonding layer 3 is prepared by using any one of Ni, Sn and Au.

[0074] Optionally, in one embodiment of the present invention, the thickness of the bonding layer 3 is 1400 nm.

[0075] based on Figure 1 The embodiment of the present invention provides a method for preparing a vertical structure LED chip, such as Figure 2 As shown, the preparation method includes the following steps S201-S210:

[0076] S201, sequentially growing an n-GaN layer, a multi-quantum well layer, a p-GaN layer, and a metal reflective layer on a silicon substrate to form an epitaxial layer;

[0077] Optionally, in one embodiment of the present invention, the total thickness of the silicon substrate and the epitaxial layer is 2-20 μm.

[0078] S202, using a photolithography process to form a mark point and an N-electrode hole pattern on the side of the epitaxial layer away from the silicon substrate, and performing inductively coupled plasma etching on the side of the epitaxial layer away from the silicon substrate based on the mark point and the N-electrode hole pattern, until the etching depth reaches the n-GaN layer;

[0079] Among them, the mark point is used for process alignment.

[0080] S203, forming a second barrier layer on a side of the epitaxial layer away from the silicon substrate;

[0081] The second barrier layer is used to isolate the P-electrode layer and the N-electrode layer.

[0082] In an embodiment of the present invention, the second barrier layer is deposited by plasma enhanced chemical vapor deposition, wherein the deposition temperature is 200-300° C. and the deposition thickness is 100 nm-300 nm.

[0083] S204, forming a conductive layer on a side of the second barrier layer away from the epitaxial layer;

[0084] Wherein, the conductive layer is prepared by indium tin oxide.

[0085] In an embodiment of the present invention, the conductive layer is deposited and photolithographically etched after patterning the second barrier layer.

[0086] Specifically, a photolithography process is used to produce a conductive layer pattern, and an inductively coupled plasma etching is performed on the surface of the conductive layer pattern, wherein an ITO etching solution is used as an etching solution.

[0087] Optionally, in one embodiment of the present invention, the thickness of the conductive layer is 200-400 nm.

[0088] S205, preparing a protective layer on a side of the conductive layer away from the second barrier layer;

[0089] The protective layer is a BAR protective layer. Optionally, the protective layer may be a composite structure of Ti, Cr, Au, and Pt, with a thickness of 1000 to 1500 nm.

[0090] Specifically, a BAR protective layer pattern is formed on a side of the conductive layer away from the second barrier layer using a photolithography process, the BAR protective layer is prepared based on the pattern of the BAR protective layer using electron beam coating or sputtering, and the metal at the pattern of the BAR protective layer is removed by stripping.

[0091] S206, sequentially preparing an insulating layer, an N-electrode layer, a first barrier layer, and a bonding layer on a side of the protective layer away from the conductive layer;

[0092] Specifically, in an embodiment of the present invention, after depositing an insulating layer on a side of the protection layer away from the conductive layer, the N-electrode layer, the first barrier layer and the bonding layer are sequentially deposited by electron beam evaporation.

[0093] S207, preparing a bonding layer on the substrate layer;

[0094] Specifically, in an embodiment of the present invention, the bonding layer is prepared on the substrate layer by electron beam evaporation or sputtering.

[0095] S208, aligning and bonding the adhesive layer and the bonding layer;

[0096] In an embodiment of the present invention, the bonding layer prepared in step S206 and the adhesive layer prepared in step S207 are aligned and bonded, thereby realizing the flipping of the p-side and n-side of the LED chip. At the same time, the large-area metal bonding improves the thermal conductivity of the LED chip.

[0097] S209, removing the silicon substrate, and roughening the surface of the epitaxial layer from which the silicon substrate is removed;

[0098] Specifically, in an embodiment of the present invention, after grinding and thinning the LED chip obtained in step S208, chemical solutions are used for etching to remove the silicon substrate. Optionally, the chemical solution is hydrofluoric acid.

[0099] A hot alkaline solution or a melt of alkaline is used to roughen the surface of the silicon substrate from which the epitaxial layer has been removed. Alternatively, in one embodiment of the present invention, a KOH aqueous solution is used to roughen the surface of the silicon substrate from which the epitaxial layer has been removed, wherein the KOH solution has a concentration of 0.05% to 10% and a temperature of 20° C. to 90° C.

[0100] S210 , preparing a P electrode layer on both sides of the epitaxial layer to complete the preparation of the vertical structure LED chip.

[0101] Specifically, in an embodiment of the present invention, the P-electrode layer is formed on both sides of the epitaxial layer by electron beam evaporation or sputtering.

[0102] In an embodiment of the present invention, the method for preparing a vertical structure LED chip further includes the following steps:

[0103] 1) Producing photolithographic patterns on vertically structured LED chips;

[0104] 2) Etching the epitaxial layer based on the photolithography pattern to obtain the light-emitting surface of the vertical structure LED chip.

[0105] Specifically, a phosphoric acid solution at 100-1300° C. is used to etch the epitaxial layer to obtain the light-emitting surface of the vertical structure LED chip.

[0106] In an embodiment of the present invention, the method for preparing a vertical structure LED chip further includes depositing a passivation layer on a side of the epitaxial layer away from the second barrier layer to protect the vertical structure LED chip of the embodiment of the present invention.

[0107] Specifically, after the passivation layer is deposited, a photolithography pattern is produced on the passivation layer, and the P-electrode layer is etched using a wet etching method to expose the P-electrode layer.

[0108] Comparative Example:

[0109] Reference Figure 3 The conductive layer 8 of the vertical structure LED chip of the embodiment of the present invention was removed to obtain the vertical structure LED chip of the comparative example. The luminous power and luminous area of ​​the vertical structure LED chip of the embodiment of the present invention and the vertical structure LED chip of the comparative example were measured, and the luminous efficiency was calculated. The specific data is shown in Table 1:

[0110] Table 1

[0111] condition Luminous power mW Test current mA Forward voltage V Luminous efficiency Embodiments of the present invention 680 350 2.87 67.69％ Comparative Example 625 350 2.86 62.22％

[0112] Table 1 shows that the luminous power of the vertical structure LED chip of the embodiment of the present invention is greater than that of the vertical structure LED chip of the comparative example, the luminous area is greater than that of the vertical structure LED chip of the comparative example, and the luminous efficiency is greater than that of the vertical structure LED chip of the comparative example. Therefore, it can be seen that, given the same luminous area, the vertical structure LED chip of the embodiment of the present invention has higher luminous flux, higher conductivity, and higher transparency. This improves the dark area at the distal end of the electrode in traditional LED chips, is more conducive to optical path design in the downstream industry chain, and is more competitive in applications with special requirements for light spot.

[0113] According to steps S201-S210, the vertical structure LED chip of the embodiment of the present invention enhances the conductivity and transparency of the LED chip by setting a conductive layer made of indium tin oxide in the LED chip, and improves the overall current structure of the LED chip, so that the LED lamp based on the vertical structure LED chip of the embodiment of the present invention has higher luminous flux and better light distribution uniformity.

[0114] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A vertical structure LED chip, characterized in that: include: substrate layer; an adhesive layer, disposed on one side of the substrate layer; A bonding layer is provided on a side of the adhesive layer away from the substrate layer; a first barrier layer, disposed on a side of the bonding layer away from the adhesive layer; An N-electrode layer is provided on a side of the first barrier layer away from the bonding layer; an insulating layer, disposed on a side of the N-electrode layer away from the first barrier layer; a protective layer, disposed on a side of the insulating layer away from the N-electrode layer; a conductive layer, disposed on a side of the protective layer away from the insulating layer, wherein the conductive layer is made of indium tin oxide; a second barrier layer, disposed on a side of the conductive layer away from the protective layer; an epitaxial layer, arranged on a side of the second barrier layer away from the conductive layer, the epitaxial layer comprising a metal reflective layer, a p-GaN layer, a multi-quantum well layer, and an n-GaN layer, wherein the metal reflective layer is arranged on a side of the second barrier layer away from the conductive layer, the p-GaN layer is arranged on a side of the metal reflective layer away from the second barrier layer, the multi-quantum well layer is arranged on a side of the p-GaN layer away from the metal reflective layer, and the n-GaN layer is arranged on a side of the multi-quantum well layer away from the p-GaN layer; The P electrode layers are respectively arranged on both sides of the epitaxial layer.

2. The vertical structure LED chip according to claim 1, characterized in that: A passivation layer is further provided on a side of the epitaxial layer away from the second barrier layer.

3. The vertical structure LED chip according to claim 1, characterized in that: The metal reflective layer is made of Ag and Ni.

4. The vertical structure LED chip according to claim 1, characterized in that: The first barrier layer and the second barrier layer are made of SiN x And SiO2.

5. The vertical structure LED chip according to claim 1, characterized in that: The P electrode layer is prepared by using any one of Cr, Ti, Al, Pt and Au.

6. The vertical structure LED chip according to claim 1, characterized in that: The bonding layer is prepared by using any one of Cr, Ni, Sn, Pt and Au.

7. The vertical structure LED chip according to claim 1, characterized in that: The bonding layer is prepared by using any one of Ni, Sn and Au.

8. A method for preparing a vertical structure LED chip, characterized in that: The following steps are involved: An n-GaN layer, a multi-quantum well layer, a p-GaN layer, and a metal reflective layer are sequentially grown on a silicon substrate to form an epitaxial layer; Using a photolithography process to form a mark point and an N-electrode hole pattern on a side of the epitaxial layer away from the silicon substrate, and performing inductively coupled plasma etching on the side of the epitaxial layer away from the silicon substrate based on the mark point and the N-electrode hole pattern, until the etching depth reaches the n-GaN layer; forming a second barrier layer on a side of the epitaxial layer away from the silicon substrate; A conductive layer is formed on a side of the second barrier layer away from the epitaxial layer, wherein the conductive layer is formed of indium tin oxide; preparing a protective layer on a side of the conductive layer away from the second barrier layer; An insulating layer, an N-electrode layer, a first barrier layer and a bonding layer are sequentially formed on a side of the protective layer away from the conductive layer; preparing a bonding layer on the substrate layer; aligning and bonding the adhesive layer and the bonding layer; removing the silicon substrate, and roughening the surface of the epitaxial layer from which the silicon substrate is removed; P electrode layers are prepared on both sides of the epitaxial layer to complete the preparation of the vertical structure LED chip.

9. The method for preparing a vertical structure LED chip according to claim 8, characterized in that: The preparation method further comprises: Fabricating a photolithographic pattern on the vertical structure LED chip; The epitaxial layer is corroded based on the photolithography pattern to obtain the light-emitting surface of the vertical structure LED chip.

10. The method for preparing a vertical structure LED chip according to claim 8, characterized in that: The preparation method further comprises: A passivation layer is deposited on a side of the epitaxial layer away from the second barrier layer.

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