Low power flip-flop
By designing a low-power flip-flop and optimizing the connection state of PMOS and NMOS using a clock control module and a flip-flop module, the problem of high dynamic power consumption of the flip-flop was solved, achieving a significant reduction in dynamic power consumption and an improvement in system performance under specific conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-06-15
- Publication Date
- 2026-06-02
Smart Images
Figure CN115333509B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a low-power trigger. Background Technology
[0002] In current circuit design, flip-flops are widely used. In very large-scale integrated circuits (VLSI), reducing energy consumption is the direct goal of low-power design, and the main reason for energy consumption is the constant switching between 0 and 1 at high frequencies. Other energy consumption consists of dynamic and static components depending on the circuit characteristics. Dynamic circuits consume energy by pre-charging the capacitors at circuit nodes, while static circuits mainly consume energy in the form of subthreshold leakage current. Therefore, the clock network composed of timing units (flip-flops and latches) is the main source of energy consumption in VLSI systems.
[0003] In typical integrated circuit designs, approximately 30% to 60% of the energy consumption is in the clock network. Reducing the energy consumption of flip-flops directly reduces the overall system energy consumption. Furthermore, improving flip-flop performance directly reduces the distributed constraints of the clock network and enhances the overall system performance. Therefore, the proper design and selection of flip-flops have a significant impact on the overall system performance and energy consumption. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low-power trigger to solve the problem of high dynamic power consumption of triggers in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a low-power trigger, comprising at least:
[0006] The clock control module includes a first, second, and third input signal terminals and a clock signal terminal; the clock control module is configured to control the clock signal Clock by inputting signal D through the first input signal terminal, inputting signal RESETB through the second input signal terminal, inputting clock signal Clock through the clock signal terminal, and inputting signal Q through the third input signal terminal, so as to generate a controlled clock signal;
[0007] The trigger module selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the signal Q.
[0008] Preferably, the first to sixth PMOS and the first to sixth NMOS are configured; wherein the gate of the first NMOS is connected to the gate of the second PMOS, and the connection terminal serves as the third signal input terminal; one end of each of the first and second PMOS and the first and second NMOS is connected to the gate of the fifth PMOS and the fifth NMOS; the gates of the third PMOS and the third NMOS are connected to the drain of the sixth PMOS, the drain of the fourth NMOS, the drain of the fifth NMOS, and the drain of the sixth NMOS, forming a connection terminal CKN; the drain of the fourth PMOS is connected to the source of the fifth PMOS; the drain of the fifth PMOS is connected to the source of the sixth PMOS; the gate of the sixth PMOS is connected to the gate of the fourth NMOS, forming a connection terminal CLK; the gate of the fourth PMOS is connected to the gate of the sixth NMOS; and the drain of the third PMOS is connected to the drain of the third NMOS, forming a connection terminal CKP.
[0009] Preferably, the source of the fourth NMOS is connected to the source of the fifth NMOS and the source of the sixth NMOS, and they are all grounded; the source of the third NMOS is grounded.
[0010] Preferably, the other ends of the first PMOS and the first NMOS are connected to each other, and the connection end serves as the first input signal end; the other ends of the second PMOS and the second NMOS are connected to each other, and the level of the input signal at the connection end is opposite to the level of the signal D input at the first input signal end; the level of the gate input signal of the first PMOS and the gate input signal of the second NMOS is opposite to the level of the signal Q input at the third input signal end.
[0011] Preferably, the gate of the fourth PMOS and the gate of the sixth NMOS share the same input signal RESETB; the connection terminal CLK is used to input the clock signal Clock.
[0012] Preferably, when the signal RESETB is low, the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to low, and the signal of the connection terminal CKP is correspondingly high.
[0013] Preferably, when the signal D and the signal Q are the same, the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to a low level, and the signal of the connection terminal CKP is correspondingly high.
[0014] Preferably, when the signal RESETB is high and the signals D and Q are inconsistent, the fourth PMOS and the fifth PMOS are turned on, the fifth NMOS and the sixth NMOS are turned off, and the signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the connection terminal CLK.
[0015] As described above, the low-power trigger of the present invention has the following beneficial effects: the present invention can significantly reduce dynamic power consumption when the switching activity rate is low or the reset signal is valid for a long time. Attached Figure Description
[0016] Figure 1 The diagram shown is a schematic of the low-power trigger circuit of the present invention;
[0017] Figure 2 The diagram shows the circuit structure of the clock control module in this invention.
[0018] Figure 3 The graph shows a power consumption comparison between the trigger with a clock control module and a conventional trigger with a reset function in the prior art.
[0019] Figure 4 The diagram shows a functional simulation of a trigger with a switching activity rate of 50% and a time reset of 1 / 3 of the time in the prior art.
[0020] Figure 5 The diagram shown is a functional simulation diagram of the low-power trigger when the switching activity rate is 50% and the time is reset by 1 / 3 of the time in this invention. Detailed Implementation
[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0022] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0023] This invention provides a low-power trigger, such as... Figure 1 As shown, Figure 1The diagram shown illustrates a low-power trigger circuit according to the present invention. It includes at least:
[0024] The clock control module (CLK_CONTROL) includes a first, second, and third input signal terminals and a clock signal terminal. The clock control module is configured to control the clock signal Clock by inputting signal D through the first input signal terminal, signal RESETB through the second input signal terminal, clock signal Clock through the clock signal terminal, and signal Q through the third input signal terminal, so as to generate a controlled clock signal.
[0025] The trigger module (DFF) selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the signal Q.
[0026] Further, the clock control module of this embodiment includes: first to sixth PMOS and first to sixth NMOS; wherein the gate of the first NMOS is connected to the gate of the second PMOS, and the connection terminal serves as the third signal input terminal; one end of each of the first, second PMOS, first, and second NMOS is connected to the gate of the fifth PMOS and the fifth NMOS; the gates of the third PMOS and the third NMOS are connected to the drain of the sixth PMOS, the drain of the fourth NMOS, the drain of the fifth NMOS, and the drain of the sixth NMOS, forming a connection terminal CKN; the drain of the fourth PMOS is connected to the source of the fifth PMOS; the drain of the fifth PMOS is connected to the source of the sixth PMOS; the gate of the sixth PMOS is connected to the gate of the fourth NMOS, forming a connection terminal CLK; the gate of the fourth PMOS is connected to the gate of the sixth NMOS; the drain of the third PMOS is connected to the drain of the third NMOS, forming a connection terminal CKP.
[0027] like Figure 2 As shown, Figure 2The diagram shows a schematic of the clock control module circuit structure in this invention. The clock control module includes: a first to a sixth PMOS and a first to a sixth NMOS; wherein the gate of the first NMOS (001) is connected to the gate of the second PMOS (02), and the connection end serves as the third signal input terminal; one end of each of the first PMOS (01), the second PMOS (02), the first NMOS (001), and the second NMOS (002) is connected to the gate of the fifth PMOS (05) and the fifth NMOS (005); the gates of the third PMOS (03) and the third NMOS (003) are connected to the drain of the sixth PMOS (06) and the fourth NMOS. The drain of S(004), the drain of the fifth NMOS(005), and the drain of the sixth NMOS(006) form a connection terminal CKN; the drain of the fourth PMOS(04) is connected to the source of the fifth PMOS(05); the drain of the fifth PMOS(05) is connected to the source of the sixth PMOS(06); the gate of the sixth PMOS(06) is connected to the gate of the fourth NMOS(004) to form a connection terminal CLK; the gate of the fourth PMOS(04) is connected to the gate of the sixth NMOS(006); the drain of the third PMOS(03) is connected to the drain of the third NMOS(003) to form a connection terminal CKP.
[0028] In a further embodiment of the present invention, the source of the fourth NMOS is connected to the source of the fifth NMOS and the source of the sixth NMOS, and they are all grounded; the source of the third NMOS is grounded.
[0029] In a further embodiment of the present invention, the other ends of the first PMOS and the first NMOS are connected to each other, and the connection end serves as the first input signal end; the other ends of the second PMOS and the second NMOS are connected to each other, and the level of the input signal at the connection end is opposite to the level of the signal D input at the first input signal end; the level of the gate input signal of the first PMOS and the gate input signal of the second NMOS is opposite to the level of the signal Q input at the third input signal end.
[0030] In a further embodiment of the present invention, the gate of the fourth PMOS and the gate of the sixth NMOS share the same input signal RESETB; the connection terminal CLK is used to input the clock signal Clock.
[0031] Furthermore, in this embodiment, when the signal RESETB is low (signal RESETB = 0), the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to low level (0), and the signal of the connection terminal CKP is correspondingly high level (1).
[0032] In a further embodiment of the present invention, when the signal D and the signal Q are the same, the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to a low level (0), and the signal of the connection terminal CKP is correspondingly high level (1).
[0033] Furthermore, in this embodiment, when the signal RESETB is high and the signal D and the signal Q are inconsistent, the fourth PMOS and the fifth PMOS are turned on, and the fifth NMOS and the sixth NMOS are turned off. The signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the connection terminal CLK.
[0034] like Figure 3 As shown, Figure 3 The diagram shows a power consumption comparison between the trigger with a clock control module and a conventional trigger with a reset function in the prior art. It can be seen that, compared with a trigger with a reset function but without a clock control module, the trigger of the present invention has significantly lower dynamic power consumption when it is in the case of multiple resets or long-term resets, or when the flip-flop rate of the trigger input signal is low.
[0035] like Figure 4 and Figure 5 As shown, Figure 4 The diagram shows a functional simulation of a trigger with a switching activity rate of 50% and a time reset of 1 / 3 of the time in the prior art. Figure 5 The diagram shown is a functional simulation of the low-power trigger in this invention when the switch activity rate is 50% and the reset time is 1 / 3. It can be seen that this invention can significantly reduce dynamic power consumption when the switch activity rate is low or the reset signal is valid for a long time.
[0036] In summary, this invention can significantly reduce dynamic power consumption when the switching activity rate is low or the reset signal is valid for a long time. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A low-power trigger, characterized in that, At least including: The clock control module includes first, second, and third input signal terminals and a clock signal terminal; The clock control module is configured to control the clock signal Clock by inputting signal D through the first input signal terminal, inputting signal RESETB through the second input signal terminal, inputting clock signal Clock through the clock signal terminal, and inputting signal Q through the third input signal terminal, so as to generate a controlled clock signal. The trigger module selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the signal Q; The clock control module includes: first to sixth PMOS and first to sixth NMOS; The gate of the first NMOS is connected to the gate of the second PMOS, and the connection terminal serves as the third signal input terminal. One end of each of the first, second PMOS, first, and second NMOS is connected to the gate of the fifth PMOS and the fifth NMOS. The gates of the third PMOS and the third NMOS are connected to the drains of the sixth PMOS, the fourth NMOS, the fifth NMOS, and the sixth NMOS, forming the connection terminal CKN. The drain of the fourth PMOS is connected to the source of the fifth PMOS. The drain of the fifth PMOS is connected to the source of the sixth PMOS. The gate of the sixth PMOS is connected to the gate of the fourth NMOS, forming the connection terminal CLK. The gate of the fourth PMOS is connected to the gate of the sixth NMOS. The drain of the third PMOS is connected to the drain of the third NMOS, forming the connection terminal CKP.
2. The low-power trigger according to claim 1, characterized in that: The source of the fourth NMOS is connected to the source of the fifth NMOS and the source of the sixth NMOS, and they are all grounded; the source of the third NMOS is grounded.
3. The low-power trigger according to claim 1, characterized in that: The other ends of the first PMOS and the first NMOS are connected to each other, and this connection end serves as the first input signal end; the other ends of the second PMOS and the second NMOS are connected to each other, and the level of the input signal at this connection end is opposite to the level of the signal D input at the first input signal end; the level of the gate input signal of the first PMOS and the gate input signal of the second NMOS is opposite to the level of the signal Q input at the third input signal end.
4. The low-power trigger according to claim 3, characterized in that: The gate of the fourth PMOS and the gate of the sixth NMOS share the input of the signal RESETB; the connection terminal CLK is used to input the clock signal Clock.
5. The low-power trigger according to claim 4, characterized in that: When the signal RESETB is high, the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to low, and the signal of the connection terminal CKP is correspondingly high.
6. The low-power trigger according to claim 4, characterized in that: When the signal D and the signal Q are the same, the fourth PMOS and the fifth PMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, the signal level of the connection terminal CKN is pulled down to a low level, and the signal of the connection terminal CKP is correspondingly high.
7. The low-power trigger according to claim 4, characterized in that: When the signal RESETB is low and the signals D and Q are inconsistent, the fourth PMOS and the fifth PMOS are turned on, and the fifth NMOS and the sixth NMOS are turned off. The signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the connection terminal CLK.