A sample-and-hold circuit and method

Abstract

This application discloses a sample-and-hold circuit and method, belonging to the field of signal processing technology. The circuit includes an input unit, a track / hold switch unit, and an output unit. The input unit receives a differential input signal and amplifies it before inputting it to the track / hold switch unit. The track / hold switch unit tracks or holds the amplified differential input signal. The track / hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source. The emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, and the base of the first emitter follower is connected to a first output terminal of the input unit. The first output terminal is used to output one of the two amplified differential input signals.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of signal processing, and particularly relates to a sample-and-hold circuit and method. BACKGROUND

[0002] The sample-and-hold circuit is connected in front of an analog-to-digital converter (ADC), which holds the level of an input signal at the beginning of analog-to-digital conversion to ensure the accuracy of conversion, and can track the change of the input signal after the end of analog-to-digital conversion to receive the input at the next moment. The sample-and-hold circuit is indispensable for an ADC of a high-speed wideband input signal, and its performance directly affects the performance of the ADC.

[0003] In the track phase of the sample-and-hold circuit with a switched emitter follower (SEF) structure, the use of the SEF can meet the demand of a high-bandwidth input signal, and in the hold phase, in order to make the linearity of the circuit high, the SEF needs to be completely turned off, which requires the current source current to be as high as possible. However, the current sample-and-hold circuit generally uses a fixed current source to control the current in the two phases. The high current corresponds to a large SEF size in the track phase, and the bandwidth is small. There is a contradiction between the bandwidth and the linearity. SUMMARY

[0004] The purpose of the embodiments of the application is to provide a sample-and-hold circuit and method, which can solve the contradiction between the bandwidth and the linearity of the existing sample-and-hold circuit.

[0005] In order to solve the above technical problems, the application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a sample and hold circuit, the circuit comprising an input unit, a tracking / holding switch unit and an output unit, the input unit being configured to receive a differential input signal and input the amplified differential input signal to the tracking / holding switch unit after amplification; the tracking / holding switch unit being configured to track or hold the amplified differential input signal, the tracking / holding switch unit comprising a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, the base of the first emitter follower is connected to a first output end of the input unit, the first output end being configured to output one of the two amplified differential input signals, the first emitter follower being configured to control the circuit to switch between tracking and holding states, and the shunt circuit subunit being configured to shunt the current of the first current source in the tracking state; and the output unit being connected to the holding capacitor and configured to output a differential output signal corresponding to the differential input signal to provide driving capability for a subsequent circuit.

[0007] In a second aspect, an embodiment of the present application provides a sample and hold method, the method being applied to the sample and hold circuit of the first aspect, the method comprising: receiving a differential input signal by an input unit and inputting the amplified differential input signal to a tracking / holding switch unit after amplification; tracking or holding the amplified differential input signal by the tracking / holding switch unit, wherein the tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, the base of the first emitter follower is connected to a first output end of the input unit, the first output end is configured to output one of the two amplified differential input signals, the first emitter follower is configured to control the circuit to switch between tracking and holding states, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; and outputting a differential output signal corresponding to the differential input signal by an output unit to provide driving capability for a subsequent circuit, wherein the output unit is connected to the holding capacitor.

[0008] In a third aspect, an embodiment of the present application provides a sample and hold device, which is used to implement the sample and hold method in the second aspect, and the device comprises: an input module, configured to receive a differential input signal and input the amplified differential input signal into a tracking / holding switch unit; a tracking / holding switch module, configured to track or hold the amplified differential input signal, the tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected with the holding capacitor, the collector of the first emitter follower is connected with a power supply voltage, the base of the first emitter follower is connected with a first output end of the input unit, the first output end is configured to output one of the two amplified differential input signals, and the first emitter follower is configured to control the circuit to switch between tracking and holding states, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; and an output module, connected with the holding capacitor, configured to output a differential output signal corresponding to the differential input signal and provide driving capability for a subsequent circuit.

[0009] In a fourth aspect, an embodiment of the present application provides an electronic device, which comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, and the program or instruction is executed by the processor to implement the steps of the sample and hold method in the second aspect.

[0010] In a fifth aspect, an embodiment of the present application provides a readable storage medium, which stores a program or instruction, and the program or instruction is executed by a processor to implement the steps of the sample and hold method in the second aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a chip, which comprises a processor and a communication interface, the communication interface is coupled with the processor, and the processor is configured to run a program or instruction to implement the steps of the sample and hold method in the second aspect.

[0012] In the embodiment of the present application, through the input unit, the tracking / holding switch unit and the output unit, the input unit is used for receiving a differential input signal and inputting the amplified differential input signal to the tracking / holding switch unit; the tracking / holding switch unit is used for tracking or holding the amplified differential input signal, the tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected with the holding capacitor, the collector of the first emitter follower is connected with a power supply voltage, the base of the first emitter follower is connected with a first output end of the input unit, the first output end is used for outputting one of the two amplified differential input signals, the first emitter follower is used for controlling the circuit to switch between tracking and holding two states, and the shunt circuit subunit is used for shunting the current of the first current source in the tracking state; the output unit is connected with the holding capacitor and is used for outputting a differential output signal corresponding to the differential input signal, thereby providing driving capability for subsequent circuits and solving the contradiction between the bandwidth and the linearity of the existing sample and hold circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a structural schematic diagram of a sample and hold circuit provided by the embodiment of the present application;

[0014] Figure 2 is a structural schematic diagram of another sample and hold circuit provided by the embodiment of the present application;

[0015] Figure 3 is a schematic flow chart of a sample and hold method provided by the embodiment of the present application;

[0016] Figure 4 is a structural schematic diagram of a sample and hold device provided by the embodiment of the present application;

[0017] Figure 5 is a structural schematic diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0019] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in a "or" relationship.

[0020] The sampling and holding circuit and method provided by the embodiments of the present application will be described in detail below in combination with the drawings, specific embodiments and application scenarios.

[0021] Figure 1 The structure diagram of the sampling and holding circuit provided by the embodiments of the present application. The sampling and holding circuit 100 comprises an input unit 110, a tracking / holding switch unit 120 and an output unit 130. The input unit 110 is configured to receive a differential input signal, amplify the differential input signal and input the amplified differential input signal to the tracking / holding switch unit. The tracking / holding switch unit 120 is configured to track or hold the amplified differential input signal. The tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source. The emitter of the first emitter follower is connected to the holding capacitor. The collector of the first emitter follower is connected to a power supply voltage. The base of the first emitter follower is connected to a first output end of the input unit. The first output end is configured to output one of two amplified differential input signals. The first emitter follower is configured to control the circuit to switch between tracking and holding states. The shunt circuit subunit is configured to shunt the current of the first current source in the tracking state. The output unit 130 is connected to the holding capacitor and is configured to output a differential output signal corresponding to the differential input signal, thereby providing driving capability for subsequent circuits.

[0022] As Figure 1As shown, the input unit 110 receives two differential inputs VIN and VIP, and outputs them after amplification through ports A and B to the track / hold switch unit 120, which is connected to the holding capacitors C1 and C2 through the emitters of the first emitter followers Q10 and Q14, the collectors of the first emitter followers are connected to the power supply voltage, and the bases of the first emitter followers are connected to the output ends A or B of the input unit 110, so as to realize tracking or holding of the two amplified differential input signals, and the output unit 130 is connected to the holding capacitors C1 and C2 respectively, for outputting differential output signals VON and VOP corresponding to the differential input signals VIN and VIP, to provide driving capability for subsequent circuits, and in the tracking state, the current of the first current source I1 or I3 is shunted through the first emitter followers Q10 and Q14 by the shunt circuit unit, so as to reduce the current flowing through the first emitter followers Q10 and Q14, and the circuit size of Q10 and Q14 can be relatively small, and the equivalent capacitance of ports A and B is also reduced, so that the bandwidth of the sample and hold circuit is improved while the linearity of the circuit is improved.

[0023] The sample and hold circuit provided in the application can realize independent control of the tracking and holding two stages by adding a shunt circuit subunit to the track / hold switch unit, that is, both the bandwidth and the linearity can be simultaneously considered to achieve relatively optimal performance.

[0024] The sample and hold circuit provided in the embodiment of the application comprises an input unit, a track / hold switch unit and an output unit, the input unit is configured to receive a differential input signal and input the differential input signal after amplification to the track / hold switch unit; the track / hold switch unit is configured to track or hold the amplified differential input signal, and comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, and the base of the first emitter follower is connected to a first output end of the input unit, the first output end is configured to output one of the two amplified differential input signals, the first emitter follower is configured to control the circuit to switch between tracking and holding states, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; and the output unit is connected to the holding capacitor and configured to output a differential output signal corresponding to the differential input signal, to provide driving capability for subsequent circuits, and can solve the contradiction between the bandwidth and the linearity existing in the prior art sample and hold circuit.

[0025] As Figure 2The diagram shown is a schematic of another sample-and-hold circuit provided in an embodiment of this application. The sample-and-hold circuit 200 includes an input unit 210, a track / hold switch unit 220, and an output unit 230. The input unit 210 receives a differential input signal and amplifies it before inputting it to the track / hold switch unit. The track / hold switch unit 220 tracks or holds the amplified differential input signal. The track / hold switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source. The emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, and the base of the first emitter follower is connected to the first output terminal of the input unit. The first output terminal outputs one of the two amplified differential input signals. The first emitter follower controls the circuit to switch between tracking and holding states. The shunt circuit subunit shunts the current from the first current source in the tracking state. The output unit 230, connected to the holding capacitor, outputs a differential output signal corresponding to the differential input signal, providing driving capability for subsequent circuits.

[0026] The shunt circuit subunit includes two switching transistors Q5, Q6 or Q16, Q18 and two cascaded transistors Q8, Q9 or Q15, Q17. The collector of the first switching transistor Q5 or Q16 is connected to the emitter of the first cascaded transistor Q8 or Q15, and the collector of the second switching transistor Q6 or Q18 is connected to the emitter of the second cascaded transistor Q9 or Q17 to form two shunts respectively. The bases of the two switching transistors are connected to the clock input terminal CKN, and the emitters of the two switching transistors are connected to the first current source I1 or I3. The bases of the two cascaded transistors are connected to a bias voltage Vb2. The collector of the first cascaded transistor Q8 or Q15 is connected to the emitter of the first emitter follower Q10 or Q14, and the collector of the second cascaded transistor Q9 or Q17 is connected to the power supply voltage Vcc.

[0027] The current shunt circuit subunit is used to shunt the current from the first current source in the tracking state, including:

[0028] The current shunt circuit subunit is used to control the current of the first current source to flow through the two shunts respectively when the signal at the clock input terminal is high.

[0029] In one implementation, when the signal at the clock input terminal is high, controlling the current of the first current source to flow through the two branches respectively includes:

[0030] When the signal at the clock input terminal is high, the first switching transistors Q5 and Q6, the first cascaded transistors Q8 and Q9, the second switching transistors Q18 and Q16, and the second cascaded transistors Q15 and Q17 are all turned on. The current I1 or I3 of the first current source flows through the two branches respectively. One of the currents in the two branches flows through the first emitter follower Q10 or Q14, turning on the first emitter follower Q10 or Q14 to track the amplified differential input signal.

[0031] In one implementation, the first emitter follower is used to control the circuit to switch between tracking and hold states, including:

[0032] When the first emitter follower is turned on, the circuit is in the tracking state;

[0033] And / or,

[0034] When the first emitter follower is turned off, the circuit is in the holding state.

[0035] In one implementation, the track / hold switch unit 220 further includes a third switching transistor Q4 or Q13 and a third cascaded transistor Q7 or Q12, wherein the base of the third switching transistor Q4 or Q13 is connected to the clock input terminal CKP, the emitter of the third switching transistor Q4 or Q13 is connected to the first current source I1 or I3, the collector of the third switching transistor Q4 or Q13 is connected to the emitter of the third cascaded transistor Q7 or Q12, the base of the third cascaded transistor Q7 or Q12 is connected to the bias voltage Vb2, and the collector of the third cascaded transistor Q7 or Q12 is connected to the base of the first emitter follower Q10 or Q14;

[0036] When the first emitter follower is turned off, the circuit is in the holding state, including:

[0037] When the signal at the clock input terminal is low, the third switching transistor Q4 or Q13 and the third cascaded transistor Q7 or Q12 are turned on respectively, the first emitter follower Q10 or Q14 is turned off, and the circuit is in the holding state.

[0038] Specifically, when CKP is high and CKN is low, Q4, Q7, Q12, and Q13 are turned on, and I1 and I3 flow through R0 and R1 respectively, making the potentials at points A and B even lower. Simultaneously, Q8, Q5, Q15, and Q16 are turned off. Due to the holding effect of capacitors C1 and C2, the potentials at points C and D remain unchanged, thus Q10 and Q14 are turned off, and the circuit is in a holding state. When CKP is low and CKN is high, Q4, Q7, Q12, and Q13 are turned off, and nodes A and B return to their normal high potentials. I1 flows through Q5 and Q8 through the main open circuit. With Q10 off, I3 flows through Q16 and Q15 to the main switch Q14. Switches Q10 and Q14 operate in emitter follower mode, and the potentials at points C and D follow the potential changes at points A and B. The circuit is in sampling mode. Due to the current shunting effect of Q6, Q9, Q17, and Q18, the current flowing through the main switches Q10 and Q14 can be reduced. At the same time, the symmetry of the two branches CKP and CKN is maintained. The circuit size of Q10 and Q14 can be relatively small, and the equivalent capacitance relative to nodes A and B is also reduced, which can effectively improve the bandwidth of the sample-and-hold circuit.

[0039] It should be noted that the input and output units in the embodiments of this application both include corresponding current sources to provide suitable current to their circuits, such as... Figure 2 The current values ​​provided by the current sources I0, I5, I2, and I4 can be the same or different, and can be set according to specific circumstances. This application does not impose specific restrictions.

[0040] Furthermore, the input unit in the above embodiments includes multiple components for amplifying the differential input signal, which may be as follows: Figure 2 The structure shown can also be composed of other components with more or fewer parts than this structure. This application does not impose specific limitations. The output unit in the above embodiment includes an emitter follower Q11 or Q19, which, by being connected to a holding capacitor C1 or C2, can isolate the holding capacitor from the subsequent load, thereby providing a certain driving capability for the subsequent load.

[0041] It should also be noted that due to the junction capacitance of the first emitter follower Q10 and Q14, voltage feedthrough will occur during the instantaneous switching on and off of the switch. Therefore, it is possible to use... Figure 2 The compensation capacitors Cf1 and Cf2 shown are used for feedforward compensation, which can cancel the interference caused by feedforward and make the sampled and held waveform more ideal.

[0042] This application also provides a sample holding method, which is applied to, for example... Figure 1 and Figure 2The sample-and-hold circuit includes: receiving a differential input signal through an input unit, amplifying the differential input signal, and inputting it into a tracking / hold switching unit; tracking or holding the amplified differential input signal through the tracking / hold switching unit, wherein the tracking / hold switching unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source; the emitter of the first emitter follower is connected to the holding capacitor; the collector of the first emitter follower is connected to a power supply voltage; the base of the first emitter follower is connected to a first output terminal of the input unit; the first output terminal is used to output one of the two amplified differential input signals; the first emitter follower is used to control the circuit to switch between tracking and holding states; the shunt circuit subunit is used to shunt the current from the first current source in the tracking state; and outputting a differential output signal corresponding to the differential input signal through an output unit to provide driving capability for subsequent circuits, wherein the output unit is connected to the holding capacitor.

[0043] The sampling and holding method provided in this application will be described below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0044] Figure 3 This paper illustrates a sample-and-hold method provided by an embodiment of this application. This method can be applied to the above-described... Figure 1 and Figure 2 The sample-and-hold circuit, or method, can be executed by various functional units within the sample-and-hold circuit. In other words, the method can be executed by software or hardware installed in the various functional units of the sample-and-hold circuit, and includes the following steps:

[0045] S:301: Receive the differential input signal through the input unit, amplify the differential input signal, and input it into the tracking / holding switch unit.

[0046] The input module receives the clock source signal at its signal input terminal.

[0047] S302: Track or hold the amplified differential input signal through the track / hold switch unit.

[0048] The tracking / hold switching unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source. The emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to the power supply voltage, and the base of the first emitter follower is connected to the first output terminal of the input unit. The first output terminal is used to output one of the two amplified differential input signals. The first emitter follower is used to control the circuit to switch between tracking and holding states. The shunt circuit subunit is used to shunt the current from the first current source in the tracking state.

[0049] S303: The output unit outputs the differential output signal corresponding to the differential input signal to provide driving capability for subsequent circuits, wherein the output unit is connected to the holding capacitor.

[0050] In one implementation, the shunt circuit subunit is used to shunt the current from the first current source in the tracking state, including:

[0051] When the signal at the clock input terminal is high, the shunt circuit subunit controls the current of the first current source to flow through two branches. These two branches are formed by connecting the collector of the first switching transistor to the emitter of the first cascaded transistor, and by connecting the collector of the second switching transistor to the emitter of the second cascaded transistor. The shunt circuit subunit includes the two switching transistors and the two cascaded transistors. The bases of the two switching transistors are connected to the clock input terminal, and the emitters of the two switching transistors are connected to the current source. The bases of the two cascaded transistors are connected to a bias voltage. The collector of the first cascaded transistor is connected to the emitter of the first emitter follower, and the collector of the second cascaded transistor is connected to the power supply voltage.

[0052] In one implementation, when the signal at the clock input terminal is high, the shunt circuit subunit controls the current of the first current source to flow through the two shunts respectively, including:

[0053] When the signal at the clock input terminal is high, the first switching transistor, the first cascaded transistor, the second switching transistor, and the second cascaded transistor are all turned on, and the current source current flows through the two branches respectively. One of the two branches flows through the first emitter follower, causing the first emitter follower to turn on to track the amplified differential input signal.

[0054] In one implementation, the first emitter follower is used to control the circuit to switch between tracking and hold states, including:

[0055] When the first emitter follower is turned on, the circuit is controlled to be in the tracking state;

[0056] And / or,

[0057] When the first emitter follower is turned off, the circuit is controlled to be in the holding state.

[0058] In one implementation, controlling the circuit to be in the holding state when the first emitter follower is turned off includes:

[0059] When the signal at the clock input terminal is low, the third switching transistor and the third cascaded transistor are turned on, the first emitter follower is turned off, and the circuit is controlled to be in the hold state. The track / hold switch unit further includes a third switching transistor and a third cascaded transistor. The base of the third switching transistor is connected to the clock input terminal, the emitter of the third switching transistor is connected to the first current source, the collector of the third switching transistor is connected to the emitter of the third cascaded transistor, the base of the third cascaded transistor is connected to the bias voltage, and the collector of the third cascaded transistor is connected to the base of the first emitter follower.

[0060] For detailed implementation of the above steps, please refer to Figure 1 and Figure 2 The descriptions of the relevant functional units of the sample-and-hold circuit, and the execution of the corresponding steps to achieve the same technical effect, will not be repeated here to avoid repetition.

[0061] This application provides a sample-and-hold method that receives a differential input signal through an input unit, amplifies the differential input signal, and inputs it to a tracking / hold switching unit. The tracking / hold switching unit tracks or holds the amplified differential input signal. The tracking / hold switching unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source. The emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, and the base of the first emitter follower is connected to a first output terminal of the input unit. The first output terminal outputs one of the two amplified differential input signals. The first emitter follower controls the circuit to switch between tracking and holding states. The shunt circuit subunit shunts the current from the first current source in the tracking state. The output unit outputs a differential output signal corresponding to the differential input signal, providing driving capability for subsequent circuits. The output unit is connected to the holding capacitor, which can resolve the contradiction between bandwidth and linearity in existing sample-and-hold circuits.

[0062] It should be noted that the sampling and holding method provided in this application can be executed by a sampling and holding device or a control module within that sampling and holding device for executing the sampling and holding method. This application uses the example of a sampling and holding device executing the sampling and holding method to illustrate the sampling and holding device provided in this application.

[0063] Figure 4 This diagram illustrates the structure of a sampling and holding device according to an embodiment of this application. Figure 4 As shown, the sample-and-hold device 400 includes: an input module 410 for receiving a differential input signal and amplifying the differential input signal before inputting it into the tracking / hold switching unit; a tracking / hold switching module 420 for tracking or holding the amplified differential input signal, the tracking / hold switching unit including a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source, wherein the emitter of the first emitter follower is connected to the holding capacitor, the collector of the first emitter follower is connected to a power supply voltage, the base of the first emitter follower is connected to the first output terminal of the input unit, the first output terminal is used to output one of the two amplified differential input signals, the first emitter follower is used to control the circuit to switch between tracking and holding states, the shunt circuit subunit is used to shunt the current of the first current source in the tracking state; and an output module 430, connected to the holding capacitor, for outputting a differential output signal corresponding to the differential input signal, providing driving capability for subsequent circuits.

[0064] In one implementation, the shunt circuit subunit includes two switching transistors and two cascaded transistors, wherein the collector of the first switching transistor is connected to the emitter of the first cascaded transistor, the collector of the second switching transistor is connected to the emitter of the second cascaded transistor to form two shunts respectively, the bases of the two switching transistors are connected to the clock input terminal, the emitters of the two switching transistors are connected to the first current source, the bases of the two cascaded transistors are connected to a bias voltage, the collector of the first cascaded transistor is connected to the emitter of the first emitter follower, and the collector of the second cascaded transistor is connected to the power supply voltage;

[0065] The current shunt circuit subunit is used to shunt the current from the first current source in the tracking state, including:

[0066] The current shunt circuit subunit is used to control the current of the first current source to flow through the two shunts respectively when the signal at the clock input terminal is high.

[0067] In one implementation, when the signal at the clock input terminal is high, controlling the current of the first current source to flow through the two branches respectively includes:

[0068] When the signal at the clock input terminal is high, the first switching transistor, the first cascaded transistor, the second switching transistor, and the second cascaded transistor are all turned on, and the current from the first current source flows through the two branches. One of the two branches flows through the first emitter follower, causing the first emitter follower to turn on to track the amplified differential input signal.

[0069] In one implementation, the first emitter follower is used to control the circuit to switch between tracking and hold states, including:

[0070] When the first emitter follower is turned on, the circuit is in the tracking state;

[0071] And / or,

[0072] When the first emitter follower is turned off, the circuit is in the holding state.

[0073] In one implementation, the track / hold switch unit further includes a third switching transistor and a third cascaded transistor, wherein the base of the third switching transistor is connected to the clock input terminal, the emitter of the third switching transistor is connected to the first current source, the collector of the third switching transistor is connected to the emitter of the third cascaded transistor, the base of the third cascaded transistor is connected to the bias voltage, and the collector of the third cascaded transistor is connected to the base of the first emitter follower.

[0074] When the first emitter follower is turned off, the circuit is in the holding state, including:

[0075] When the signal at the clock input terminal is low, the third switching transistor and the third cascaded transistor are turned on, the first emitter follower is turned off, and the circuit is in the holding state.

[0076] The sampling and holding device in the embodiments of this application can be a device, or it can be a component, integrated circuit, or chip in a terminal. The embodiments of this application do not make specific limitations.

[0077] The sampling and holding device in the embodiments of this application can be a device with an operating system, or other possible operating systems. The embodiments of this application do not specifically limit it.

[0078] The sampling and holding device provided in this application embodiment can achieve... Figures 1 to 2The function of each unit in the sample-and-hold circuit, or to implement Figure 3 The various processes implemented in the sampling and holding method embodiments are not described in detail here to avoid repetition.

[0079] Optional, such as Figure 5 As shown, this application embodiment also provides an electronic device 500, including a processor 501, a memory 502, and a program or instructions stored in the memory 502 and executable on the processor 501. When executed by the processor 501, the program or instructions perform the following: receiving a differential input signal through an input unit, amplifying the differential input signal, and inputting it to a tracking / holding switch unit; tracking or holding the amplified differential input signal through the tracking / holding switch unit. The tracking / holding switch unit includes a first emitter follower, a holding capacitor, a shunt circuit subunit, and a first current source. The first emitter follower... The emitter is connected to the holding capacitor. The collector of the first emitter follower is connected to the power supply voltage. The base of the first emitter follower is connected to the first output terminal of the input unit. The first output terminal is used to output one of the two amplified differential input signals. The first emitter follower is used to control the circuit to switch between tracking and holding states. The shunt circuit subunit is used to shunt the current of the first current source in the tracking state. The output unit outputs the differential output signal corresponding to the differential input signal to provide driving capability for subsequent circuits. The output unit is connected to the holding capacitor.

[0080] It should be noted that the embodiments of electronic devices described in this specification and the embodiments of sample-and-hold circuits described in this specification are based on the same inventive concept. Therefore, the specific implementation of this embodiment can be referred to the implementation of the corresponding sample-and-hold circuit described above, and the repeated parts will not be described again.

[0081] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described sample-and-hold method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0082] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0083] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described sample-and-hold method embodiment, or to implement the functions of the various modules of the above-described sample-and-hold circuit or sample-and-hold device embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0084] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0085] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0086] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0087] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0088] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxesFigure 1 The steps of the function specified in one or more boxes.

[0089] In a typical configuration, an electronic device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0090] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0091] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A sample-and-hold circuit, characterized by, The sampling and holding circuit comprises an input unit, a tracking / holding switch unit and an output unit, the input unit is configured to receive a differential input signal and input the amplified differential input signal to the tracking / holding switch unit after amplification; The tracking / holding switch unit is configured to track or hold the amplified differential input signal, and the tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, wherein the emitter of the first emitter follower is connected with the holding capacitor, the collector of the first emitter follower is connected with a power supply voltage, the base of the first emitter follower is connected with a first output end of the input unit, the first output end is configured to output one of the two amplified differential input signals, the first emitter follower is configured to control the circuit to switch between tracking and holding states, and the shunt circuit subunit is configured to shunt the current of the first current source in the tracking state; The output unit is connected with the holding capacitor and configured to output a differential output signal corresponding to the differential input signal to provide driving capability for a subsequent circuit; The shunt circuit subunit comprises two switch transistors and two cascade transistors, wherein the collector of the first switch transistor is connected with the emitter of the first cascade transistor, the collector of the second switch transistor is connected with the emitter of the second cascade transistor to form two shunt circuits respectively, the base of the two switch transistors is connected with a clock input end, the emitter of the two switch transistors is connected with the first current source, the base of the two cascade transistors is connected with a bias voltage, the collector of the first cascade transistor is connected with the emitter of the first emitter follower, and the collector of the second cascade transistor is connected with the power supply voltage; The shunt circuit subunit is configured to shunt the current of the first current source in the tracking state, and the shunt circuit subunit comprises: When the signal at the clock input end is at a high level, the shunt circuit subunit is configured to control the current of the first current source to flow through the two shunt circuits respectively.

2. The sample-and-hold circuit of claim 1, wherein, When the signal at the clock input end is at a high level, the shunt circuit subunit is configured to control the current of the first current source to flow through the two shunt circuits respectively, and the shunt circuit subunit comprises: When the signal at the clock input end is at a high level, the first switch transistor, the first cascade transistor, the second switch transistor and the second cascade transistor are turned on respectively, and the current of the first current source flows through the two shunt circuits respectively, wherein the current of one of the two shunt circuits flows through the first emitter follower, so that the first emitter follower is turned on to track the amplified differential input signal.

3. The sample-and-hold circuit of claim 1, wherein, The first emitter follower is configured to control the circuit to switch between tracking and holding states, and the first emitter follower comprises: When the first emitter follower is turned on, the circuit is in the tracking state; and / or, When the first emitter follower is turned off, the circuit is in the holding state.

4. The sample-and-hold circuit of claim 3, wherein, The tracking / holding switch unit further comprises a third switch transistor and a third cascade transistor, wherein a base of the third switch transistor is connected to a clock input end, an emitter of the third switch transistor is connected to the first current source, a collector of the third switch transistor is connected to an emitter of the third cascade transistor, a base of the third cascade transistor is connected to a bias voltage, and a collector of the third cascade transistor is connected to a base of the first emitter follower; The circuit is in the holding state when the first emitter follower is turned off, and the circuit comprises: When a signal of the clock input end is a low level, the third switch transistor and the third cascade transistor are turned on respectively, the first emitter follower is turned off, and the circuit is in the holding state.

5. A sample-and-hold method characterized by, The method is applied to the sample-and-hold circuit according to any one of claims 1-4, and the method comprises: receiving a differential input signal through an input unit and inputting the amplified differential input signal into a tracking / holding switch unit; tracking or holding the amplified differential input signal through the tracking / holding switch unit, wherein the tracking / holding switch unit comprises a first emitter follower, a holding capacitor, a shunt circuit subunit and a first current source, an emitter of the first emitter follower is connected to the holding capacitor, a collector of the first emitter follower is connected to a power supply voltage, a base of the first emitter follower is connected to a first output end of the input unit, the first output end is used for outputting one of two amplified differential input signals, the first emitter follower is used for controlling the circuit to switch between tracking and holding states, and the shunt circuit subunit is used for shunting a current of the first current source in the tracking state; outputting a differential output signal corresponding to the differential input signal through an output unit to provide driving capability for a subsequent circuit, wherein the output unit is connected to the holding capacitor.

6. The method of claim 5, wherein, The shunt circuit subunit is used for shunting the current of the first current source in the tracking state, and the shunt circuit subunit comprises: controlling the current of the first current source to flow through two branches respectively through the shunt circuit subunit when a signal of a clock input end is a high level, wherein the two branches are respectively formed by a collector of a first switch transistor and an emitter of a first cascade transistor and a collector of a second switch transistor and an emitter of a second cascade transistor, the shunt circuit subunit comprises the two switch transistors and the two cascade transistors, bases of the two switch transistors are connected to the clock input end, emitters of the two switch transistors are connected to the current source, bases of the two cascade transistors are connected to a bias voltage, a collector of the first cascade transistor is connected to an emitter of the first emitter follower, and a collector of the second cascade transistor is connected to the power supply voltage.

7. The method of claim 6, wherein, The controlling the current of the first current source to flow through two branches respectively through the shunt circuit subunit when a signal of a clock input end is a high level comprises: When the signal at the clock input is high, the first switch transistor, the first cascade transistor, the second switch transistor and the second cascade transistor are all turned on, respectively, and the current source current flows through the two branches, respectively, wherein the current in one of the two branches flows through the first emitter follower, so that the first emitter follower is turned on to track the amplified differential input signal.

8. The method of claim 5, wherein, The first emitter follower is configured to control the circuit to switch between a tracking state and a holding state, and the control comprises: controlling the circuit to be in the tracking state when the first emitter follower is turned on; and / or controlling the circuit to be in the holding state when the first emitter follower is turned off. The controlling the circuit to be in the holding state when the first emitter follower is turned off comprises:

9. The method of claim 8, wherein, when the signal at the clock input is low, the third switch transistor and the third cascade transistor are turned on, respectively, the first emitter follower is turned off, and the circuit is controlled to be in the holding state, wherein the tracking / holding switch unit further comprises the third switch transistor and the third cascade transistor, the base of the third switch transistor is connected to the clock input, the emitter of the third switch transistor is connected to the first current source, the collector of the third switch transistor is connected to the emitter of the third cascade transistor, the base of the third cascade transistor is connected to a bias voltage, and the collector of the third cascade transistor is connected to the base of the first emitter follower. ​

Images