Block size limit for DMVR

Abstract

Block size limitations for DMVR are described. A method of video processing is provided that includes performing a conversion between a video block and a bitstream for the video block based on at least one of a width and a height of the video block, refraining from applying a decoder-side motion vector refinement step during the conversion in response to a width-to-height ratio (W / H) being less than a first threshold, and refraining from applying the decoder-side motion vector refinement step during the conversion in response to the width-to-height ratio (W / H) being greater than a second threshold, where W and H are the width and the height of the video block, respectively, and where the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion.

Description

[0001] Cross Reference to Related Applications

[0002] This application is a continuation of Chinese Patent Application No. 201910590860.8, filed on July 2, 2019, which claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 693,412, filed on July 2, 2018. The entire disclosure of International Patent Application No. 62 / 693,412 is incorporated by reference as part of the disclosure of this application. TECHNICAL FIELD

[0003] This document relates to video coding techniques. BACKGROUND

[0004] Despite advances in video compression, digital video occupies the largest bandwidth use on the Internet and other digital communication networks. As the number of connected user devices that can receive and display video increases, the bandwidth demand for digital video usage is expected to continue to grow. SUMMARY

[0005] Techniques related to decoder-side motion vector derivation (DMVD) in video coding are disclosed. It can be applied to existing video coding standards (e.g., HEVC) or standards to be finalized (Versatile Video Coding (VVC). It can also be applied to future video coding standards or video codecs.

[0006] In one example aspect, a method of video processing is disclosed. The method includes determining a video block size width (W) and height (H) based on a condition of the video block; making a decision between enabling and disabling a decoder-side motion vector refinement step for a conversion between the video block and an encoded representation of the video block; conducting the conversion by enabling the decoder-side motion vector refinement step if the decision is to enable; and conducting the conversion by disabling the decoder-side motion vector refinement step if the decision is to disable, wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the encoded representation, and using the refined value during the conversion.

[0007] In another example aspect, a video decoding device is disclosed, including a processor configured to implement the above method.

[0008] In yet another example, a video encoding device is disclosed, including a processor configured to implement the above method.

[0009] In yet another example, a computer readable medium is disclosed. The medium stores code that, when executed by a processor, causes the processor to implement the above method.

[0010] In yet another example aspect, a method of video processing is provided that includes performing a conversion between the video block and a bitstream of the video block based on at least one of a width and a height of the video block, refraining from applying a decoder-side motion vector refinement step during the conversion in response to a width-to-height ratio (W / H) being less than a first threshold, and refraining from applying the decoder-side motion vector refinement step during the conversion in response to the width-to-height ratio (W / H) being greater than a second threshold, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion.

[0011] In yet another example aspect, an apparatus for coding video data is provided that includes a processor and a non-transitory memory having instructions embodied thereon, wherein the instructions, when executed by the processor, cause the processor to perform a conversion between the video block and a bitstream of the video block based on at least one of a width and a height of the video block, refrain from applying a decoder-side motion vector refinement step during the conversion in response to a width-to-height ratio (W / H) being less than a first threshold, and refrain from applying the decoder-side motion vector refinement step during the conversion in response to the width-to-height ratio (W / H) being greater than a second threshold, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion.

[0012] In yet another example aspect, a non-transitory computer-readable storage medium storing instructions that cause a processor to perform a conversion between the video block and a bitstream of the video block based on at least one of a width and a height of the video block, refrain from applying a decoder-side motion vector refinement step during the conversion in response to a width-to-height ratio (W / H) being less than a first threshold, and refrain from applying the decoder-side motion vector refinement step during the conversion in response to the width-to-height ratio (W / H) being greater than a second threshold, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein the decoder-side motion vector refinement step is disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

[0013] In yet another example aspect, a non-transitory computer-readable storage medium storing a bitstream of a video generated by a method performed by a video processing device is provided, wherein the method comprises: generating the bitstream based on at least one of a width and a height of a video block; responsive to a width-to-height ratio (W / H) being less than a first threshold, refraining from applying a decoder-side motion vector refinement step during the conversion; and responsive to the width-to-height ratio (W / H) being greater than a second threshold, refraining from applying the decoder-side motion vector refinement step during the conversion, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder-side motion vector refinement step comprises refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion.

[0014] These and other aspects are further described in the present document. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 An example of decoder-side motion vector refinement (DMVR) based on bilateral template matching is shown.

[0016] Figure 2 is a flowchart of an example method according to some example embodiments.

[0017] Figure 3 is an example of a block diagram of a video decoding and / or encoding device. DETAILED DESCRIPTION

[0018] Various techniques are provided herein that can be used by a decoder of a video bitstream to improve the quality of decompressed or decoded digital video. Furthermore, a video encoder can also implement these techniques during the encoding process in order to reconstruct decoded frames for further encoding.

[0019] The use of section headings in this document is for convenience only and should not be taken as limiting the embodiments and techniques to the particular sections where they are discussed. Similarly, examples from one section can be combined with examples from other sections.

[0020] Technical Framework

[0021] Video coding standards have evolved mainly through the development of the well-known ITU-T and ISO / IEC standards. The ITU-T produced H.261 and H.263, ISO / IEC produced MPEG-1 and MPEG-4 Visual, and the two organizations jointly produced the H.262 / MPEG-2 Video and H.265 / HEVC standards. From H.262 onwards, the video coding standards are based on the hybrid video coding structure, where temporal prediction plus transform coding are used. To explore future video coding technologies beyond HEVC, the Joint Video Exploration Team (JVET) was founded by VCEG and MPEG jointly in 2015. Since then, many new methods have been adopted by the JVET and put into the reference software named Joint Exploration Test Model (JEM). In April 2018, the Joint Video Team (JVT) was created between VCEG (Q6 / 16) and ISO / IEC JTC1 SC29 / WG11 (MPEG) to work on the VVC standard with the goal of a 50% bitrate reduction compared to HEVC.

[0022] Inter prediction in HEVC / H.265

[0023] Each inter predicted prediction unit (PU) has motion parameters for one or two reference picture lists. The motion parameters include motion vectors and reference picture indices. The use of one of the two reference picture lists can also be signaled using inter_pred_idc. Motion vectors can be explicitly coded as a delta with respect to a predictor.

[0024] When a coding unit (CU) is coded with skip mode, one PU is associated with the CU and there are no significant residual coefficients, no coded motion vector delta or reference picture indices. Merge mode is specified, which derives the motion parameters of the current PU from neighboring (one or more) PUs, including spatial and temporal candidates. Merge mode can be applied to any inter predicted PU, not only for skip mode. An alternative to merge mode is the explicit transmission of motion parameters, where the motion vector (more precisely, the motion vector difference compared to a motion vector predictor), and for each reference picture list and reference picture list used, the corresponding reference picture index are explicitly signaled for each PU. This mode is referred to as advanced motion vector prediction (AMVP) in this text.

[0025] When signaled that one of the two reference picture lists will be used, the PU is generated from a block of samples. This is referred to as ‘uni-prediction’. Uni-prediction can be used for both P-slices and B-slices.

[0026] When the signaling indicates that both reference picture lists will be used, the PU is generated from two blocks of samples. This is referred to as 'bi-prediction'. Bi-prediction is only available for B-slices.

[0027] In bilateral matching merge mode, bi-prediction is always applied because the motion information for the CU is derived based on the closest match of the two blocks along the motion trajectory of the current CU in two different reference pictures. There is no such restriction for template matching merge mode. In template matching merge mode, the encoder can choose among uni-prediction from list 0, uni-prediction from list 1 or bi-prediction for a CU. The choice is based on the following template matching cost:

[0028]

[0029]

[0030] where costO is the SAD of listO template matching, costi is the SAD of listi template matching, and costBi is the SAD of bi-prediction template matching. The value of the factor is equal to 1.25, which means that the selection process is biased towards bi-prediction.

[0031] Inter prediction direction selection is only applied to the CU level template matching process.

[0032] Decoder side motion vector refinement

[0033] In bi-prediction operation, for the prediction of a block region, two prediction blocks formed using the motion vector (MV) of listO and the MV of listi respectively are combined to form a single prediction signal. In the decoder side motion vector refinement (DMVR) method, the two motion vectors of bi-prediction are further refined by a bilateral template matching process. The bilateral template matching is applied in the decoder to perform a distortion-based search between the bilateral template and the reconstructed samples in the reference pictures in order to obtain the refined MVs without the need to transmit additional motion information.

[0034] As Figure 1As shown, in DMVR, a bilateral template is generated as a weighted combination (i.e., average) of two prediction blocks from the initial MV0 in List 0 and MV1 in List 1, respectively. The template matching operation includes computing a cost metric between the generated template and a sample region in the reference picture (surrounding the initial prediction block). For each of the two reference pictures, the MV that produces the minimum template cost is considered as the updated MV for that list to replace the original MV. In JEM, for each list, nine MV candidates are searched. The nine MV candidates include the original MV and eight surrounding MVs that have one luma sample offset in the horizontal direction or in the vertical direction or both relative to the original MV. Finally, the two new MVs (i.e., MV0' and MV1' as shown) are used to generate the final bi-prediction result. Sum of absolute difference (SAD) is used as the cost metric. Note that when computing the cost of a prediction block generated by a surrounding MV, the rounded MV (rounded to integer pixels) is actually used to obtain the prediction block instead of the true MV. Figure 1

[0035] DMVR is applied to the bi-predictive merge mode where one MV comes from a past reference picture and the other MV comes from a future reference picture without the need to transmit extra syntax elements. In JEM, DMVR will not be applied when LIC, affine motion, FRUC, or sub-CU merge candidate is enabled for a CU.

[0036] In some example embodiments, as shown, in a first step: a bilateral template is generated from the prediction blocks referred by the initial MV0 and MV1; and in a second step: a bilateral template matching is performed to find the best matching blocks referred by the updated MV0' and MV1'. Figure 1

[0037] The techniques and apparatuses of the present disclosure reduce complexity and improve the coding performance of the DMVD method.

[0038] In one aspect, the cost (e.g., difference, distortion, or cost that considers both distortion and MV) between the template and the candidate blocks is computed only for fractional pixels in the decoder-side motion estimation (i.e., in the motion information derivation or refinement process). In another aspect, for DMVR, the interpolation time is reduced. In another aspect, some embodiments using the disclosed techniques apply DMVR to the AMVP mode. In another aspect, for different block sizes, the weighting factor of the MV difference can be different.

[0039] ​​The following enumerated examples provide some approaches by which the techniques of this disclosure can be implemented as a video encoding or decoding process. Let prec denote the motion vector precision, when prec equals N, it means the motion vector has 1 / 2^N pel precision. N can be a positive integer, zero or negative integer.

[0040] The DMVR method can be enabled / disabled according to certain conditions.

[0041] In one aspect, the enabling or disabling of DMVR can depend on the block size and / or block shape. The block size can be denoted as W x H, where W is the width of the block and H is the height. The following rules can apply:

[0042] a. In one example, for block size equal to 4x4, DMVR can be disabled all the time.

[0043] b. In another example, for block size equal to Wx4 or 4xH, H is an integer value greater than or equal to 1, DMVR can be disabled all the time.

[0044] c. In another example, for block WxH, where W<=T1 or H<=T2, W, H, T1 and T2 are integer values greater than or equal to 1, DMVR can be disabled all the time.

[0045] d. In another example, for block WxH, where W<=T1 and H<=T2, W, H, T1 and T2 are integer values greater than or equal to 1, DMVR can be disabled all the time.

[0046] e. In another example, for block WxH, where W*H<=TO, where W, H and TO are integer values greater than or equal to 1, DMVR can be disabled all the time.

[0047] f. In another example, if W / H is less than a threshold, and / or W / H is greater than a threshold, DMVR can be disabled all the time. The threshold(s) can be signaled or predefined (e.g., equal to 1). W and H are integer values, and the threshold can be expressed as a fraction.

[0048] Figure 2is a flowchart of an example method 200 of video processing. The method 200 can be used, for example, to disable or enable a decoder-side motion vector refinement (DMVR) video decoder or encoder. The method 200 includes determining (202) a video block size width (W) and height (H), deciding to disable the DMVR video decoder when a condition is met and to enable the DMVR video decoder when the condition is not met, and decoding a bitstream into a data block based on the decision. For example, the method 200 can include, at 204, making the decision between enabling and disabling DMVR steps during a conversion between a video block and an encoded representation of the video block. After the decision, at 206, the conversion between the video block and the encoded representation is performed. The conversion is performed using one of a first mode and a second mode, where in the first mode the decision is to enable DMVR, in which case the conversion is performed by enabling DMVR, and in the second mode the decision is to disable DMVR, in which case the conversion is performed by disabling DMVR. For example, the conversion refers to an encoding or transcoding operation that generates the encoded representation (e.g., a bitstream). Alternatively, the conversion can result in generating sample values of the video block from the encoded representation. Various possible embodiments and variants of the above method, where the condition is met due to one of the following rules:

[0049] The condition is met because the block size has W = 4 and H = 4.

[0050] The condition is met because the block size has H = 4 or W = 4.

[0051] The condition is met because the block size has W <= T1 or H <= T2.

[0052] The condition is met because the block size has W <= T1 and H <= T2.

[0053] The condition is met because the block size has W*H <= T0.

[0054] The condition is met because the block size has W / H is less than a first threshold and W / H is greater than a second threshold.

[0055] The condition is met because the block size has W / H is less than a threshold or W / H is greater than another threshold.

[0056] In the above, the thresholds T0, T1 and T2 can be fixed values independent of the conversion process. For example, T1 and T2 can be 4 or 8 and can be pre-specified and known to the encoder and decoder.

[0057] In the above description, various thresholds used can represent the aspect ratio of the current block. For example, a threshold can be set to 1, such that wide blocks (W > H) can use DMVR, while tall blocks (W <= H) can disable DMVR. Because motion is generally more accurately perceived in the horizontal direction, such an arrangement can help the visual quality of the coded representation to be at a higher level than otherwise.

[0058] The first threshold and the second threshold are received via a message. The message can be included in a syntax element of the coded representation. The syntax element can be inserted on a slice-by-slice or picture-by-picture basis to allow changing the thresholds at a picture or slice or coding unit level.

[0059] In some embodiments, the decoding condition comprises selecting a low precision motion vector, and wherein generating the set of candidate blocks comprises generating the set of candidate blocks using the low precision motion vector. In some embodiments, when the decoding condition is that the current block is in merge mode, the motion vector is inherited by the current block. In different modes, the precision can be increased by refining using a step size or a scale factor. For example, the step size can be 1. As another example, the scale factor can be 2, and the precision can be increased from 4-pixel resolution to 2-pixel resolution to 1 -pixel resolution, etc.

[0060] Figure 3A block diagram showing an example embodiment of a hardware device 300 that can be used to implement various portions of the technology disclosed herein is shown. The hardware device 300 can be a laptop, a smartphone, a tablet, a camcorder, or other type of device capable of processing video. The device 300 includes a processor or controller 302 for processing data, and a memory 304 in communication with the processor 302 to store and / or buffer data. For example, the processor 302 can include a central processing unit (CPU) or a microcontroller unit (MCU). In some implementations, the processor 302 can include a field programmable gate array (FPGA). In some implementations, the device 300 includes or is in communication with a graphics processing unit (GPU), a video processing unit (VPU), and / or a wireless communication unit for various visual and / or communication data processing functions of a smartphone device. For example, the memory 304 can include and store processor-executable code that, when executed by the processor 302, configures the device 300 to perform various operations, such as receiving information, commands, and / or data, processing the information and data, and sending or providing the processed information / data to another device, such as an actuator or an external display. To support the various functions of the device 300, the memory 304 can store information and data, such as instructions, software, values, images, and other data processed or referenced by the processor 302. For example, various types of random access memory (RAM) devices, read-only memory (ROM) devices, flash memory devices, and other suitable storage media can be used to implement the storage functions of the memory 304. The device 300 can also include a dedicated video processing circuit 306 for performing repetitive computational functions, such as transforms and decodes.

[0061] The technology described herein can be implemented by a video encoder or a video decoder using a hardware platform such as described with respect to Figure 3 FIG. 1.

[0062] From the foregoing, it will be appreciated that specific embodiments of the technology herein have been described for purposes of illustration, and that various modifications can be made without deviating from the scope of the application. Accordingly, the technology disclosed herein is not limited except as by the appended claims.

[0063] The disclosed and other embodiments, modules and the functional operations described herein can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or in combinations of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also include, in addition to a hardware part, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. The propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.

[0064] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and are interconnected by a communication network.

[0065] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0066] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0067] Although the present patent document contains many details, these should not be construed as limiting the scope of any invention or of the scope of patentable subject matter in which an invention resides, but as a description of features that can be part of particular embodiments of the invention. In this patent document, certain features that are described in the context of separate embodiments can also be implemented in combination with each other. Conversely, various features that are described in the context of a single embodiment can also be implemented on a stand-alone basis or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0068] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor that all illustrated operations be performed, to achieve desirable results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0069] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A method of video processing, comprising: performing a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block; in response to a ratio of a width W of the video block to a height H of the video block being less than a first threshold, refraining from applying a decoder-side motion vector refinement step during the conversion; and in response to the ratio being greater than a second threshold, refraining from applying the decoder-side motion vector refinement step during the conversion, wherein the decoder-side motion vector refinement step comprises refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion. the conversion comprises decoding the bitstream into pixel values of the video block.

2. The method of claim 1, wherein, the conversion comprises encoding pixel values of the video block into the bitstream.

3. The method of claim 1, wherein, when W <= Tl or H <= T2, determining to disable the decoder-side motion vector refinement step, wherein Tl is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

4. The method of claim 1, wherein, when W <= Tl and H <= T2, determining to disable the decoder-side motion vector refinement step, wherein Tl is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

5. The method of claim 1, wherein, the decoder-side motion vector refinement step is applied in a sub-block level.

6. The method of claim 1, wherein, when W*H <= TO, determining to disable the decoder-side motion vector refinement step, wherein TO is a fifth threshold, and TO is an integer value greater than or equal to 1.

7. The method of claim 1, wherein, when W = 4 and H = 4, determining to disable the decoder-side motion vector refinement step.

8. The method of claim 1, wherein, when W = 4 or H = 4, determining to disable the decoder-side motion vector refinement step.

9. The method of claim 1, wherein, the first threshold and the second threshold have fixed values.

10. The method of claim 1, wherein, the second threshold is equal to 8, and 11. The method of claim 1, wherein, wherein, in response to an affine mode being applied to a current block, the decoder-side motion vector refinement step is refrained from being applied to the current block.

12. An apparatus for coding video data, comprising a processor and a non-transitory memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to: perform a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block; in response to a ratio of a width W of the video block to a height H of the video block being less than a first threshold, refrain from applying a decoder-side motion vector refinement step during the conversion; and in response to the ratio being greater than a second threshold, refrain from applying the decoder-side motion vector refinement step during the conversion, the decoder-side motion vector refinement step comprises refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion. wherein, the conversion comprises decoding the bitstream into pixel values of the video block.

13. The apparatus of claim 12, wherein, the conversion comprises encoding pixel values of the video block into the bitstream.

14. The apparatus of claim 12, wherein, when W <= Tl or H <= T2, determining to disable the decoder-side motion vector refinement step, wherein Tl is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

15. The apparatus of claim 12, wherein, ​ 16. The apparatus of claim 12, wherein, when W <= T1 or H <= T2, it is determined to disable the decoder-side motion vector refinement step, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

17. The apparatus of claim 12, wherein, The decoder-side motion vector refinement step is applied in a sub-block level.

18. The apparatus of claim 12, when W*H <= TO, it is determined to disable the decoder-side motion vector refinement step, wherein TO is a fifth threshold, and TO is an integer value greater than or equal to 1.

19. A non-transitory computer-readable storage medium storing instructions that cause a processor to: perform a conversion between a video block and a bitstream for the video block based on at least one of a width and a height of the video block; in response to a ratio of a width W of the video block to a height H of the video block being less than a first threshold, refrain from applying a decoder-side motion vector refinement step during the conversion; and in response to the ratio being greater than a second threshold, refrain from applying the decoder-side motion vector refinement step during the conversion, wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein when W <= T1 or H <= T2, it is determined to disable the decoder-side motion vector refinement step, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

20. A non-transitory computer-readable storage medium storing a bitstream of a video generated by a method performed by a video processing device, wherein the method comprises: generating the bitstream based on at least one of a width and a height of a video block; in response to a ratio of a width W of the video block to a height H of the video block being less than a first threshold, refraining from applying a decoder-side motion vector refinement step during the generation; and in response to the ratio being greater than a second threshold, refraining from applying the decoder-side motion vector refinement step during the generation, wherein the decoder-side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the generation. ​

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