Chip design testing method, system, medium, device and FPGA prototype verification platform

Abstract

The application provides a chip design test method, system, medium, equipment and FPGA prototype verification platform; the FPGA prototype verification platform comprises at least two verification blocks; each verification block comprises a control FPGA and a test FPGA; the control FPGA is connected with the test FPGA and is used for controlling the test FPGA to test the design of a chip; the FPGA prototype verification platform is divided into resources, a plurality of users can be simultaneously provided with a design verification environment, the waste of the FPGA prototype verification platform resources is effectively avoided, the verification efficiency of the customer is improved, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip design testing, and particularly relates to a chip design testing method, system, medium, equipment and FPGA prototype verification platform. BACKGROUND

[0002] With the development of integrated circuits, the scale of integrated circuits is increasing, and the function modules of systems are becoming more and more complex. The large design scale and complex functions make the design more rigorous and standardized, and small errors can cause the failure of tape-out and the extension of the delivery cycle. Therefore, the test and verification of integrated circuits are crucial.

[0003] Based on the inherent limitations of pure software and dynamic simulation technology and formal verification technology, it is determined that some chip design errors cannot be found by dynamic function simulation, because the speed of simulation cannot be compared with the speed of actual chip operation, and the FPGA system can meet this requirement.

[0004] Therefore, compared with software simulation, the FPGA-based prototype verification system not only accelerates the development of ASIC and other designs, shortens the research and development cycle, and reduces the development cost of ASIC application systems, but also has the advantages of fast simulation speed, allowing designers to perform real operations on the platform, and improving the success rate of chip tape-out.

[0005] However, due to the uniqueness of the prototype verification platform, we do not need all FPGA resources to verify our design many times, which will cause resource waste. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a chip design testing method, system, medium, equipment and FPGA prototype verification platform, which is used to solve the problem of resource waste existing in the prior art FPGA prototype verification platform.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides an FPGA prototype verification platform, comprising: at least two verification blocks; each of the verification blocks comprises a control FPGA and a test FPGA; the control FPGA is connected with the test FPGA, and is used to control the test FPGA to test the design of a chip.

[0008] In an embodiment of the present application, the FPGA prototype verification platform further comprises: at least one sub-control FPGA; at least two of the verification blocks are connected to form a multi-board FPGA; one of the multi-board FPGAs corresponds to one of the sub-control FPGAs; the sub-control FPGA is connected with the multi-board FPGA to form a verification unit; and the number of the verification units is at least two.

[0009] In an embodiment of the present application, at least one of the verification units forms a first verification unit group; at least one second verification unit group is formed by the verification units other than those in the first verification unit group; the number of verification units in the second verification unit group and the connection relationship between the verification units are the same as those in the first verification unit group, or when the number of verification units is at least three, any two of the verification units form a third verification unit group.

[0010] In an embodiment of the present application, the FPGA prototype verification platform further comprises a master control FPGA; the master control FPGA is connected with the verification units.

[0011] A chip design testing method applied to an electronic device, comprising the following steps: obtaining to-be-tested data based on a chip; sending the to-be-tested data to a target position on the FPGA prototype verification platform based on an environment configuration file in the to-be-tested data, so that the FPGA prototype verification platform tests the design of the chip based on the to-be-tested data; the environment configuration file is used for configuring the target position.

[0012] In an embodiment of the present application, the method further comprises the following steps: after the step of sending the to-be-tested data to the target position, in response to receiving feedback information sent by the FPGA prototype verification platform, determining that the target position is occupied; in response to the target position being occupied, modifying the environment configuration file to change the target position; sending the to-be-tested data to the changed target position, so that the FPGA prototype verification platform tests the design of the chip based on the to-be-tested data; the changed target position is located on the FPGA prototype verification platform.

[0013] In an embodiment of the present application, the step of obtaining to-be-tested data based on a chip comprises the following steps: obtaining the to-be-tested data based on the current resource usage of the chip and the FPGA prototype verification platform; the current resource usage at least comprises occupied positions on the FPGA prototype verification platform and / or idle positions on the FPGA prototype verification platform; the target position belongs to the idle positions.

[0014] The present application provides a storage medium having a computer program stored thereon, which is executed by a processor to implement the chip design testing method described above.

[0015] The present application provides an electronic device comprising a processor and a memory; the memory is used for storing a computer program; the processor is used for executing the computer program stored in the memory, so that the electronic device executes the chip design testing method described above.

[0016] The application provides a chip design test system, comprising the electronic device and the FPGA prototype verification platform.

[0017] As described above, the chip design test method, system, medium, device and FPGA prototype verification platform have the following beneficial effects:

[0018] (1) Compared with the prior art, the application provides an FPGA prototype verification platform suitable for multiple users, which can provide a design verification environment for multiple users at the same time by segmenting the resources of the FPGA prototype verification platform, thereby effectively avoiding waste of resources of the FPGA prototype verification platform, improving verification efficiency of customers, and reducing costs.

[0019] (2) The application connects multiple verification blocks to form a verification unit, so that the verification unit can realize verification test of complex SOC / ASIC design, and by planning reasonable FPGA resources for each design according to different requirements of different design gate levels, multiple users can access and operate the FPGA prototype verification platform, and multiple designs can be verified at the same time.

[0020] (3) The application designs the connection relationship between the verification units, so that when the configured target position is occupied, the design of the chip can be verified by modifying the environment configuration file and using other idle positions on the FPGA prototype verification platform, and the verification result is not affected. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A structure schematic diagram of a terminal of the application in an embodiment is shown.

[0022] Figure 2 A structure schematic diagram of an FPGA prototype verification platform of the application in an embodiment is shown.

[0023] Figure 3 A structure schematic diagram of an FPGA prototype verification platform of the application in another embodiment is shown.

[0024] Figure 4 A structure schematic diagram of an FPGA prototype verification platform of the application in still another embodiment is shown.

[0025] Figure 5 A structure schematic diagram of an FPGA prototype verification platform of the application in yet another embodiment is shown.

[0026] Figure 6FIG. 3 shows a structural schematic diagram of the FPGA prototype verification platform according to an embodiment of the present application.

[0027] Figure 7 FIG. 4 shows a flowchart of the chip design testing method according to an embodiment of the present application.

[0028] Figure 8 FIG. 5 shows a flowchart of the chip design testing method according to an embodiment of the present application when the target position is occupied.

[0029] Figure 9 FIG. 6 shows a structural schematic diagram of the chip design testing system according to an embodiment of the present application.

[0030] Label Explanation

[0031] 1 terminal

[0032] 11 processing unit

[0033] 12 memory

[0034] 121 random access memory

[0035] 122 cache memory

[0036] 123 storage system

[0037] 124 program / utility

[0038] 1241 program module

[0039] 13 bus

[0040] 14 input / output interface

[0041] 15 network adapter

[0042] 2 external device

[0043] 3 display

[0044] 21 verification block

[0045] 211 control FPGA

[0046] 212 test FPGA

[0047] 22 sub-control FPGA

[0048] 23 multi-board FPGA

[0049] 24 verification unit

[0050] 25 first verification unit group

[0051] 26 second verification unit group

[0052] 27 master FPGA

[0053] 91 electronic device

[0054] 92 FPGA prototype verification platform

[0055] S71-S72 steps

[0056] S81-S83 steps DETAILED DESCRIPTION

[0057] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is contemplated that the application described herein will be practiced with variation of the procedure which, if not explicitly described, will become apparent to those skilled in the art in light of the description herein. It is also contemplated that various embodiments described herein will be practiced with different combinations of the features described herein, and that the features described herein can be combined with other features not expressly described herein, without departing from the spirit of the application.

[0058] It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the application should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with their full scope of equivalents. Various modifications and changes can be made thereto by those skilled in the art without departing from the spirit and scope of the application, which is defined by the following claims. For example, the steps recited in any of the methods or processes can be performed in a different order than those which are described herein. Also, the elements recited in any of the various claims can be combined in a different manner than is recited in the claims.

[0059] Compared with the prior art, the chip design test method, system, medium, device and FPGA prototype verification platform of the present application provide an FPGA prototype verification platform suitable for multiple users. By segmenting the resources of the FPGA prototype verification platform, the design verification environment can be provided for multiple users at the same time, thereby effectively avoiding the waste of resources of the FPGA prototype verification platform, improving the verification efficiency of the customers, and reducing the cost. The present application connects multiple verification blocks to form a verification unit, so that the verification unit can realize the verification test of a complex SOC / ASIC design. According to different requirements of different design gate levels, reasonable FPGA resources are planned for each design, which also allows multiple users to access and operate the FPGA prototype verification platform, so that multiple designs can be verified at the same time. The connection relationship between the verification units is designed, so that when the target position is occupied, the design of the chip is verified by modifying the environment configuration file and using other idle positions on the FPGA prototype verification platform, and the verification result is not affected.

[0060] The storage medium of the present application stores a computer program, which, when executed by a processor, implements the chip design test method described below. The storage medium includes: a read-only memory (ROM), a random access memory (RAM), a magnetic disk, a U disk, a memory card, or an optical disk, and various media that can store program codes.

[0061] Any combination of one or more storage media can be employed. The storage media can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0062] The computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program codes are carried. Such a propagated data signal can take on many forms, including but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium that can send, propagate, or transmit the program for use by or in connection with an instruction execution system, apparatus, or device.

[0063] The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination of the above.

[0064] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0065] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0066] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0067] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0068] The electronic device of the present application includes a processor and a memory.

[0069] The memory is used for storing a computer program; preferably, the memory comprises: ROM, RAM, a disk, a U disk, a memory card or an optical disk and various media capable of storing program codes.

[0070] The processor is connected with the memory, and is used for executing the computer program stored in the memory, so that the electronic device executes the chip design test method.

[0071] Preferably, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP) and the like; and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0072] In an embodiment, the electronic device comprises a terminal and / or a server.

[0073] Figure 1 A block diagram of an exemplary terminal 1 suitable for implementing embodiments of the present application is shown.

[0074] Figure 1 The terminal 1 shown is merely an example and should not limit the function and scope of use of embodiments of the present application.

[0075] As shown in Figure 1 , the terminal 1 is in the form of a general-purpose computing device. The components of the terminal 1 can include, but are not limited to, one or more processors or processing units 11, a memory 12, a bus 13 connecting different system components, including the memory 12 and the processing unit 11.

[0076] Bus 13 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MCA) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0077] Terminal 1 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by Terminal 1, including volatile and non-volatile media, removable and non-removable media.

[0078] Memory 12 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 121 and / or cache memory 122. Terminal 1 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 123 may be used to read and write non-removable, non-volatile magnetic media (… Figure 1 Not shown; usually referred to as a "hard drive"). Although Figure 1 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 13 via one or more data media interfaces. Memory 12 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0079] A program / utility 124 having a set (at least one) of program modules 1241 may be stored, for example, in memory 12. Such program modules 1241 include—but are not limited to—an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 1241 typically perform the functions and / or methods described in the embodiments of the present invention.

[0080] Terminal 1 can also communicate with one or more external devices 2 (e.g., keyboard, pointing device, display 3, etc.), and with one or more devices that enable a user to interact with terminal 1, and / or with any device that enables terminal 1 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed through input / output (I / O) interface 14. Furthermore, terminal 1 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 15. Figure 1 As shown, network adapter 15 communicates with other modules of terminal 1 via bus 13. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with terminal 1, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0081] like Figure 2 As shown, in one embodiment, the FPGA prototype verification platform of the present invention includes at least two verification blocks 21 (to... Figure 2 (This will be illustrated using two verification blocks, 21 as an example).

[0082] Specifically, each of the verification blocks 21 includes a control FPGA 211 and a test FPGA 212; the control FPGA 211 is connected to the test FPGA 212 and is used to control the test FPGA 212 to test the chip design.

[0083] It should be noted that sometimes the logic gate capacity of a single FPGA board can meet the user's logic requirements (for some simple SOC / ASIC designs), that is, the design of a chip can be tested through one of the above-mentioned verification blocks 21. In this invention, by setting at least two verification blocks 21, the design of at least two chips can be tested simultaneously, thereby enabling multiple users to access and operate the FPGA prototype verification platform.

[0084] Furthermore, in the field of FPGA prototyping, when the logic gate capacity of a single FPGA board cannot meet the user's logic requirements (for some complex SOC / ASIC designs), multiple FPGA boards need to be connected together, that is, multiple FPGA boards need to work together to complete the task. Specifically, FPGAs can transmit signals to each other through pin connections. However, considering the uniqueness of the FPGA prototyping platform, it is often not necessary to use all the FPGA resources on the platform to verify the design, which would result in a waste of resources.

[0085] like Figure 3As shown, in an embodiment, the FPGA prototype verification platform further comprises at least one sub-control FPGA 22.

[0086] Specifically, at least two of the verification blocks 21 are connected to form a multi-board FPGA 23 (as shown in Figure 3 For example, the multi-board FPGA 23 corresponds to one of the sub-control FPGAs 22; and the sub-control FPGA 22 is connected to the multi-board FPGA 23 to form a verification unit 24.

[0087] It should be noted that the number of the verification units 24 is at least two (for example, two verification units 24 are included in Figure 3 Specifically, each verification unit 24 is used for verifying a design, and two verification units 24 can be used for verifying two designs.

[0088] Further, when one verification unit 24 is needed for verifying a design, each of the verification units 24 on the FPGA prototype verification platform can be used; of course, it is also possible that more than one verification unit 24 is needed for verifying a design.

[0089] As shown in Figure 4 , in an embodiment, when the number of the verification units 24 is at least three (for example, four verification units 24 are included in Figure 4 , which correspond to the verification unit A, the verification unit B, the verification unit C, and the verification unit D in Figure 4 , respectively), any two of the verification units 24 form a third verification unit group, that is, any two of the verification units 24 form a third verification unit group, and another third verification unit group formed by any other two of the verification units 24 has the same function, which can be used for verifying the same design.

[0090] Specifically, if the verification unit A and the verification unit B in Figure 4 are used for verifying a design, but the verification unit A is occupied by another design, then the verification unit B and the verification unit C, or the verification unit B and the verification unit D, or the verification unit C and the verification unit D can be selected to verify the design.

[0091] It should be noted that, considering the layout and actual production, Figure 4 , the design is relatively complex in layout.

[0092] As shown in Figure 5As shown, in an embodiment, at least one of the verification units 24 forms a first verification unit group 25; and the verification units 24 other than those in the first verification unit group 25 form at least one second verification unit group 26; the number of verification units 24 in the second verification unit group 26 and the connection relationship between the verification units 24 are the same as those in the first verification unit group 25.

[0093] Specifically, in the embodiment, the first verification unit group 25 and the second verification unit group 26 each include two verification units 24. Figure 5 Figure 5 Specifically, in the embodiment, the first verification unit group 25 and the second verification unit group 26 each include two verification units 24.

[0094] It should be noted that the first verification unit group 25 and the second verification unit group 26 can be used for verifying a design; when the first verification unit group 25 is used to verify the design, if the first verification unit group 25 is occupied by other designs, any second verification unit group 26 can be used to verify the design; specifically, by designing the verification units 24 in the first verification unit group 25 and the second verification unit group 26, when the first verification unit group 25 is replaced by the second verification unit group 26, the verification result will not be affected.

[0095] In the embodiment, by designing the number of verification units 24 and the wiring mode in the first verification unit group 25 and the second verification unit group 26, it is ensured that the second verification unit group 26 and the first verification unit group 25 can be replaced at will.

[0096] It should be noted that, Figure 5 the design in the embodiment is compared with Figure 4 In actual production, the wiring is simpler.

[0097] As shown in FIG. 2, the verification unit E, the verification unit F, the verification unit G, the verification unit H, the verification unit I, and the verification unit J are all the verification units 24. Figure 5 ​As shown, in an embodiment, on the FPGA prototype verification platform, each minimum unit formed by cascading a plurality of FPGAs is called a verification unit, and it is assumed that user Xiao Wang uses verification unit E and verification unit F for the first time when he performs design verification, and user Xiao Wang finds that verification unit E and verification unit F have been occupied by user Xiao Liu when he performs design verification next time, at which time user Xiao Wang can use verification unit G and verification unit H to perform verification, and each time of design verification can not occupy all FPGA resources in the verification unit, in order to ensure that the test using the replaced verification unit does not affect the test result, the pin connections between the internal FPGAs of each verification unit should be ensured to be completely the same during hardware design, and at the same time, when a plurality of verification units are used, the pin connections between each two verification units should also be ensured to be the same when the test using the replaced verification unit is performed, only in this way, the environment of the FPGA prototype verification platform can be ensured not to affect the verification result when the design verification using the replaced verification unit is performed.

[0098] Further, in actual production, considering which verification units 24 (corresponding to the first verification unit group 25) are prepared to be interchangeable in the finally formed FPGA prototype verification platform, the FPGA prototype verification platform is designed with corresponding hardware.

[0099] As shown in the figure, Figure 5 In an embodiment, the FPGA prototype verification platform further includes a master control FPGA 27.

[0100] Specifically, the master control FPGA 27 is connected with the verification units 24.

[0101] The working principle of the FPGA prototype verification platform of the present application will be further explained and described through specific embodiments.

[0102] As shown in the figure, Figure 6 Taking product MIMIC-32 as an example, the product uses a main controller C32 (corresponding to the master control FPGA 27) to manage 8 verification units 24 in the device, which correspond to Figure 6The verification units K, L, M, N, O, P, Q and R are cascaded in each of the verification units 24, and the pin connections between the FPGAs in each of the verification units 24 are completely identical. The eight verification units 24 are connected by a backplane, and the pin connections between the verification units K and L, the verification units M and N, the verification units O and P, and the verification units Q and R are completely identical. Therefore, when a design occupies one verification unit, any verification unit can be replaced for design verification in the second design verification. When a design occupies two verification units, the verification units K and L can be replaced by the verification units M and N, the verification units O and P, or the verification units Q and R for design verification. When a design occupies three or four verification units, the verification units K, L and M (and N) can be replaced by the verification units O, P and Q (and R) for design verification.

[0103] It should be noted that, after a design is verified by the FPGA prototype verification platform, the space occupied by the design during verification is released, so that the available space for the next design verification includes the space occupied by the design during verification.

[0104] As shown in FIG. 1, in an embodiment, the chip design testing method of the present application is applied to an electronic device, and includes the following steps: Figure 7

[0105] In step S71, the chip obtains the to-be-tested data.

[0106] Specifically, the to-be-tested data is generated by code compilation, constraint setting, RTL code synthesis, netlist file generation, layout and wiring and other operations on the design of the chip.

[0107] It should be noted that the database file includes an environment configuration file, which is used to locate the amount and specific location of FPGA resources required by the design, i.e., to configure the target location for verifying the design; for example, the target location is the verification units K and L.

[0108] In step S72, based on the environment configuration file in the to-be-tested data, the to-be-tested data is sent to the target location on the FPGA prototype verification platform, so that the FPGA prototype verification platform tests the design of the chip based on the to-be-tested data.​

[0109] Specifically, the electronic device is connected to the FPGA prototyping platform and is used to send the test data to a target location on the FPGA prototyping platform.

[0110] In one embodiment, the step of acquiring the test data based on the chip includes the following steps: acquiring the test data based on the current resource usage of the chip and the FPGA prototype verification platform.

[0111] It should be noted that the current resource usage includes, but is not limited to, occupied positions on the FPGA prototype verification platform and / or idle positions on the FPGA prototype verification platform; the target position belongs to the idle positions.

[0112] Specifically, before generating the database file, the electronic device already knows which positions on the FPGA prototyping platform are occupied and / or which positions are free. In this way, when generating the database file, the target position can be selected from the free positions, thereby ensuring that the target position is definitely a free position on the FPGA prototyping platform. This avoids the trouble of having to change the target position because it is occupied by other designs being tested, thus improving verification efficiency.

[0113] It should be noted that how the electronic device knows which positions on the FPGA prototyping platform are occupied and / or which positions are free is not a limitation of the present invention. For example, when a design occupies a certain position on the FPGA prototyping platform for verification, the FPGA prototyping platform will generate usage information and feed it back to the electronic device. The usage information includes at least the position information on the FPGA prototyping platform occupied by the design.

[0114] Furthermore, it is also possible that when the electronic device sends the data to be tested to the target location on the FPGA prototyping platform, the electronic device is unaware whether the target location is occupied because other designs are being tested.

[0115] like Figure 8 As shown, in one embodiment, after the step of sending the test data to the target location, the method further includes the following steps:

[0116] Step S81: In response to receiving feedback information sent by the FPGA prototype verification platform, determine that the target location is occupied.

[0117] Specifically, when the electronic device sends the to-be-tested data to the target position in the environment configuration file, if the target position is occupied (at this time, the target position cannot receive the to-be-tested data), the FPGA prototype verification platform generates a feedback information and sends the feedback information to the electronic device, so that the electronic device knows that the target position has been occupied after receiving the feedback information.

[0118] Step S82, in response to the target position being occupied, modifying the environment configuration file to change the target position.

[0119] It should be noted that the changed target position is located on the FPGA prototype verification platform.

[0120] Specifically, by modifying the environment configuration file in the database file, the to-be-tested data is placed in several verification units for testing, and other users can verify their own designs in other idle verification units.

[0121] Step S83, sending the to-be-tested data to the changed target position, so that the FPGA prototype verification platform tests the design of the chip based on the to-be-tested data.

[0122] It should be noted that when switching the target position for design verification, only the environment configuration file in the database file compiled by the design needs to be repositioned and can be downloaded to any required and idle available FPGA for design verification.

[0123] It should be noted that the protection scope of the chip design test method of the present application is not limited to the step execution order listed in the embodiment, and any scheme realized by adding, replacing or replacing steps of the prior art according to the principle of the present application is included in the protection scope of the present application.

[0124] As shown in Figure 9 In an embodiment, the chip design test system of the present application includes the above-mentioned electronic device 91 and the above-mentioned FPGA prototype verification platform 92.

[0125] Specifically, the electronic device 91 is connected with the FPGA prototype verification platform 92.

[0126] It should be noted that the working principle of the chip design test system is as follows:

[0127] Through operating software on the electronic device 91, the design of the chip is packaged, an environment configuration file is added, a database file is generated, and then the database file is downloaded to the corresponding FPGA through a command operation; if the FPGA resource is occupied, the database file can be replaced to other idle FPGA resources by changing the environment configuration file.

[0128] Taking the electronic device 91 as an example, the electronic device 91 includes a server.

[0129] Specifically, the server can open multiple windows for different users to use; in the present application, the resources of the FPGA prototype verification platform 92 are divided, so that when the customer tests his own design later, the server first encapsulates the customer's design by using its own software, and then adds an environment configuration file to realize control of which FPGAs the design is downloaded to, so that other idle FPGA resources can be used by other users.

[0130] The aforementioned design of connecting the verification unit pins on the FPGA prototype verification platform 92 makes a user be able to replace to other FPGAs for testing when the FPGAs are occupied by another user, and the logic between the FPGAs does not change.

[0131] It should be noted that the chip design test system of the present application can realize the chip design test method of the present application, but the implementation device of the chip design test method of the present application includes but is not limited to the structure of the chip design test system listed in the present embodiment, and any modification and replacement of the prior art structure according to the principle of the present application is included in the protection scope of the present application.

[0132] In summary, compared with the prior art, the chip design test method, system, medium, equipment and FPGA prototype verification platform provided by the present application provide an FPGA prototype verification platform suitable for multiple users, the resources of the FPGA prototype verification platform are divided, and the design verification environment can be provided for multiple users at the same time, so that the waste of resources of the FPGA prototype verification platform is effectively avoided, the verification efficiency of the customer is improved, and the cost is reduced; the multiple verification blocks are connected to form a verification unit, so that the verification unit can realize the verification test of a complex SOC / ASIC design, reasonable FPGA resources are planned for each design according to different design gate level scales, multiple users can access and operate the FPGA prototype verification platform, and multiple designs can be verified at the same time; the connection relationship between the verification units is designed, when the target position is occupied, the environment configuration file is modified, the design of the chip is verified by using other idle positions on the FPGA prototype verification platform, and it is guaranteed that the verification result will not be affected; therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0133] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An FPGA prototyping platform, characterized in that, include: At least two verification blocks; each verification block includes a control FPGA and a test FPGA; The control FPGA is connected to the test FPGA and is used to control the test FPGA to test the chip design; The FPGA prototype verification platform further includes: at least one sub-control FPGA; at least two verification blocks connected to form a multi-board FPGA; one multi-board FPGA corresponding to one sub-control FPGA; the sub-control FPGA connected to the multi-board FPGA to form a verification unit; the number of verification units is at least two. The FPGA prototype verification platform also includes a central control FPGA; the central control FPGA is connected to the verification unit.

2. The FPGA prototype verification platform of claim 1, wherein, At least one of the verification units forms a first verification unit group; among the plurality of verification units, in addition to the verification units in the first verification unit group, at least one second verification unit group is formed; the number of verification units in the second verification unit group and the connection relationship between the verification units are the same as those in the first verification unit group, or When the number of verification units is at least three, any two of the verification units form a third verification unit group.

3. A chip design testing method applied to an electronic device, characterized in that, Includes the following steps: Acquiring test data based on the chip; Based on the environment configuration file in the test data, the test data is sent to the target location on the FPGA prototype verification platform according to any one of claims 1 to 2, so that the FPGA prototype verification platform can perform testing on the chip design based on the test data; the environment configuration file is used to configure the target location.

4. The method of claim 3, wherein the test program is executed by the test program execution unit. The method further includes the following steps: After the step of sending the test data to the target location, in response to receiving feedback information sent by the FPGA prototype verification platform, it is determined that the target location is occupied; In response to the target location being occupied, the environment configuration file is modified to change the target location; The test data is sent to the modified target location so that the FPGA prototype verification platform can perform testing on the chip design based on the test data; the modified target location is located on the FPGA prototype verification platform.

5. The method of claim 3, wherein the test program is executed by the test program execution unit. The process of acquiring test data based on the chip includes the following steps: acquiring the test data based on the current resource usage of the chip and the FPGA prototype verification platform; the current resource usage includes at least: occupied positions on the FPGA prototype verification platform, and / or idle positions on the FPGA prototype verification platform; the target position belongs to the idle positions.

6. A storage medium having stored thereon a computer program, characterized in that When the computer program is executed by the processor, it implements the chip design testing method according to any one of claims 3 to 5.

7. An electronic device, comprising: include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory to cause the electronic device to perform the chip design test method according to any one of claims 3 to 5.

8. A system for testing a chip design, the system comprising: include: The electronic device as described in claim 7 and the FPGA prototype verification platform as described in any one of claims 1 to 2; The electronic device is connected with the FPGA prototyping platform. The electronic device is connected with the FPGA prototyping platform.

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