A multi-bus ad-hoc network device with a three-CPU architecture

Abstract

The application belongs to the technical field of vehicle communication, and discloses a multi-bus self-organizing network device with a three-CPU architecture, which comprises a motherboard, a first bus board, a second bus board and a third bus board; the motherboard is connected with an external power supply, and the first bus board, the second bus board and the third bus board are all connected with the motherboard. The three bus boards can realize the starting of a FlexRay bus network, and can communicate with an upper computer through the CAN bus of the bus board; a CAN bus interface and two FlexRay bus interfaces are integrated in a small space, the interaction mode of the two buses is perfect, the communication rate is high, the protection level is high, and the anti-electromagnetic interference is high; the FlexRay bus can be connected with multiple bus nodes, and can communicate with the upper computer through the CAN bus, so that the FlexRay bus communication condition can be monitored in real time and fault positioning can be performed, and the use requirements of military armored vehicles on multiple bus communication, multiple bus information interaction, complex environment and strong anti-interference are met.

Description

Technical Field

[0001] This invention belongs to the field of vehicle communication technology, and in particular relates to a multi-bus self-organizing network device with a three-CPU architecture. Background Technology

[0002] FlexRay bus is a high-speed, synchronous, deterministic bus technology with fault tolerance. It supports various network topologies, combining event-triggered and time-triggered methods, resulting in high network utilization and system flexibility. It can serve as the backbone network for the internal control network of next-generation armored vehicles. Currently, multiple systems in new armored vehicles, including weapon systems, power distribution systems, and integrated electronic information systems, utilize FlexRay bus for communication.

[0003] Currently, the utilization rate of FlexRay bus technology in the electronic control system of military armored vehicles is gradually increasing. The number of FlexRay bus network nodes is large, and a single FlexRay bus node cannot start the network. The FlexRay bus cannot be directly connected to the host computer system, and it is impossible to intuitively analyze the current status of each bus information through the computer software. Once a fault occurs, it is difficult to locate and eliminate the fault in a short time, and it may even cause the entire vehicle network bus communication failure, making the vehicle unable to be used normally.

[0004] Modern armored vehicles are equipped with both FlexRay and CAN buses. Due to the special nature of FlexRay bus network startup and the inconvenience of FlexRay bus monitoring, there is a need for a multi-bus self-organizing network device with a three-CPU architecture that can realize FlexRay bus network self-start, information exchange between the two buses, and online diagnostics of the CAN bus. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-bus self-organizing network device with a three-CPU architecture to solve the technical problems of FlexRay bus network self-starting, information exchange between two buses, and online diagnosis of CAN bus.

[0006] To achieve the above objectives, the specific technical solution of the three-CPU architecture multi-bus self-organizing network device of the present invention is as follows:

[0007] A multi-bus self-organizing network device with a three-CPU architecture includes a motherboard, a first bus board, a second bus board, and a third bus board. The motherboard is connected to an external power supply via a power connector. The first, second, and third bus boards are all connected to the motherboard. The first, second, and third bus boards are three identical bus boards, each with an independent CPU, a FlexRay bus communication module, a CAN bus communication module, and a FlexRay bus master cold start node. Each bus board communicates with an external FlexRay bus node via a FlexRay bus connector and with a host computer via a CAN bus connector. The bus boards are interconnected and communicate with each other.

[0008] The motherboard includes a power interface circuit, a power filter circuit, a power conversion circuit, a FlexRay bus interface circuit, and a CAN bus interface circuit.

[0009] The input terminal of the power interface circuit is connected to an external power source, and the output terminal is connected to the input terminal of the power filter circuit; the output terminal of the power filter circuit is connected to the input terminal of the power conversion circuit and each bus board respectively; the output terminal of the power conversion circuit is connected to each bus board.

[0010] The FlexRay bus interface circuit and the CAN bus interface circuit are respectively connected to the corresponding external buses for communication.

[0011] The motherboard's power filter circuit outputs 24V power, and the power conversion circuit outputs 5V power.

[0012] The motherboard includes a reverse protection diode D1, filter capacitors C1 to C8, resistors R20 to R25, power connector J1, power module IQDNM-140202, bus board connection base b1, bus board connection base b2, bus board connection base b3, FlexRay bus connector J3, CAN bus connector J2, capacitors C20, C22, C23, and C24.

[0013] The positive terminal of the external power supply is connected to the positive terminal of the reverse protection diode D1. The negative terminal of the reverse protection diode D1 is connected to the positive terminal of the filter capacitors C1 to C6. The negative terminal of the external power supply is connected to the negative terminal of the filter capacitors C1 to C6 via the power connector. The positive and negative terminals of the filtered power supply are connected to pins 2 and 3 of the power module IQDNM-140202, respectively. Pins 4 and 5 of the power module IQDNM-140202 are connected to pins P1-1 and P1-5 on the bus board connection bases b1, b2, and b3 via filter capacitors C7 and C8. Pins P1-1 to P1-4 and pins P1-5 to P1-8 on each bus board connection base are connected in parallel.

[0014] Power connector J1 connects to pins P1-9 and P1-15 of bus board connection bases b1, b2, and b3. Pins P1-9 to P1-14 on each bus board connection base are connected in parallel, and pins P1-15 to P1-20 are connected in parallel. Pins P2-10 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-12 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-14 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-9 to P1-15 on each bus board connection base are interconnected. Pin 0 is connected in parallel, pins P2-11 to P2-12 are connected in parallel, pins P2-13 to P2-16 are connected in parallel, and then connected to FlexRay bus connector J3; pins P2-16 on bus board connection bases b1, b2, and b3 are interconnected, pins P2-18 are interconnected, and pins P2-20 are interconnected; pins P2-13 to P2-16, P2-17 to P2-18, and P2-19 to P2-20 on each bus board connection base are connected in parallel, and then connected to FlexRay bus connector J3;

[0015] Resistors R20 and R21 are connected in series and then in parallel with capacitor C23 between pins P2-10 and P2-12 of the connection base of each bus board. Resistors R20 and R21 are connected to signal ground through resistor R22 and capacitor C20. Resistors R23 and R24 are connected in series and then in parallel with capacitor C24 between pins P2-18 and P2-20 of the connection base of each bus board. Resistors R23 and R24 are connected to signal ground through resistor R25 and capacitor C22.

[0016] The P2-1 pins of the bus board connecting bases b1, b2, and b3 are interconnected, the P2-3 pins are interconnected, and the P2-5 pins are interconnected. The P2-1 to P2-2 pins, the P2-3 to P2-4 pins, and the P2-5 to P2-6 pins on each bus board connecting base are connected in parallel and then connected to the CAN bus connector J2.

[0017] The bus board includes a power supply circuit, a power module, a FlexRay bus transceiver, a CAN bus transceiver, a CPU circuit, a TBDML circuit, and a watchdog circuit.

[0018] The power supply circuit, TBDML circuit, watchdog circuit, FlexRay bus transceiver, and CAN bus transceiver are all connected to the CPU circuit; the power module is connected to the FlexRay bus transceiver and the CAN bus transceiver.

[0019] The bus board includes capacitors C10-C15, capacitors C30-C33, a microcontroller, a CAN bus transceiver, two FlexRay bus transceivers, a watchdog circuit, a TBDML circuit, and a power module JD5-12D11205.

[0020] The motherboard's power conversion circuit, through capacitors C30, C31, C32 and inductor L1, is simultaneously connected to pins 83 and 66 of the CPU microcontroller, pins 1 and 2 of the CAN bus transceiver, pins 1 and 13 of the FlexRay bus transceiver, pins 2 and 4 of the watchdog circuit, and pins 2 and 6 of the TBDML circuit. Pin 1 of the watchdog circuit is simultaneously connected to pin 4 of the TBDML circuit and pin 44 of the microcontroller. Pin 1 of the watchdog circuit is connected to the motherboard's power conversion circuit through diode D4 and resistor R8. Pin 3 of the TBDML circuit is connected to pin 29 of the microcontroller through resistor R7.

[0021] The motherboard's power filter circuit is connected to pins 1 and 2 of the power module JD5-12D11205. Pins 3, 4, 5, and 6 of the power module JD5-12D11205 are connected to pins 4, 5, 8, and 13 of the FlexRay bus transceiver, respectively. Capacitors C10 and C13 are connected in parallel at the input of the power module JD5-12D11205, capacitors C12 and C14 are connected in parallel at the 5V power output, and capacitors C11 and C15 are connected in parallel at the 12V power output.

[0022] Pins 24 and 25 of the microcontroller are connected to the RXE pins of the two FlexRay bus transceivers, pins 57 and 36 of the microcontroller are connected to the RXD pins of the two FlexRay bus transceivers, pins 58 and 37 of the microcontroller are connected to the TXD pins of the two FlexRay bus transceivers, pins 59 and 38 of the microcontroller are connected to the TXE pins of the two FlexRay bus transceivers, and the FBM and FBP pins of FlexRay bus transceivers U5 and U6 are connected to the external network.

[0023] Pins 101 and 102 of the microcontroller are connected to the TXD and RXD pins of the CAN bus transceiver, respectively. The CANH, CANL, and CANG pins of the CTM1051 CAN bus transceiver are connected to the external CAN bus network.

[0024] Among them, pins 8 and 9 of the microcontroller are connected to LEDs D2 and D3 respectively.

[0025] The CAN bus transceiver and FlexRay bus transceiver are respectively the CAN bus transceiver CTM1051 with built-in power supply isolation and signal isolation and the FlexRay bus transceiver MFLR01.

[0026] Preferably, the bus board and the motherboard are directly connected by a board-mounted rectangular connector.

[0027] The three-CPU architecture multi-bus self-organizing network device of the present invention has the following advantages: the three bus boards can realize FlexRay bus network startup and networking, and can communicate with the host computer through the CAN bus of the bus board; it integrates one CAN bus and two FlexRay bus network interfaces in a small space, with perfect interaction between the two buses, high communication speed, high protection level, and high resistance to electromagnetic interference; the FlexRay bus can connect multiple bus nodes and communicate with the host computer through the CAN bus, enabling real-time monitoring and fault location of FlexRay bus communication status, meeting the usage requirements of military armored vehicles for multiple bus communication and multiple bus information interaction, complex environment, and strong anti-interference. Attached Figure Description

[0028] Figure 1 This is a system composition diagram of the three-CPU architecture multi-bus self-organizing network device of the present invention;

[0029] Figure 2 This is a diagram of the motherboard circuit.

[0030] Figure 3 This is the circuit schematic of the motherboard;

[0031] Figure 4 This is a circuit diagram of the bus board;

[0032] Figure 5 This is the schematic diagram of the bus board circuit.

[0033] Figure 6 This is the flowchart of the bus board program. Detailed Implementation

[0034] To better understand the purpose, structure, and function of this invention, the following detailed description of a multi-bus self-organizing network device with a three-CPU architecture, in conjunction with the accompanying drawings, is provided.

[0035] like Figure 1As shown, the three-CPU architecture multi-bus self-organizing network device of this embodiment includes a motherboard, a first bus board, a second bus board, and a third bus board. The first, second, and third bus boards are three identical bus boards, each with an independent CPU, FlexRay bus communication module, and CAN bus communication module. Each bus board has a FlexRay bus master cold start node, enabling self-starting of the FlexRay bus network. After startup, it interacts with the FlexRay and CAN buses. The bus boards communicate with external FlexRay bus nodes via FlexRay bus connectors and with a host computer via CAN bus connectors. The three bus boards communicate with each other. The motherboard is connected to an external power supply via a power connector to power the first, second, and third bus boards.

[0036] like Figure 2 As shown, the motherboard includes a power interface circuit, a power filter circuit, a power conversion circuit, a FlexRay bus interface circuit, and a CAN bus interface circuit. The power interface circuit supplies power to the power filter circuit, which is connected to the DC24V-DC5V power conversion circuit. After voltage conversion, a 5V power supply is output to power the bus board. Simultaneously, the power filter circuit directly provides a 24V power supply to the bus board. The FlexRay bus interface circuit and the CAN bus interface circuit are respectively connected to the corresponding external buses for communication with the outside world.

[0037] The specific circuit structure of the motherboard is as follows: Figure 3As shown, the external power supply is supplied to the motherboard via power connector J1. The power supply is first connected to the positive terminal of the reverse protection diode D1. The negative terminal of the reverse protection diode D1 is connected to the positive terminal of the filter capacitors C1 to C6. The negative terminal of the power supply is directly connected to the negative terminal of the filter capacitors C1 to C6 via the power connector, forming a power filtering circuit. After filtering, the power supply is connected to pins 2 and 3 of the DC24V-DC5V power module IQDNM-140202. Pins 4 and 5 of the power module IQDNM-140202 output 5V voltage, which is connected to the positive and negative terminals of the filter capacitors C7 and C8 for filtering. Then, it is connected to pins P1-1 and P1-5 on the bus board connection bases b1, b2, and b3, forming a power conversion circuit. Pins P1-1 to P1-4 and pins P1-5 to P1-8 on each bus board connection base are connected in parallel to supply power to the bus board. Power connector J1 connects simultaneously to pins P1-9 and P1-15 of bus board connection bases b1, b2, and b3. Pins P1-9 to P1-14 are connected in parallel, and pins P1-15 to P1-20 are connected in parallel on each bus board connection base, providing a 24V power supply to each of the three bus boards. The FlexRay bus interface circuit includes two bus interface circuits: FlexRay bus channel A and channel B. Pins P2-10 on bus board connection bases b1, b2, and b3 are interconnected; pins P2-12 on bus board connection bases b1, b2, and b3 are interconnected; pins P2-14 on bus board connection bases b1, b2, and b3 are interconnected; and pins P2-9 to P2-10, P2-11 to P2-12, and P2-13 to P2-16 on each bus board connection base are connected in parallel, and then... Connect to FlexRay bus connector J3 to achieve physical layer connection of FlexRay bus channel A; connect the P2-16 pins, P2-18 pins, and P2-20 pins on the bus board connection bases b1, b2, and b3 to each other; connect the P2-13 to P2-16 pins, P2-17 to P2-18 pins, and P2-19 to P2-20 pins on each bus board connection base in parallel; and then connect to FlexRay bus connector J3 to achieve physical layer connection of FlexRay bus channel B.Both FlexRay bus channel A and channel B interface circuits include impedance matching circuits. Resistors R20 and R21, connected in series, are connected in parallel with capacitor C23 between pins P2-10 and P2-12 of each bus board connection base. Resistors R20 and R21 are connected to signal ground via resistor R22 and capacitor C20, forming the impedance matching circuit for FlexRay bus channel A. Similarly, resistors R23 and R24, connected in series, are connected in parallel with capacitor C24 between pins P2-18 and P2-20 of each bus board connection base. Resistors R23 and R24 are connected to signal ground via resistor R25 and capacitor C22, forming the impedance matching circuit for FlexRay bus channel B. These impedance matching circuits for FlexRay bus channels A and B play a crucial role in the stability and anti-interference capabilities of the FlexRay bus network. The bus board connecting bases b1, b2, and b3 are interconnected via pins P2-1, P2-3, and P2-5. On each bus board connecting base, pins P2-1 to P2-2 are connected in parallel, P2-3 to P2-4 in parallel, and P2-5 to P2-6 in parallel. These are then connected to the CAN bus connector J2 to achieve the physical layer connection of the CAN bus. The three bus boards are directly plugged into the motherboard using board-mount rectangular connectors, ensuring a convenient and reliable connection.

[0038] like Figure 4 As shown, the bus board includes a power supply circuit, a power module, a FlexRay bus transceiver, a CAN bus transceiver, a CPU circuit, a TBDML circuit, and a watchdog circuit. The power supply circuit, TBDML circuit, watchdog circuit, FlexRay bus transceiver, and CAN bus transceiver are all connected to the CPU circuit; the power module is connected to the FlexRay bus transceiver and the CAN bus transceiver.

[0039] like Figure 5As shown, the 5V power supply circuit provided by the motherboard first connects capacitors C30, C31, and C32 in parallel, and then connects them in series with inductor L1 for filtering. It is then simultaneously connected to pins 83 and 66 of the CPU circuit's main chip microcontroller MC9S12XF512MLM, pins 1 and 2 of the CAN bus transceiver CTM1051, pins 1 and 13 of the FlexRay bus transceiver MLFR01, pins 2 and 4 of the watchdog circuit MC33064D, and pins 2 and 6 of the TBDML circuit, supplying power to all circuits on the entire bus board. The CPU circuit uses the MC9S12X... The F512MLM microcontroller serves as the main processor. The clock circuit uses a 4MHz crystal oscillator, with its two pins connected to pins 48 and 49 of the MC9S12XF512MLM. Pin 1 of the watchdog circuit MC33064D is connected to pin 4 of the TBDML circuit, and then to pin 44 of the MC9S12XF512MLM microcontroller. It is connected to a 5V power supply via diode D4 and resistor R8. Pin 3 of the TBDML circuit is connected to resistor R7 and then to pin 29 of the MC9S12XF512MLM microcontroller for program downloading and operation. During program debugging, the microcontroller is reset to prevent electromagnetic interference in complex electromagnetic environments from causing program crashes and infinite loops. A watchdog circuit can be used to monitor the microcontroller's operating status in real time, restarting the microcontroller when it enters an infinite loop. Pins 8 and 9 of the MC9S12XF512MLM microcontroller are connected to LEDs D2 and D3 respectively. The different flashing frequencies of the two LEDs indicate the microcontroller's operating status and whether the FlexRay bus network is successfully established. The motherboard provides one 24V power supply. The power supply module JD5-12D11205's pins 1 and 2 are connected to the source. Pins 3, 4, 5, and 6 of the JD5-12D11205 are connected to pins 4, 5, 8, and 13 of the FlexRay bus transceiver U5, respectively. Simultaneously, pins 3, 4, 5, and 6 of the JD5-12D11205 are connected to pins 4, 5, 8, and 13 of the FlexRay bus transceiver U6, respectively. This converts the DC24V voltage to DC12V and DC5V voltages, supplying power to the isolation circuits of the FlexRay bus transceivers U5 and U6. Capacitors C10 and C13 are connected in parallel at the input of the JD5-12D11205 power supply module, capacitors C12 and C14 are connected in parallel at the 5V power output, and capacitors C11 and C15 are connected in parallel at the 12V power output to further eliminate power harmonic interference, thereby further eliminating the problem of unstable bus network communication caused by external voltage fluctuations. Both FlexRay bus transceivers U5 and U6 are FlexRay bus transceivers MFLR01.

[0040] Pins 24 and 25 of the MC9S12XF512MLM microcontroller are connected to the RXE pins of FlexRay bus transceivers U5 and U6, respectively. Pins 57 and 36 of the MC9S12XF512MLM microcontroller are connected to the RXD pins of FlexRay bus transceivers U5 and U6, respectively. Pins 58 and 37 of the MC9S12XF512MLM microcontroller are connected to the TXD pins of FlexRay bus transceivers U5 and U6, respectively. Pins 59 and 38 of the MC9S12XF512MLM microcontroller are connected to the TXE pins of FlexRay bus transceivers U5 and U6, respectively. This enables the transmission and reception control of two FlexRay bus channels and connects to an external network through the FBM and FBP pins of FlexRay bus transceivers U5 and U6. LEDs D2 and D3 are connected to pins 8 and 9 of the microcontroller, respectively. When the FlexRay bus network is started, LEDs D2 and D3 flash mutually, indicating that the FlexRay bus network has been started.

[0041] Pins 101 and 102 of the microcontroller MC9S12XF512MLM are connected to the TXD and RXD pins of the CAN bus transceiver CTM1051, respectively. The CANH, CANL, and CANG pins of the CAN bus transceiver CTM1051 are connected to the external CAN bus network to realize communication with the external CAN bus node. At the same time, a 120-ohm resistor is connected in parallel at both ends of the CANH and CANL pins to achieve impedance matching of the entire CAN network.

[0042] like Figure 6 As shown, the workflow of this embodiment is as follows: After the entire device is powered on, power is supplied to its three core bus boards. Then, the three bus boards start running the microcontroller software program. First, the CPU chip MC9S12XF512MLM is initialized, as are FlexRay, CAN communication, watchdog functions, and software variables. Then, CAN bus interrupt and FlexRay bus interrupt are enabled. After the bus board receives data, it starts the FlexRay bus network. After starting the FlexRay bus network, it receives FlexRay bus information in the interrupt and realizes the mutual conversion between CAN bus and FlexRay bus. It connects to the host computer through the CAN bus, and the host computer software monitors the FlexRay bus communication status in real time. This bus board is responsible for communicating with external FlexRay bus nodes and internally converting the data to CAN bus before sending it to the host computer software for real-time monitoring of the FlexRay bus communication status.

[0043] This invention discloses a multi-bus self-organizing network device with a three-CPU architecture. Considering the particularly complex electromagnetic environment of armored vehicles and the potential for hardware damage from static electricity, surges, and short circuits directly affecting communication lines, isolation is essential before the self-organizing network device connects to the bus. This embodiment uses a CAN bus transceiver CTM1051 with built-in power and signal isolation, and a FlexRay bus transceiver MFLR01, eliminating electrical connections between inputs and outputs and preventing the power supply from affecting the transceivers. Dual isolation of power and communication ensures isolation and protection between the FlexRay bus transceiver, the CAN bus transceiver, and the MCU, thereby protecting the device's communication signal ports. This solution offers high reliability, small PCB space footprint, and a high EMC protection level.

[0044] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art will be able to make various modifications and improvements without departing from the principles of the present invention, and these modifications and improvements should also be considered to fall within the scope of protection of the present invention.

Claims

1. A multi-bus self-organizing network device with a three-CPU architecture, characterized in that, It includes a motherboard, a first bus board, a second bus board, and a third bus board; the motherboard is connected to an external power supply via a power connector, and the first bus board, the second bus board, and the third bus board are all connected to the motherboard; The first bus board, the second bus board, and the third bus board are three bus boards with the same structure. Each bus board has an independent CPU, FlexRay bus communication module, CAN bus communication module, and FlexRay bus master cold start node. All bus boards are connected and communicate with external FlexRay bus nodes via FlexRay bus connectors and with the host computer via CAN bus connectors; the bus boards are interconnected and communicate with each other. The bus board includes a power supply circuit, a power supply module, a FlexRay bus transceiver, a CAN bus transceiver, a CPU circuit, a TBDML circuit, and a watchdog circuit. The power supply circuit, TBDML circuit, watchdog circuit, FlexRay bus transceiver, and CAN bus transceiver are all connected to the CPU circuit; the power module is connected to the FlexRay bus transceiver and the CAN bus transceiver. The bus board includes capacitors C10-C15, capacitors C30-C33, a microcontroller, a CAN bus transceiver, two FlexRay bus transceivers, a watchdog circuit, a TBDML circuit, and a power module JD5-12D11205. The motherboard's power conversion circuit, through capacitors C30, C31, C32 and inductor L1, is simultaneously connected to pins 83 and 66 of the CPU microcontroller, pins 1 and 2 of the CAN bus transceiver, pins 1 and 13 of the FlexRay bus transceiver, pins 2 and 4 of the watchdog circuit, and pins 2 and 6 of the TBDML circuit. Pin 1 of the watchdog circuit is simultaneously connected to pin 4 of the TBDML circuit and pin 44 of the microcontroller. Pin 1 of the watchdog circuit is connected to the motherboard's power conversion circuit through diode D4 and resistor R8. Pin 3 of the TBDML circuit is connected to pin 29 of the microcontroller through resistor R7. The motherboard's power filter circuit is connected to pins 1 and 2 of the power module JD5-12D11205. Pins 3, 4, 5, and 6 of the power module JD5-12D11205 are connected to pins 4, 5, 8, and 13 of the FlexRay bus transceiver, respectively. Capacitors C10 and C13 are connected in parallel at the input of the power module JD5-12D11205, capacitors C12 and C14 are connected in parallel at the 5V power output, and capacitors C11 and C15 are connected in parallel at the 12V power output. Pins 24 and 25 of the microcontroller are connected to the RXE pins of the two FlexRay bus transceivers, pins 57 and 36 of the microcontroller are connected to the RXD pins of the two FlexRay bus transceivers, pins 58 and 37 of the microcontroller are connected to the TXD pins of the two FlexRay bus transceivers, pins 59 and 38 of the microcontroller are connected to the TXE pins of the two FlexRay bus transceivers, and the FBM and FBP pins of FlexRay bus transceivers U5 and U6 are connected to the external network. Pins 101 and 102 of the microcontroller are connected to the TXD and RXD pins of the CAN bus transceiver, respectively. The CANH, CANL, and CANG pins of the CTM1051 CAN bus transceiver are connected to the external CAN bus network.

2. The multi-bus self-organizing network device with a three-CPU architecture according to claim 1, characterized in that, The motherboard includes a power interface circuit, a power filtering circuit, a power conversion circuit, a FlexRay bus interface circuit, and a CAN bus interface circuit. The input terminal of the power interface circuit is connected to an external power source, and the output terminal is connected to the input terminal of the power filter circuit; the output terminal of the power filter circuit is connected to the input terminal of the power conversion circuit and each bus board respectively; the output terminal of the power conversion circuit is connected to each bus board. The FlexRay bus interface circuit and the CAN bus interface circuit are respectively connected to the corresponding external buses for communication.

3. The multi-bus self-organizing network device with a three-CPU architecture according to claim 2, characterized in that, The motherboard's power filter circuit outputs 24V power, and the power conversion circuit outputs 5V power.

4. The multi-bus self-organizing network device with a three-CPU architecture according to claim 2, characterized in that, The motherboard includes a reverse protection diode D1, filter capacitors C1 to C8, resistors R20 to R25, power connector J1, power module IQDNM-140202, bus board connection base b1, bus board connection base b2, bus board connection base b3, FlexRay bus connector J3, CAN bus connector J2, capacitors C20, C22, C23, and C24. The positive terminal of the external power supply is connected to the positive terminal of the reverse protection diode D1. The negative terminal of the reverse protection diode D1 is connected to the positive terminal of the filter capacitors C1 to C6. The negative terminal of the external power supply is connected to the negative terminal of the filter capacitors C1 to C6 via the power connector. The positive and negative terminals of the filtered power supply are connected to pins 2 and 3 of the power module IQDNM-140202, respectively. Pins 4 and 5 of the power module IQDNM-140202 are connected to pins P1-1 and P1-5 on the bus board connection bases b1, b2, and b3 via filter capacitors C7 and C8. Pins P1-1 to P1-4 and pins P1-5 to P1-8 on each bus board connection base are connected in parallel. Power connector J1 connects to pins P1-9 and P1-15 of bus board connection bases b1, b2, and b3. Pins P1-9 to P1-14 on each bus board connection base are connected in parallel, and pins P1-15 to P1-20 are connected in parallel. Pins P2-10 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-12 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-14 on bus board connection bases b1, b2, and b3 are interconnected. Pins P2-9 to P1-15 on each bus board connection base are interconnected. Pin 0 is connected in parallel, pins P2-11 to P2-12 are connected in parallel, pins P2-13 to P2-16 are connected in parallel, and then connected to FlexRay bus connector J3; pins P2-16 on bus board connection bases b1, b2, and b3 are interconnected, pins P2-18 are interconnected, and pins P2-20 are interconnected; pins P2-13 to P2-16, P2-17 to P2-18, and P2-19 to P2-20 on each bus board connection base are connected in parallel, and then connected to FlexRay bus connector J3; Resistors R20 and R21 are connected in series and then in parallel with capacitor C23 between pins P2-10 and P2-12 of the connection base of each bus board. Resistors R20 and R21 are connected to signal ground through resistor R22 and capacitor C20. Resistors R23 and R24 are connected in series and then in parallel with capacitor C24 between pins P2-18 and P2-20 of the connection base of each bus board. Resistors R23 and R24 are connected to signal ground through resistor R25 and capacitor C22. The P2-1 pins of the bus board connecting bases b1, b2, and b3 are interconnected, the P2-3 pins are interconnected, and the P2-5 pins are interconnected. The P2-1 to P2-2 pins, the P2-3 to P2-4 pins, and the P2-5 to P2-6 pins on each bus board connecting base are connected in parallel and then connected to the CAN bus connector J2.

5. The multi-bus self-organizing network device with a three-CPU architecture according to claim 3, characterized in that, LEDs D2 and D3 are connected to pins 8 and 9 of the microcontroller, respectively.

6. The multi-bus self-organizing network device with a three-CPU architecture according to claim 5, characterized in that, The CAN bus transceiver and FlexRay bus transceiver are respectively the CAN bus transceiver CTM1051 with built-in power supply isolation and signal isolation and the FlexRay bus transceiver MFLR01.

7. The multi-bus self-organizing network device with a three-CPU architecture according to claim 1, characterized in that, The bus board and the motherboard are directly connected by a board-mounted rectangular connector.

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