Command control circuit and method, command decode circuit, device

Abstract

The present disclosure relates to a command control circuit, a command control method, a command decoding circuit and an electronic device, and relates to the technical field of integrated circuits. The command control circuit comprises: a first latch configured to latch a first cycle signal at a first clock; and a command control module configured to control an enable or disable of a latching function of a second cycle signal according to a chip select signal at a second clock and the latched first cycle signal. The present disclosure provides a method for reducing resource waste in a command decoding process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a command control circuit, a command control method, a command decoding circuit and an electronic device. BACKGROUND

[0002] Double Data Rate fifth-generation Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a kind of high-bandwidth computer memory.

[0003] Two types of commands are usually included in DDR5: single-cycle commands and double-cycle commands. The decoding structure suitable for double-cycle commands will still be decoded in the second cycle without a command for single-cycle commands, resulting in resource waste.

[0004] It should be noted that the signals disclosed in the above background section are only used to strengthen the understanding of the background of the present disclosure, and therefore can include signals that do not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a command control circuit, a command control method, a command decoding circuit and an electronic device to provide a method for reducing resource waste in the execution of command decoding process.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a command control circuit is provided, comprising:

[0008] a first latch for latching a first cycle signal at a first clock;

[0009] a command control module for controlling the latching function of a second cycle signal to be turned on or off according to the chip select signal and the latched first cycle signal at a second clock.

[0010] In some embodiments of the present disclosure, the command control module is configured to turn off the latching function of the second cycle signal at the second clock in the case of a single-cycle command, and turn on the latching function of the second cycle signal at the second clock in the case of a double-cycle command.

[0011] In some embodiments of the present disclosure, the latched first cycle signal includes a chip select latch signal, a first bus latch signal and a second bus latch signal.

[0012] In some embodiments of the present disclosure, the command control module is configured to turn off the latching function of the second cycle signal when the chip select latching signal is low, and the first bus latching signal and the second bus latching signal are high.

[0013] In some embodiments of the present disclosure, the command control module is configured to turn on the latching function of the second cycle signal when the chip select latching signal, the first bus latching signal and the second bus latching signal are all low.

[0014] In some embodiments of the present disclosure, the command control module is configured to turn on the latching function of the second cycle signal when the chip select latching signal and the first bus latching signal are low, and the second bus latching signal is high.

[0015] In some embodiments of the present disclosure, the command control module is configured to turn on the latching function of the second cycle signal when the chip select latching signal is low, the first bus latching signal is high, and the second bus latching signal is low.

[0016] In some embodiments of the present disclosure, the command control module comprises an AND gate, an NAND gate and a NOT gate; wherein,

[0017] The input end of the AND gate is connected to the chip select latching signal, the first bus latching signal and the second bus latching signal, and the NOT gate is arranged on the line connected to the chip select latching signal.

[0018] The input end of the NAND gate is connected to the output end of the AND gate and the chip select signal under the current clock, and the output end of the NAND gate is connected to the second latch.

[0019] In some embodiments of the present disclosure, the second latch is the first latch.

[0020] In some embodiments of the present disclosure, the second latch is one or more of an address latch, a command latch and an array latch.

[0021] According to a second aspect of the present disclosure, a command control method is provided, comprising:

[0022] latching a first cycle signal at a first clock;

[0023] controlling the latching function of a second cycle signal to be turned on or off according to the chip select signal under a second clock and the latched first cycle signal.

[0024] In some embodiments of the present disclosure, the control of the enablement or disablement of the latching function of the second cycle signal according to the chip select signal under the second clock and the latched first cycle signal comprises:

[0025] In the case of a single cycle command, the latching function of the second cycle signal is disabled at the second clock;

[0026] In the case of a double cycle command, the latching function of the second cycle signal is enabled at the second clock.

[0027] In some embodiments of the present disclosure, the latched first cycle signal comprises a chip select latched signal, a first bus latched signal and a second bus latched signal.

[0028] According to a third aspect of the present disclosure, a command decoding circuit is provided, comprising the above-mentioned command control circuit and a command decoder; wherein,

[0029] The output terminal of the first latch of the command control circuit is connected to the input terminal of the command decoder.

[0030] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned command control circuit.

[0031] The technical solutions provided by the present disclosure can have the following beneficial effects:

[0032] The command control circuit provided by the exemplary embodiments of the present disclosure is used to control the enablement or disablement of the latching function of the second cycle signal according to the chip select signal under the second clock and the latched first cycle signal, so as to disable the latching function of the second cycle signal at the second clock in the case of a single cycle command, and enable the latching function of the second cycle signal at the second clock in the case of a double cycle command. Thus, for a double cycle command, the latching and decoding functions after the latching can be continued at the second clock. In addition, for a single cycle command, the latching function can be disabled at the second clock, so that unnecessary waste can be avoided when the single cycle command is executed, and the purposes of cost saving and energy consumption reduction can be achieved.

[0033] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings:

[0035] Figure 1 A command truth table of a DDR5 is schematically illustrated according to an example embodiment of the present disclosure;

[0036] Figure 2 A block diagram of a command control circuit is schematically illustrated according to an example embodiment of the present disclosure;

[0037] Figure 3 A structural diagram of a command control module in a command control circuit is schematically illustrated according to an example embodiment of the present disclosure;

[0038] Figure 4 A structural diagram of a command control circuit is schematically illustrated according to an example embodiment of the present disclosure;

[0039] Figure 5 A flowchart of a command control method is schematically illustrated according to an example embodiment of the present disclosure;

[0040] Figure 6 A structural diagram of a command decoding circuit is schematically illustrated according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0042] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0043] The block diagrams in the drawings show functions and functionality as they can be implemented in software or computer programs. Implementations in software can be through the use of application specific circuits, processors, microcontrollers, or general purpose processors. The block diagrams do not show the specific circuitry or details of the hardware (e.g., host devices, network devices, processors, memory, etc.) that can be used to implement the depicted functionality, and thus the block diagrams should not be interpreted in these terms. Rather, the block diagrams represent a functional description of the software or computer programs that implement the depicted functionality.

[0044] DDR5 is the abbreviation of the fifth generation of DDR SDRAM, DDR SDRAM is the abbreviation of Double Data Rate SDRAM in English, which is translated as double data rate SDRAM in Chinese, and SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, which is translated as synchronous dynamic random access memory, and the synchronization object is the system clock frequency. Therefore, combined together, DDR5 means the fifth generation of double data rate synchronous dynamic random access memory.

[0045] DDR5 is the first time in the history of memory technology to combine command and address signals into a CA bus. Compared with the independent characteristics of command and address signal pins in DDR4 and previous memory products, the parsing method of DDR5 is very different. Specifically, DDR4 and previous memory products, under the premise that the chip select signal is valid, when the rising edge comes, the DRAM command receiver will sample all command signals to parse the current command, and sample the address signal as needed to obtain the address signal, which means that all operations can be completed in one clock cycle. Because of the use of CA bus, many commands in DDR5 need two clock cycles to complete, that is, when the first rising edge comes, the CA signal is sampled to parse the command, and when the second rising edge comes, the other CA signal is sampled to parse the address.

[0046] Referring to Figure 1 , the command truth table of DDR5 is shown (the table is extracted from DDR5 Full Spec Draft Rev0.1), in which region one 101 shows double cycle commands, and region two 102 shows single cycle commands. For DDR5, there are 14 CA pins in total: CA0-CA13, among which CA0 and CA1 are used to distinguish first cycle commands and second cycle commands. As can be seen from the figure, commands with CA0 and CA1 as high level H are single cycle commands, and other cases are double cycle commands.

[0047] Figure 1 In it, CS_n represents the chip select signal. For double cycle commands, when CS_n is low L, the command is parsed, that is, the first cycle command is completed; when CS_n is high H, the address is parsed, that is, the second cycle command is completed. For single cycle commands, only when CS_n is low L, all commands are parsed, and when CS_n is high H, the Deselect command is executed, that is, no parsing work is done. Therefore, for single cycle commands, when CS_n is high H, that is, in the second cycle, it is in the non-working state, and if the parsing work is still performed, it will cause waste of resources and increase of power consumption.

[0048] Based on this, the command control circuit provided in the example embodiments of the present disclosure can be used for both single-cycle commands and double-cycle commands, and can also achieve the purpose of reducing power consumption. It should be noted that the command control circuit provided in the example embodiments of the present disclosure is not only applicable to DDR5 memories, but also applicable to other memories with single-cycle commands and / or double-cycle commands. The example embodiments of the present disclosure are not specially limited for specific use ranges.

[0049] With reference to Figure 2 The command control circuit 200 comprises a first latch 220 and a command control module 240, wherein

[0050] The first latch 220 is configured to latch a first cycle signal at a first clock.

[0051] The command control module 240 is configured to control the latching function of a second cycle signal to be turned on or off according to a chip select signal at a second clock and the latched first cycle signal.

[0052] In actual applications, the decoding of a command usually starts from the latching of a signal in the command. The signal in the command is latched at the first clock, and the latched signal is decoded at the second clock. Therefore, in the example embodiments of the present disclosure, the first clock is the time when the signal in the command is latched to obtain the first cycle signal.

[0053] For a double-cycle command, the first cycle signal is Figure 1 For a single-cycle command, the first cycle signal is Figure 1 For a single-cycle command, the first cycle signal is

[0054] In actual applications, the first latch is a command latch, which is mainly used to latch the signal in the command. The latched signal includes a chip select latched signal CS_n_d and a plurality of bus latched signals.

[0055] In the example embodiments of the present disclosure, the latched first cycle signal mainly includes a chip select latched signal CS_n_d, a first bus latched signal CA0_d and a second bus latched signal CA1_d.

[0056] In the second clock, the chip select signal CS_n is a high level H signal, at this time the second period signal of the double period command is collected, and the single period command executes the Deselect command. The command control module 240 in the command control circuit provided by the exemplary embodiments of the present disclosure is mainly used to, according to the chip select signal in the second clock and the latched first period signal, in the case of a single period command, turn off the latching function of the second period signal at the second clock; in the case of a double period command, turn on the latching function of the second period signal at the second clock. Thus, for a double period command, the latching and decoding functions and the like after the latching can continue to be executed at the second clock; in addition, for a single period command, the latching function can be turned off at the second clock, so that unnecessary waste can be avoided when the single period command is executed, and the purpose of saving cost and reducing energy consumption is achieved.

[0057] The exemplary embodiments of the present disclosure take the command truth table of DDR5 shown in Figure 1 The specific signal levels are described as follows:

[0058] The command control module 240 is configured to, when the chip select latching signal CS_n_d is a low level 0, the first bus latching signal CA0_d and the second bus latching signal CA1_d are high levels 1, at this time it is indicated that the command is a single period command, and the latching function of the second period signal is turned off.

[0059] The command control module 240 is configured to, when the chip select latching signal CS_n_d, the first bus latching signal CA0_d and the second bus latching signal CA1_d are all low levels 0, at this time it is indicated that the command is a double period command, and the latching function of the second period signal is turned on.

[0060] The command control module 240 is configured to, when the chip select latching signal CS_n_d and the first bus latching signal CA0_d are low levels 0, and the second bus latching signal CA1_d is a high level 1, at this time it is indicated that the command is a double period command, and the latching function of the second period signal is turned on.

[0061] The command control module 240 is further configured to, when the chip select latching signal CS_n_d is a low level 0, the first bus latching signal CA0_d is a high level 1, and the second bus latching signal CA1_d is a low level 0, at this time it is indicated that the command is a double period command, and the latching function of the second period signal is turned on. The latching function of the second period signal refers to the latching function in the second clock. The latching function in the second clock includes one or more of the command latching function, the address latching function and the array latching function.

[0062] It should be noted that with the development of products, the command truth table can be changed, and therefore, whether the chip select latch signal CS_n_d, the first bus latch signal CA0_d and the second bus latch signal CA1_d are low level 0 or high level 1 needs to be adjusted according to the actual command truth table, and the exemplary embodiments of the present disclosure do not make special limitations thereon.

[0063] The exemplary embodiments of the present disclosure determine the command control module in the circuit structure shown in Figure 3 In actual applications, the implementation mode of the command control module is not limited to the structure shown in Figure 3 Any implementation mode that can implement the above functions falls within the protection scope of the present disclosure.

[0064] Referring to Figure 3 , the command control module 240 provided by the exemplary embodiments of the present disclosure includes an AND gate 301, an NAND gate 303 and a NOT gate 305; wherein the command control module 240 is the structure of the latch and the decoder in the high enablement scenario, and the structure in the low enablement scenario can be referred to the setting, which will not be described one by one here.

[0065] The input end of the AND gate 301 is connected to the chip select latch signal CS_n_d, the first bus latch signal CA0_d and the second bus latch signal CA1_d; the NOT gate 305 is arranged on the line connected to the chip select latch signal CS_n_d, and is used to take the NOT of the chip select latch signal CS_n_d.

[0066] The input end of the NAND gate 303 is connected to the output end of the AND gate 301 and the chip select signal CS_n under the current clock, and the output end of the NAND gate 303 is connected to the second latch.

[0067] In actual applications, if the chip select latch signal CS_n_d is low level 0, the NOT is high level 1, the first bus latch signal CA0_d and the second bus latch signal CA1_d are high level 1, at this time, the three signals are output as high level 1 through the AND gate 301, if the current clock is the first clock, the chip select signal CS_n under the first clock is low level 0, the high level 1 output by the AND gate 301 and the low level 0 of the chip select signal CS_n under the first clock are input into the NAND gate 303, and high level 1 is obtained, in the case of high level enablement, at this time, the first period signal can be normally obtained.

[0068] If the current clock is the second clock, the chip select signal CS_n under the second clock is high level 1, the high level 1 outputted by the AND gate 301 and the high level 1 of the chip select signal CS_n under the second clock pass through the NAND gate 303, and a low level 0 is obtained. In the case of high level enable, the latch function of the second period signal can be turned on at this time, which is suitable for a double period command.

[0069] In practical application, if the chip select latch signal CS_n_d is low level 0, the NAND gate 302 outputs high level 1, the first bus latch signal CA0_d is low level 0, and the second bus latch signal CA1_d is high level 1, the three signals pass through the AND gate 301 and output low level 0. If the current clock is the first clock, the chip select signal CS_n under the first clock is low level 0, the low level 0 outputted by the AND gate 301 and the low level 0 of the chip select signal CS_n under the first clock pass through the NAND gate 303, and a high level 1 is obtained. In the case of high level enable, the first period signal can be normally acquired at this time.

[0070] If the current clock is the second clock, the chip select signal CS_n under the second clock is high level 1, the low level 0 outputted by the AND gate 301 and the high level 1 of the chip select signal CS_n under the second clock pass through the NAND gate 303, and a high level 1 is obtained. In the case of high level enable, the latch function of the second period signal can be turned on at this time, which is suitable for a double period command.

[0071] In practical application, if the chip select latch signal CS_n_d is low level 0, the NAND gate 302 outputs high level 1, the first bus latch signal CA0_d is low level 0, and the second bus latch signal CA1_d is high level 1, the three signals pass through the AND gate 301 and output low level 0. If the current clock is the first clock, the chip select signal CS_n under the first clock is low level 0, the low level 0 outputted by the AND gate 301 and the low level 0 of the chip select signal CS_n under the first clock pass through the NAND gate 303, and a high level 1 is obtained. In the case of high level enable, the first period signal can be normally acquired at this time.

[0072] If the current clock is the second clock, the chip select signal CS_n under the second clock is high level 1, the low level 0 outputted by the AND gate 301 and the high level 1 of the chip select signal CS_n under the second clock pass through the NAND gate 303, and a high level 1 is obtained. In the case of high level enable, the latch function of the second period signal can be turned on at this time, which is suitable for a double period command.

[0073] In actual application, if the chip select latch signal CS_n_d is low 0, the non-take is high 1, the first bus latch signal CA0_d is high 1, and the second bus latch signal CA1_d is low 0, at this time, the three signals output low 0 through the AND gate 301, if the current clock is the first clock, the chip select signal CS_n under the first clock is low 0, and the low 0 output by the AND gate 301 and the chip select signal CS_n under the first clock are low 0, which are input into the NAND gate 303, and high 1 is obtained, and in the case of high level enable, at this time, the first period signal can be normally acquired.

[0074] If the current clock is the second clock, the chip select signal CS_n under the second clock is high 1, and the low 0 output by the AND gate 301 and the chip select signal CS_n under the second clock are high 1, which are input into the NAND gate 303, and high 1 is obtained, and in the case of high level enable, at this time, the latch function of the second period signal can be started, which is suitable for the double period command.

[0075] It can be seen that the command control module 240 provided by the example embodiment of the present disclosure meets the requirement of closing or starting the latch function of the second period signal according to the single period command and the double period command in the high enable scene, and can achieve the purpose of closing the latch function of the second period signal in the single period command in the present disclosure, which has the effects of saving power consumption and saving resources.

[0076] Referring to Figure 4 , a structure schematic diagram of a command control circuit provided by an example embodiment of the present disclosure is shown, wherein the output end of the command control module 240 is connected with the enable end of the second latch, for controlling the starting or closing of the second latch.

[0077] In actual application, the second latch can be one or more of the command latch 411, the array latch 412 and the address latch 413. In addition, the second latch can also be the first latch 220, that is, in the first clock, the command control module 240 is used to acquire the first period signal from the first latch 220, and in the second clock, the command control module 240 controls the first latch 220 to start or close. The first latch 220 here is a command latch.

[0078] The example embodiment of the present disclosure also provides a command control method. Referring to Figure 5 , the command control method can specifically include the following steps:

[0079] Step S52, latch the first period signal in the first clock;

[0080] Step S54, according to the chip select signal under the second clock and the latched first cycle signal, the control second cycle signal latching function is opened or closed.

[0081] In some embodiments of the present disclosure, according to the chip select signal under the second clock and the latched first cycle signal, the control second cycle signal latching function is opened or closed, including: in the case of single cycle command, at the second clock, the latching function of the second cycle signal is closed; in the case of double cycle command, at the second clock, the latching function of the second cycle signal is opened.

[0082] In some embodiments of the present disclosure, the latched first cycle signal includes: chip select latching signal, first bus latching signal and second bus latching signal.

[0083] The command control method provided by the exemplary embodiments of the present disclosure can judge single cycle command and double cycle command through the latched first cycle signal, and then control the latching function of the second cycle signal to be opened or closed in combination with the chip select signal under the second clock, so as to achieve the purpose of opening the latching function of the second cycle signal when executing double cycle command, and closing the latching function of the second cycle signal when executing single cycle command. Thus, power consumption can be saved when executing single cycle command, unnecessary resource waste can be reduced, and resource utilization can be improved.

[0084] The specific details of each step in the above command control method have been described in detail in the corresponding command control circuit, so they will not be repeated here.

[0085] Referring to Figure 6 The exemplary embodiments of the present disclosure also provide a command decoding circuit, which comprises the command decoder 610 and the above-mentioned command control circuit, the output end of the first latch in the command control circuit is connected with the input end of the command decoder, and the command decoder is used for decoding the address signal output by the first latch.

[0086] In the exemplary embodiments of the present disclosure, the specific structure of the command control circuit in the command decoding circuit has been described in detail in the above-mentioned embodiments, so it will not be repeated here.

[0087] The exemplary embodiments of the present disclosure also provide an electronic device, which comprises the above-mentioned command control circuit, wherein the specific structure of the command control circuit has been described in detail in the above-mentioned embodiments, so it will not be repeated here.

[0088] In the embodiments described above, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded on a computer, all or part of the processes or functions described in the embodiments of the present disclosure are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium. The computer readable storage medium can be any available medium accessible by a computer or data storage device such as a server, data center, etc. containing one or more media integrated with the medium. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer can include the devices described above.

[0089] Although the present disclosure is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from an inspection of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0090] Although the present disclosure is described herein in conjunction with specific features and embodiments thereof, it is understood that various modifications and combinations can be made thereto without departing from the spirit and scope of the disclosure. Accordingly, the description and drawings are to be regarded as illustrative in nature and are not to be taken as limiting the scope of the disclosure. Obviously, many modifications and variations of this disclosure are possible in light of its teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, this disclosure can be practiced otherwise than as specifically described.

Claims

1. A command control circuit, characterized by comprising: The first latch is used for latching the first period signal at the first clock. The latched first period signal comprises a chip select latch signal, a first bus latch signal and a second bus latch signal. The command control module is used for controlling the latching function of the second period signal to be opened or closed according to the chip select signal at the second clock and the latched first period signal. The command control module is used for closing the latching function of the second period signal when the chip select latch signal is at a low level and the first bus latch signal and the second bus latch signal are at high levels.

2. The command control circuit of claim 1, wherein, The command control module is used for opening the latching function of the second period signal when the chip select latch signal, the first bus latch signal and the second bus latch signal are all at low levels.

3. The command control circuit of claim 1, wherein, The command control module is used for opening the latching function of the second period signal when the chip select latch signal and the first bus latch signal are at low levels and the second bus latch signal is at a high level.

4. The command control circuit of claim 1, wherein, The command control module is used for opening the latching function of the second period signal when the chip select latch signal is at a low level, the first bus latch signal is at a high level and the second bus latch signal is at a low level.

5. The command control circuit of claim 1, wherein, The command control module comprises an AND gate, an NAND gate and a NOT gate.

6. The command control circuit according to any one of claims 1 to 5, characterized by, The input end of the AND gate is connected to the chip select latch signal, the first bus latch signal and the second bus latch signal, and the NOT gate is arranged on the line connected to the chip select latch signal. The input end of the NAND gate is connected to the output end of the AND gate and the chip select signal at the current clock, and the output end of the NAND gate is connected to the second latch. The second latch is the first latch.

7. The command control circuit of claim 6, wherein, The second latch is one or more of an address latch, a command latch and an array latch.

8. The command control circuit of claim 7, wherein, The first period signal is latched at the first clock, and the latched first period signal comprises a chip select latch signal, a first bus latch signal and a second bus latch signal.

9. A command control method characterized by, The latching function of the second period signal is controlled to be opened or closed according to the chip select signal at the second clock and the latched first period signal, which comprises closing the latching function of the second period signal at the second clock in the case of a single period command and opening the latching function of the second period signal at the second clock in the case of a double period command. The command control circuit and the command decoder according to any one of claims 1-8 are comprised. The output end of the first latch of the command control circuit is connected to the input end of the command decoder.

10. A command decode circuit, comprising: The command control circuit according to any one of claims 1-8 is comprised. ​ 11. An electronic device, comprising: ​

Images