Method and system for testing a memory

Abstract

The application discloses a memory test method and a test system. The memory test method is used for controlling the test state and test flow of each to-be-tested memory through at least two layers of loop control and read-write sequence operation. The at least two layers of loop control include: algorithm loop, each algorithm loop controls the execution of all algorithm steps of one to-be-tested memory, and the test flow of the corresponding to-be-tested memory is ended after the execution of all algorithm steps; address loop, the test address is traversed in the execution process of each algorithm step, each traversed address is executed the read-write sequence operation, and the address loop is ended after the traversal of the test address is completed. The application realizes algorithm atomization, so that the MBIST memory built-in self-test architecture can realize a more flexible test process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of built-in self test of memory, in particular to a test method of memory with atomic MBIST algorithm and a corresponding test system. BACKGROUND

[0002] The commonly used MBIST memory built-in self test (MBIST, Memory Built-in Self Test) architecture is generally based on two ways.

[0003] One is the traditional way of using a total algorithm state machine to directly control the outer modules of the memory, that is, an algorithm state machine controls multiple outer modules of the memory, and then controls the test of the corresponding memory based on these outer modules. The algorithm state of this way is tightly coupled with the address / data generator in the outer module, and the flexibility is poor. Since only one total algorithm state machine is used, all the outer control modules mounted by the controller (test controller) must be completely synchronized at least in algorithm, and all the outer modules under the control of the same controller must use the same test algorithm. If different test algorithms need to be implemented between different memories, this way is not feasible, that is, the algorithm steps cannot realize atomic operation in this mode, and the flexibility is poor.

[0004] The second way adopts a structure based on a configurable instruction and algorithm register group. This way improves higher test flexibility compared with the traditional algorithm state machine, but the process of configuring the register group needs to spend a certain amount of time. Moreover, limited by the size of the register space, the configuration combination provided by the register group is relatively limited. If higher test flexibility is sought based on this way, it means higher chip area overhead. Since the register group still exists in the controller, the coupling between the controller and the outer module is still quite tight. Once the algorithm of the algorithm state machine in the controller is determined, the flexibility is also determined, that is, the atomic operation of the algorithm in this mode is not completely realized. SUMMARY

[0005] In order to solve the technical problems of tight coupling between the controller and the outer module and low flexibility in the prior art, the present application proposes a new test method and test system for memory.

[0006] The test method for memory proposed by the present application controls the test state and test flow of the corresponding memory to be tested through at least two layers of loop control and read-write sequence operation for each memory to be tested.

[0007] The at least two layers of loop control include:

[0008] The algorithm loop controls the execution of all algorithm steps for a memory under test, and terminates the test process for the corresponding memory under test after all algorithm steps have been executed.

[0009] The address loop iterates through the test address during each algorithm step. Each traversed address will be subjected to the read / write sequence operation. The address loop ends when the test address traversal is complete.

[0010] Furthermore, the loop control also includes executing an intra-word loop in each address loop process. When an intra-word loop exists in an address loop process, the read and write sequence operations in that address loop process are executed in each intra-word loop process.

[0011] Furthermore, at least once before the address cycle begins, the configuration of the test address mode is performed in the corresponding algorithm step.

[0012] Furthermore, after each sequence read operation, the test results are compared to determine if there is a fault. If a fault is found, the FAIL signal is set and output.

[0013] The memory testing system proposed in this invention includes a test controller and a memory outer layer control module. The test controller and the memory outer layer control module cooperate with each other and use the memory testing method described in the above technical solution to test at least one memory under test.

[0014] Furthermore, the test controller includes:

[0015] The internal signal control module receives external signals and instructions from the configuration instruction decoder, and provides and / or allocates basic signals to the various modules of the test controller;

[0016] The algorithm state machine module contains an algorithm state machine that is the same number as the number of memory devices under test. Each algorithm state machine is used to control the execution of all algorithm steps of a memory device under test.

[0017] The test control communication management module includes a communication server with the same number of memories under test. The communication server enables communication between the corresponding algorithm loop module of the algorithm state machine module and the corresponding memory outer layer control module.

[0018] The state machine decoding polling controller is connected to the algorithm state machine module and the configuration instruction decoder via the state machine decoding request bus. It is used to control the polling of the output state of each algorithm state machine and send the polled state to the configuration instruction decoder for decoding.

[0019] The configuration instruction decoder decodes the corresponding state to obtain a configuration instruction and sends the configuration instruction to the corresponding memory outer control module.

[0020] Further, the communication server is in signal connection with a test control communication client in the corresponding memory outer control module, for feeding back the current working state of the test controller and understanding the current working state of the corresponding memory outer control module.

[0021] Further, the communication server is in signal connection with the corresponding algorithm state machine, for understanding the state of the current algorithm step and controlling the algorithm step switching.

[0022] Further, the memory outer control module comprises:

[0023] a data generator which selects a test background data generation mode required in the current algorithm step according to the configuration instruction of the test controller, generates corresponding test background data, and sends the test background data to the input signal multiplexer;

[0024] an address generator which selects a test address generation mode required in the current algorithm step according to the configuration instruction, generates corresponding test address, and sends the test address to the input signal multiplexer;

[0025] a read-write controller which selects a read-write sequence operation required in the current algorithm step according to the configuration instruction, and sends a test read-write signal corresponding to the read-write sequence operation to the input signal multiplexer;

[0026] an input signal multiplexer which receives test signals generated by the data generator, the address generator and the read-write controller, and also receives functional signals input by external circuits, judges whether to be in a test state according to a test mode signal, and when the device is in the test state, selects to send the test signals to the memory under test, otherwise, sends the functional signals to the memory under test.

[0027] a comparator which receives data signals input to the memory under test by the memory outer control module and data output signals of the memory under test, and compares the two, and the comparison result is fed back to the test controller.

[0028] Compared with the prior art, the present application has the following advantages:

[0029] The application realizes atomization of the MBIST algorithm (so-called algorithm atomization refers to dividing the test algorithm into a combination of multiple algorithm operation sequences, and each algorithm operation sequence is an algorithm atom) by planning the test process as two-layer or three-layer loops in the form of basic read-write operation sequences on the basis of isolating the algorithm from the external memory control module. Meanwhile, the algorithm and the external memory control module are isolated from each other, and the specific operation of the algorithm depends on the corresponding configuration mode of the internal algorithm steps of the external memory control module. When the configuration modes in different external memory control modules are different, the same algorithm steps can realize completely different algorithms in each external memory control module, further improving the test flexibility and applicability of the system.

[0030] The application decouples the binding relationship between different external memory control modules and algorithm state machines in the test controller by configuring an instruction decoder, a polling controller and a corresponding decoding request bus. When controlling multiple external memory control modules, the modules in each group are completely independent and do not interfere with each other, improving the flexibility and diversity of the application scenarios of the test system.

[0031] The application can adapt to algorithms with inter-word data loops, further improving the test flexibility and algorithm applicability.

[0032] The application can also start the function of user-defined address loop by the setting function of the software, and the address loop range can be specified. BRIEF DESCRIPTION OF DRAWINGS

[0033] The application will be described in detail below in combination with embodiments and drawings, in which:

[0034] Figure 1 is a schematic diagram of the overall structure of an embodiment of the application.

[0035] Figure 2 is an internal architecture diagram of the test controller of an embodiment of the application.

[0036] Figure 3 is an internal architecture diagram of the external memory control module of an embodiment of the application.

[0037] Figure 4 is a test flowchart of an embodiment of the application. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects of the application clearer, the application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0039] Thus, one of skill in the art will appreciate that a statement that a feature is "in one embodiment" does not mean that the feature is required in all or in any embodiment. Further, one of skill in the art will appreciate that, where a feature is described as being in "one embodiment" or "some embodiments" and one or more features are described as being in "another embodiment" or "some embodiments", different combinations of features described as being in one or more embodiments can be combined with features described as being in another one or more embodiments.

[0040] Currently, the hot field and the recognized direction of progress of the next generation of MBIST architecture is to try to achieve the atomization of MBIST algorithm operation. The memory test method proposed in the application solves the test drawbacks of the traditional MBIST structure, re-plans the whole test flow based on the idea of algorithm atomization, and can be summarized as at least two operation cycles and a basic read-write operation sequence with quite wide algorithm adaptability. By respectively independently realizing different operation cycles in the test controller and the outer control module (peripheral module) of the memory, the algorithm process and the specific data and address generation process are further decoupled, and the algorithm operation atomization is realized more thoroughly. At the same time, the advantages of the current application architecture are maintained, such as user algorithm customization, and the inter-word data cycle function can be realized.

[0041] A basic embodiment of the memory test method of the application is described below.

[0042] The memory test method of the application realizes the control of the test state and test flow of the corresponding memory to be tested through at least two layers of cycle control and read-write sequence operation for each memory to be tested.

[0043] The at least two layers of cycle control include algorithm cycle and address cycle.

[0044] Each memory to be tested has a corresponding set of algorithm cycles, each algorithm cycle controls the execution of all algorithm steps of a memory to be tested, and ends the test flow of the corresponding memory to be tested after the execution of all algorithm steps.

[0045] The address cycle is responsible for traversing the test address during the execution of each algorithm step, and each traversed address will be executed by the read-write sequence operation. When the test address traversal is completed, the address cycle ends. The test address is traversed in each algorithm step, and part of the test address or all the test address can be traversed according to the specific algorithm.

[0046] On the basis of the above-mentioned embodiments, the loop control can further comprise a third layer loop control, i.e. a word loop. The word loop exists in at least one address loop, and when the word loop exists in an address loop, the read / write sequence operation in the address loop is executed in each word loop.

[0047] The mode of each address loop can also be different, and thus in an embodiment, before each address loop starts, the configuration of the test address mode is performed in the corresponding algorithm step. The test address mode specifically refers to the mode of the generation of the test address, and the contents that can be determined by the mode can be, for example, the variation order of the test address, the start address of the test address, and the like.

[0048] In an embodiment, after each read sequence operation, the test result comparison can also be performed, and it is determined whether there is a fault, and if there is a fault, the corresponding signal is output.

[0049] The test system of the memory of the present application at least comprises a test controller and a memory outer control module, and the test controller and the memory outer control module cooperate with each other to test at least one to-be-tested memory by using the test method of the memory of the above-mentioned technical solution.

[0050] Figure 1 An embodiment of the test system of the memory of the present application is shown, and in the embodiment, the test system comprises a test controller, a memory outer control module, and a comparator.

[0051] The main function of the test controller is to control the test state and the test flow. The input end of the test controller is connected with an external test clock signal (clk), a test reset signal (reset), and a test start signal (T_start). The configuration instruction signal, the test mode (test_Mode), and the test chip selection enable, clock, reset, and the like of the output end of the test controller are connected with the memory outer control module, the test controller sends the configuration instruction to the memory outer control module, selects the test mode, and performs test initialization on the memory outer control module, and the like. The test completion signal and the test failure signal of the output end of the test controller are used as the total output end, and are used for feeding back the test result of the corresponding to-be-tested memory. The test controller and the memory outer control module are further connected through a communication signal, and are used for realizing the communication interaction between the test controller and the memory outer control module.

[0052] The main function of the memory outer control module is to perform corresponding algorithm operation on the to-be-tested memory according to the received configuration instruction. The number of the memory outer control module is consistent with the number of the to-be-tested memory, and each memory outer control module controls the test of one to-be-tested memory. There is a communication signal between the memory outer control module and the test controller, which is used for communication interaction with the test controller. The read-write signal, data signal, address signal and other memory control signals of the output end of the memory outer control module are connected with the corresponding to-be-tested memory, and are used for algorithm test operation on the to-be-tested memory.

[0053] The main function of the comparator module is to judge the test result of each step of the test algorithm, receive the data signal input to the to-be-tested memory from the memory outer control module and the output signal of the to-be-tested memory, and compare them, and finally feed back the comparison result to the test controller.

[0054] As shown in Figure 2 In one specific embodiment, the test controller includes an internal signal control module, an algorithm state machine module, a test control communication management module, a state machine decoding polling controller and a configuration instruction decoder.

[0055] The internal signal control module receives external signals and provides and / or distributes basic signals for each module of the test controller.

[0056] The internal signal control module provides appropriate clock, chip select enable, reset and other basic signals for each module of the test controller under the MBIST architecture according to the test requirements. The internal signal control module receives the test clock (clk), test reset signal (reset) and test start signal (T_start) from the outside, and distributes clock, chip select enable, reset, test mode and other test basic signals for each module in the test controller and the memory outer control module. At the same time, the internal signal control module will feed back test completion and test failure and other test result signals according to the working state of the test.

[0057] The algorithm state machine module includes algorithm state machines consistent with the number of to-be-tested memories, and each algorithm state machine is used to control one algorithm cycle (such as test algorithm FSM 1). The execution of each algorithm cycle is to realize the execution of all algorithm steps of one to-be-tested memory.

[0058] The algorithm state machine module is mainly used for generating and switching algorithm steps. The algorithm state machine module receives interaction signals from the communication server, determines the receiving and completion of the configuration instructions sent by the test controller to the memory outer layer control module, switches to the next step based on the algorithm step when it is determined that the sent configuration instructions are successfully received, and feeds back to the algorithm communication server that the configuration is ready when it is determined that the test configuration of the previous step is completed. The algorithm state machine, the communication server, and the memory outer layer control module all adopt a one-to-one allocation mode. That is, one memory to be tested corresponds to one memory outer layer control module, one communication server, and one algorithm state machine.

[0059] The test control communication management module includes a communication server consistent with the number of memories to be tested. The communication server realizes the communication between the corresponding algorithm loop module of the algorithm state machine module and the corresponding memory outer layer control module.

[0060] The test control communication management module is mainly used for communication interaction with the test control communication client of each memory outer layer control module. The test control communication management module can include multiple communication servers (also called algorithm communication servers) inside. Each communication server has a corresponding algorithm state machine and a test control communication client of the memory outer layer control module. Each communication server inside is connected with the communication client in the corresponding memory outer layer control module through communication signals, which is used to feedback the current working state of the test controller, such as the preparation of the configuration instructions, and to understand the current working state of the memory outer layer control module, such as the configuration receiving condition, the configuration test completion condition, etc. At the same time, each communication server also interacts with the corresponding algorithm state machine, which is used to understand the current algorithm step state and to control the algorithm step switching. That is, the communication server and the test control communication client in the corresponding memory outer layer control module are connected through communication signals, which is used to feedback the current working state of the test controller and to understand the current working state of the corresponding memory outer layer control module. The communication server and the corresponding algorithm state machine are connected through communication signals, which is used to understand the current algorithm step state and to control the algorithm step switching.

[0061] The state machine decoding polling controller is connected to the algorithm state machine module and the configuration instruction decoder via the state machine decoding request bus. The controller controls the polling of the output states of each algorithm state machine and sends the polled states to the configuration instruction decoder for decoding. The controller determines the completion status of the previous configuration test step for each memory under test and sorts the instructions of the next round of algorithm state machines according to the order of completion. It then controls the decoding request bus and the configuration instruction decoder to send the algorithm state machine states to the configuration instruction decoding module for decoding, obtaining the configuration instructions.

[0062] The configuration instruction decoder receives the state of the algorithm state machine from the decoding request bus according to the control of the state machine decoding polling controller, and decodes it into the corresponding configuration instruction signal and sends it to the outer layer control module of the memory.

[0063] like Figure 3 As shown, in one embodiment, the memory outer layer control module includes a data generator, an address generator, a read / write controller, and an input signal multiplexer.

[0064] The data generator selects the required test background data generation mode for the current algorithm step according to the configuration instructions of the test controller, generates the corresponding test background data, and sends the test background data to the input signal multiplexer.

[0065] The address generator, based on the configuration instructions, selects the test address generation mode required for the current algorithm step, generates the corresponding test address signal, and sends the test address signal to the input signal multiplexer. The address generator also includes a test control communication client, which communicates with the test controller's communication server to obtain the test controller's configuration readiness status. When the current configuration test is complete and it is known that the next configuration step is ready, the outer control module of the control memory receives the next configuration instruction; simultaneously, it sends a communication signal to the communication server to provide feedback on the configuration reception and configuration operation completion status.

[0066] The read / write sequence controller selects the read / write sequence operation required for the current algorithm step according to the configuration instructions, and sends the test read / write enable signal corresponding to the read / write sequence operation to the input signal multiplexer.

[0067] The input signal multiplexer receives test signals generated by the data generator, address generator, and read / write sequence controller, as well as function signals from external circuits. It determines whether it is in test mode based on the test mode signal. When in test mode, it sends test signals to the memory under test; otherwise, it sends function signals to the memory under test.

[0068] By the technical solution, the binding relationship between different memory outer layer control modules and corresponding algorithm state machines is decoupled through the state machine decoding polling controller, the state machine decoding request bus and the configuration instruction decoder. When the algorithm state in the test controller controls multiple memory outer layer control modules, each group of modules is completely independent and does not interfere with each other, and the flexibility and diversity of the application scene of the test system are improved. Here, one group of modules includes one algorithm state machine, one communication server and one memory outer layer control module.

[0069] Figure 4 This is a preferred embodiment of the present application, which is based on the idea of atomization and performs MBIST test on the to-be-tested memory. The detailed process of the test method is as follows. Step 401, the external (test protocol, such as IEEE1687, etc., or a hardware test network conforming to the test protocol) gives an excitation, makes a test start signal valid, gives a test clock, the internal control signal generation module accesses the clock and other signals and makes the circuit enter a test mode, and starts to start this MBIST test.

[0070] Step 402, enter the test preparation phase, the external gives an excitation, makes a test enable signal and a test reset signal valid, and the internal signal controller performs test initialization preparation of enabling and resetting the modules of the MBIST circuit and the to-be-tested memory. At the same time, the state machine makes test preparation for the first step algorithm step state.

[0071] Step 403, the algorithm state machine sends the first step test state according to the test algorithm requirement, and the first step test state is decoded into a corresponding configuration instruction. The configuration instruction is sent to the memory outer layer control module for configuration; each time entering step 403, the algorithm step is rotated, that is, the next step is entered, the test state of the next step is sent, and the test state of the next step is decoded into a corresponding configuration instruction, etc.

[0072] Step 404, the address generator receives the configuration instruction, sets the start address, end address and address change mode of the test address according to the configuration instruction, etc.

[0073] Step 405, the address generator generates an initial address for testing according to the configuration mode in step 404, and each time entering step 405, a new address is generated according to the configuration mode until the end address bit is reached.

[0074] Step 406, it is judged whether the word fault test is needed, if yes, step 407 is entered; if no, step 409 is entered.

[0075] Step 407, the data generator receives the configuration instruction, and prepares the test background data required for testing the fault in the test word according to the configuration instruction, sets the initial test background data and the change order of the subsequent test background data.

[0076] Step 408, the data generator generates the initial test background data for testing according to the generation mode of the test background data configured in step 407, and each subsequent entry into step 408 will rotate the test background data according to the configured mode.

[0077] Step 409, the data generator receives the configuration instruction, selects a test background data according to the configuration instruction, and outputs it to the memory under test for testing.

[0078] Step 410, the read-write signal controller receives the configuration instruction, sets the read-write sequence according to the test algorithm of this step, and performs the read-write sequence operation on the test data of the current test address of the memory under test; at the same time, when performing the read operation, the read data and the test data are output to the comparator for comparison, and the result is fed back to the controller.

[0079] Step 411, according to the comparison result, it is judged whether the memory under test has a fault, if yes, step 412 is entered, if not, step 413 is entered.

[0080] Step 412, the memory fault is detected, and the test failure signal is valid and output.

[0081] Step 413, the data generator will judge whether all the test background data in this mode have been output according to the configured mode, if yes, step 414 is entered; if not, step 408 is entered.

[0082] Step 414, the address generator will judge whether the test address has been output according to the configured mode, if yes, step 415 is entered; if not, step 405 is entered to realize address cycle.

[0083] Step 415, the algorithm state machine will judge whether the state of all algorithm steps corresponding to this algorithm has been sent (i.e. all steps of this algorithm have been completed), if yes, step 416 is entered; if not, step 403 is entered to realize algorithm cycle.

[0084] Step 416, wait for all memory outer control module tests to be completed, when all tests have been completed, the test completion signal is valid and output.

[0085] Step 417, the MBIST test is completed.

[0086] The above merely describes preferred embodiments of the present application and is not intended to limit the present application, and the technical solutions of the present application can be applied in various occasions, and the present application does not limit the specific purpose of the test, and the specific purpose of the test can be to test the failure of the memory, or to test the performance of the memory, etc., when the present application is applied to test the failure, the comparator can be a separate module independent of the test controller and the outer controller module of the memory, in different embodiments, the comparator can also be arranged in the test controller or the outer controller of the memory, and any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory test system comprising a test controller and a memory outer layer control module, characterized in that, The test controller and the memory outer layer control module cooperate with each other, and a test method of the memory is used to test at least one to-be-tested memory; The test controller comprises: An internal signal control module which receives external signals and provides and / or distributes basic signals for each module of the test controller; An algorithm state machine module which comprises algorithm state machines consistent with the number of to-be-tested memories, and each algorithm state machine is used to control execution of all algorithm steps of one to-be-tested memory; A test control communication management module which comprises communication servers consistent with the number of to-be-tested memories, and the communication servers realize communication between the memory outer layer control modules corresponding to the algorithm state machines; A state machine decoding polling controller which is connected with a configuration instruction decoder through a state machine decoding request bus, and is used to control polling of states output by each algorithm state machine to the decoding request bus and send the polled states to the configuration instruction decoder for decoding; The configuration instruction decoder decodes the corresponding states to obtain configuration instructions and sends the configuration instructions to the corresponding memory outer layer control module; The test method of the memory realizes control of a test state and a test flow of each to-be-tested memory through at least two layers of loop controls and read-write sequence operations for each to-be-tested memory; The at least two layers of loop controls comprise: An algorithm loop which controls execution of all algorithm steps of one to-be-tested memory and ends the test flow of the corresponding to-be-tested memory after execution of all algorithm steps is completed; An address loop which traverses test addresses during execution of each algorithm step, and each traversed address is subjected to the read-write sequence operation, and the address loop ends when the test addresses are traversed.

2. The memory testing system of claim 1, wherein, The loop control further comprises execution of an intra-word loop during at least one address loop, and the read-write sequence operation in the address loop is executed during each intra-word loop when the intra-word loop exists in the address loop.

3. The memory testing system of claim 1 or 2, wherein, Before each address loop starts, a test address mode is configured in the corresponding algorithm step.

4. The memory testing system of claim 1 or 2, wherein, After each read sequence operation, a test result is compared, and it is determined whether a fault exists, and if the fault exists, a corresponding signal is output.

5. The memory testing system of claim 1, wherein, The communication server is connected with a test control communication client in the corresponding memory outer layer control module through a communication signal, and is used to feed back a current working state of the test controller and understand a current working state of the corresponding memory outer layer control module.

6. The memory testing system of claim 1, wherein, The communication server is connected with the corresponding algorithm state machine through a communication signal, and is used to understand a state of a current algorithm step and control switching of the algorithm step.

7. The memory testing system of claim 1, wherein, The memory outer layer control module comprises: A data generator which selects a generation mode of test background data required in a current algorithm step according to a configuration instruction of the test controller, generates corresponding test background data, and sends the test background data to an input signal multiplexer; an address generator, which selects a generation mode of a test address required in a current algorithm step according to the configuration instruction, generates a corresponding test address, and sends the test address to the input signal multiplexer; a read-write controller, which selects a read-write sequence operation required in the current algorithm step according to the configuration instruction, and sends a test read-write sequence corresponding to the read-write sequence operation to the input signal multiplexer; the input signal multiplexer receives internal signals generated by the data generator, the address generator, and the read-write controller, and receives functional input signals of external circuits, judges whether it is in a test state according to a test mode signal, inputs a test signal to the memory under test when it is in the test state, and otherwise sends functional signals to the memory under test.

8. The memory testing system of any one of claims 5 to 7, wherein, a comparator, which receives data signals input to the memory under test by the memory outer control module and output signals of the memory under test, compares them, and feeds back a comparison result to the test controller.

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