Method for modifying a semiconductor mask pattern and semiconductor structure

Abstract

The present application discloses a semiconductor mask pattern correction method and a semiconductor structure thereof. The semiconductor mask pattern correction method comprises the following steps: firstly, dividing a to-be-corrected pattern in a semiconductor mask pattern into a plurality of symmetrical sub-blocks which are symmetrical to each other and can be overlapped. Then, performing optical approximate correction on one of the plurality of symmetrical sub-blocks to obtain a correction template. At least one correction template copy is generated according to the correction template for other symmetrical sub-blocks. The correction template and the at least one correction template copy are spliced to form a combined correction pattern to replace the original to-be-corrected pattern.

Description

Technical Field

[0001] This invention relates to a semiconductor fabrication process and semiconductor structure thereof, and particularly to a method for modifying a semiconductor mask pattern and a semiconductor structure fabricated using this modification method. Background Technology

[0002] Photolithography is a crucial and vital step in semiconductor manufacturing. A typical photolithography process involves exposing a photoresist layer on a semiconductor substrate (e.g., a silicon wafer) to light through a photomask, creating an exposure pattern associated with the photomask pattern. The pattern is then transferred to the substrate via an etching process.

[0003] However, due to diffraction when light waves pass through a photomask, and interference between light waves at different positions on the photomask, the actual light intensity distribution projected onto the photoresist layer is the result of the superposition of these diffracted light waves. Therefore, the exposure pattern on the photoresist layer will not be exactly the same as the photomask pattern. This phenomenon of deviation between the exposure pattern and the photomask pattern due to light wave diffraction and interference is called the Optical Proximity Effect (OPE). When the critical dimension (CD) on the photomask pattern is much larger than the wavelength of light, the deviation between the exposure pattern and the photomask pattern is relatively insignificant. However, as the feature size of integrated circuits continues to shrink into ultra-deep submicron fabrication processes (critical dimensions between 0.13 micrometers and even below 0.09 micrometers), this deformation and deviation become increasingly severe, directly affecting integrated circuit performance and fabrication yield.

[0004] To minimize deformation and deviation between the exposure pattern and the photomask pattern, suppress the negative effects of optical proximity, and thus improve the yield of integrated circuit manufacturing processes, Optical Proximity Correction (OPC) has been widely applied in the design and correction of photomask patterns. Current OPC techniques typically utilize proximity correction modeling tools to simulate light diffraction and interference principles, adjusting the designed photomask pattern, especially the positions of its edges. The adjusted photomask pattern is then exposed, and the distance between corresponding edges of the actual exposure pattern and the photomask pattern is calculated and compared to a predetermined threshold. This process is repeated until the obtained distance is less than the predetermined threshold, ensuring that the actual exposure pattern matches the optimized photomask pattern.

[0005] However, the repeated process of adjustment, measurement, and comparison not only incurs significant costs for photomask processing, chip printing, measurement, and equipment calibration, but is also extremely time-consuming, severely limiting production efficiency.

[0006] Therefore, there is a need to provide an advanced method for correcting semiconductor mask patterns and a semiconductor mask thereof to solve the problems faced by the prior art. Summary of the Invention

[0007] An embodiment of the present invention discloses a method for correcting a semiconductor mask pattern. This method includes the following steps: First, dividing a pattern to be corrected in the semiconductor mask pattern into multiple symmetrical sub-blocks that are symmetrical and overlaptable. Then, performing optical proximity correction (OPC) on one of the multiple symmetrical sub-blocks to obtain a corrected template. Generating at least one copy of the corrected template corresponding to the other multiple symmetrical sub-blocks. Finally, splicing the corrected template and the at least one copy of the corrected template to form a combined corrected pattern that replaces the original pattern to be corrected.

[0008] According to the above embodiments, the present invention provides a method for correcting semiconductor mask patterns. This method involves providing or identifying a pattern to be corrected that can be divided into multiple symmetrical and overlapping sub-blocks within the semiconductor mask pattern. Only one sub-block undergoes optical approximation correction to obtain a correction template. Then, based on the number of symmetrical sub-blocks, the correction template is copied to generate at least one copy. These copies are then stitched together to form a combined correction pattern, directly replacing the original pattern to be corrected. Since only one sub-block of the pattern to be corrected needs optical approximation correction, the correction result of the entire pattern can be obtained by copying the correction template. This significantly reduces the number of steps and the scope of optical approximation correction, lowers the costs of photomask processing, chip printing, measurement, and equipment calibration required for pattern correction, saves correction time, and improves the efficiency of the photolithography process. Attached Figure Description

[0009] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

[0010] Figure 1A A flowchart illustrating the steps of a method for correcting a semiconductor mask pattern according to an embodiment of the present invention;

[0011] Figures 1B to 1D To implement Figure 1A A schematic diagram illustrating the changes in the semiconductor mask pattern during the semiconductor mask pattern correction method;

[0012] Figure 2A A flowchart illustrating the steps of a method for correcting a semiconductor mask pattern, as shown in another embodiment of the present invention;

[0013] Figures 2B to 2D To implement Figure 2A A schematic diagram illustrating the changes in the semiconductor mask pattern during the method for correcting the semiconductor mask pattern;

[0014] Figures 3A to 3C This illustration is for another embodiment of the present invention. Figure 2A A schematic diagram illustrating the changes in the semiconductor mask pattern during the process of correcting the semiconductor mask pattern using the method described above.

[0015] Figures 4A to 4C The illustration is for another embodiment of the present invention. Figure 2A The method described includes a schematic diagram illustrating the changes in the semiconductor mask pattern during mask pattern correction; and...

[0016] Figure 5 for Figures 2A to 2D A cross-sectional schematic diagram of the semiconductor structure produced by the semiconductor mask pattern correction method.

[0017] Symbol Explanation

[0018] 100: Semiconductor mask pattern

[0019] 101: Pattern to be corrected

[0020] 101A, 101B: Sub-blocks

[0021] 101A1: Sub-block pattern

[0022] 102: Optical Approximation Correction

[0023] 111: Combined Correction Pattern

[0024] 111A: Modify Template

[0025] 111B: Correction of template copy

[0026] 111A1: Correct template pattern

[0027] 200: Semiconductor mask pattern

[0028] 201: Pattern to be corrected

[0029] 201A~201H: Sub-blocks

[0030] 201A1: Sub-block pattern

[0031] 201AS: Edge Area

[0032] 202, 212: Optical Approximation Corrections

[0033] 203: Surrounding Area

[0034] 203A: Buffer Pattern

[0035] 203B: Edge Pattern

[0036] 211: Combined Correction Pattern

[0037] 211A: Modified Template

[0038] 211B1~211B7: Corrected template copies

[0039] 211A1: Modify template pattern

[0040] 221A: Expanded Correction Template

[0041] 300: Semiconductor mask pattern

[0042] 301AS: Edge Area

[0043] 302, 312: Optical approximation corrections

[0044] 303: Surrounding Area

[0045] 303A~303H: Sub-blocks

[0046] 311A: Modify Template

[0047] 311B1~311B7: Correction of template copies

[0048] 321A: Expanded Correction Template

[0049] 400: Semiconductor mask pattern

[0050] 401A~401H: Sub-blocks

[0051] 402: Optical Approximation Correction

[0052] 403: Surrounding Area

[0053] 411A: Modify Template

[0054] 411B1~411B7: Correction of template copies

[0055] 421A: Expanded Correction Template

[0056] 50: Semiconductor Structure

[0057] 51: Translucent substrate

[0058] 51a: Surface of translucent substrate

[0059] 511: Columnar protrusion

[0060] 512: Depression

[0061] 500: Planar optical matrix

[0062] H, H', H”: Distance

[0063] L1: Axis of symmetry

[0064] P: Center of symmetry

[0065] θ: central angle

[0066] S11: Divide a pattern to be corrected in a semiconductor mask pattern into multiple symmetrical sub-blocks that can be symmetrical and coincident with each other.

[0067] S12: Perform optical approximation correction on one of the multiple symmetric sub-blocks to obtain a correction template.

[0068] S13: Generate at least one copy of the modified template based on the other of the multiple symmetric sub-blocks corresponding to the modified template.

[0069] S14: Combine the correction template and the copy of the correction template to form a combined correction pattern to replace the original pattern to be corrected.

[0070] S21: Divide a pattern to be corrected in a semiconductor mask pattern into multiple symmetrical sub-blocks that can be symmetrical and coincident with each other.

[0071] S22: Perform optical approximation correction on one of the multiple symmetric sub-blocks to obtain a correction template.

[0072] S221: Expand the range of the sub-block to be optically approximated to the edge region of the sub-block, and then perform optical approximation correction to form an expanded correction template.

[0073] S222: Shave off the portion of the enlarged correction template corresponding to the edge region to form the correction template.

[0074] S23: Generate at least one copy of the modified template based on the other of the multiple symmetric sub-blocks corresponding to the modified template.

[0075] S24: Combine the correction template and the copy of the correction template to form a combined correction pattern to replace the original pattern to be corrected.

[0076] S25: Perform additional optical approximation corrections on the surrounding area. Detailed Implementation

[0077] This specification provides a method for correcting semiconductor mask patterns and a semiconductor mask thereof, which can solve the problems of high processing cost, long processing time, and reduced production efficiency of existing optical proximity correction technology. To make the above embodiments and other objects, features, and advantages of this specification more apparent and understandable, several embodiments are described below in detail with reference to the accompanying drawings.

[0078] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0079] Please refer to Figures 1A to 1D , Figure 1A This is a flowchart illustrating a method for modifying a semiconductor mask pattern according to an embodiment of this specification. Figures 1B to 1D It is a drawing implementation Figure 1A A schematic diagram illustrating the changes in the semiconductor mask pattern 100 during the correction method.

[0080] The method for correcting a semiconductor mask pattern 100 includes the following steps: First, as shown in step S11, a pattern 101 to be corrected in the semiconductor mask pattern 100 to be formed on a semiconductor mask (not yet formed, therefore not shown) is divided into a plurality of symmetrical sub-blocks (e.g., sub-blocks 101A and 101B) that are symmetrical and overlap each other. In some embodiments of this specification, the pattern 101 to be corrected may be a portion of the semiconductor mask pattern 100. In other embodiments, the semiconductor mask pattern 100 and the pattern 101 to be corrected substantially overlap.

[0081] In this embodiment, the semiconductor mask pattern 100 and the pattern to be corrected 101 substantially overlap. Furthermore, the pattern to be corrected 101 can be an axis-paired pattern. That is, the pattern to be corrected 101 can be divided into two symmetrical sub-blocks 101A and 101B along the axis of symmetry L1. Sub-blocks 101A and 101B each contain a sub-block pattern 101A1 composed of multiple strip-shaped or branch-shaped pattern units (e.g., ...). Figure 1B shown).

[0082] Next, as shown in step S12: an optical approximation correction 102 is performed on one of the multiple symmetrical sub-blocks (e.g., sub-block 101A) to obtain a corrected template 111A. In some embodiments of this specification, the optical approximation correction 102 may employ computer software to perform optical simulation of the sub-block pattern 101A1 in the sub-block 101A of the pattern 101 to be corrected, taking into account parameters such as photomask material, pattern size, and optical proximity effect, based on the principles of light wave diffraction and interference, and adjust the edge positions of each sub-block pattern 101A1.

[0083] For example, in this embodiment, the optical approximation correction 102 is a simulation model software provided by Mentor Graphics and verified through chip testing. OPCverify performs optical simulation on the sub-block pattern 101A1 within the sub-block 101A of the pattern 101 to be corrected. Based on the principle of optical diffraction, it adjusts the endpoints, edges, and corners of the elongated or branched pattern units of the sub-block pattern 101A1 within the sub-block 101A to obtain, for example... Figure 1C The correction template 111A is shown. It is expected that the actual exposure pattern (not shown) obtained after exposure of the correction template pattern 111A1 in the correction template 111A will be as close as possible to the correction sub-block pattern 101A1 in the sub-block 101A.

[0084] The following steps are as follows: At least one copy of the correction template 111B is generated based on the other symmetrical sub-blocks (e.g., sub-block 101B) corresponding to the correction template 111A. Then, as shown in step S14, the correction template 111A and the copy of the correction template 111B are spliced ​​together to form a combined correction pattern 111 to replace the original pattern 101 to be corrected, thus completing the correction of the semiconductor mask pattern 100.

[0085] In this embodiment, the correction template pattern 111A1 in the correction template 111A is copied to generate a correction template copy 111B corresponding to the sub-block 101B. These correction templates 111A and correction template copies 111B are then correspondingly spliced ​​together to form a combined correction pattern 111 that replaces the original pattern 101 to be corrected. The correction templates 111A and correction template copies 111B are mirror-spliced ​​along the axis of symmetry L1 to form... Figure 1D The illustrated combined correction pattern 111.

[0086] Since the combined correction pattern 111 after splicing is composed of two symmetrical and superimposed correction template patterns 111A1, it is roughly the same as the result obtained by performing two optical approximation corrections 102 on each sub-block 101A and 101B in the pattern to be corrected 101. In other words, the correction method of semiconductor mask pattern used in this embodiment (such as...) Figure 1A (As illustrated), this method can save half the steps and correction time consumed by optical approximation correction 102. Therefore, it can significantly reduce the costs of photomask processing, wafer printing, measurement and equipment calibration consumed in optical approximation correction of semiconductor mask pattern 100, save correction time, and improve the efficiency of photolithography process.

[0087] Please refer to Figures 2A to 2D , Figure 2A This is a flowchart illustrating a method for modifying a semiconductor mask pattern 200 according to another embodiment of this specification. Figures 2B to 2D It is a drawing implementation Figure 2A A schematic diagram illustrating the changes in the semiconductor mask pattern 200 during the method for correcting the semiconductor mask pattern 200.

[0088] Figure 2A The method for correcting the semiconductor mask pattern shown includes the following steps: First, as shown in step S21, one of the patterns 201 to be corrected in the semiconductor mask pattern 200 to be formed on the semiconductor mask (not yet formed, so not shown) is divided into a plurality of symmetrical sub-blocks (e.g., 8 sub-blocks 201A to 201H) that can be symmetrical to each other and can overlap.

[0089] In this embodiment, the size of the semiconductor mask pattern 200 is larger than that of the correction pattern 201; a portion of the semiconductor mask pattern 200 near its center point can serve as the correction pattern 201; each side of the correction pattern 201 to the periphery of the semiconductor mask pattern 200 can include a peripheral region 203 surrounding the correction pattern 201.

[0090] like Figure 2B As illustrated, the pattern 201 to be corrected can be a rotational pair pattern. That is, the pattern 201 to be corrected has a center of symmetry P, and is divided into eight sub-blocks 201A to 201H that are symmetrical and overlappable with respect to the central angle θ (e.g., θ equals 45°) of the center of symmetry P. Each sub-block 201A to 201H contains a sub-block pattern 201A1 composed of multiple circular pattern units of the same size. However, in other embodiments, the shape, size, and number of pattern units in the pattern 201 to be corrected are not limited.

[0091] In some embodiments of this specification, the peripheral region 203, located away from the pattern 201 to be corrected, has at least one portion that is symmetrical and overlaps with another portion. For example, in this embodiment, the peripheral region 203 can be divided into a buffer pattern 203A adjacent to the pattern 201 to be corrected and an edge pattern 203B located away from the pattern 201 to be corrected. The buffer pattern 203A, like the pattern 201 to be corrected, can be divided into eight symmetrical and overlappable sub-blocks (not shown) with a central angle θ around the center of symmetry P. The edge pattern 203B does not have a symmetrical and overlappable other portion.

[0092] Although edge pattern 203B and pattern 201 to be corrected are adjacent to each other and can both be divided into the same number of symmetrical and overlapping sub-blocks, considering that edge pattern 203B is adjacent to edge pattern 203B, the diffraction and interference of light waves will cause the buffer pattern 203A to be affected by the optical proximity effect. Therefore, when performing subsequent optical approximation correction 202, edge pattern 203B and pattern 201 to be corrected are specifically processed separately.

[0093] Next, as shown in step S22: an optical approximation correction 202 is performed on one of the plurality of symmetrical sub-blocks (e.g., sub-block 201A) to obtain a correction template 211A. In this embodiment, the optical approximation correction 202 includes the following steps: First, as in step S221: the range of the sub-block (e.g., sub-block 201A) to be optically approximated 202 is expanded to the edge region 201AS of sub-block 201A, and then the optical approximation correction 202 is performed to form an expanded correction template 221A. Then, as in step S222: the portion of the expanded correction template 221A corresponding to the edge region 201AS is shaved off to form the correction template 211A.

[0094] In detail, expanding the formation of the correction template 221A involves extending the area to be optically approximated 202 outward by a distance H from the edge of the sub-block 201A. This expands the area to be optically approximated 202 to include not only the sub-block 201A but also the edge region 201AS, which consists of a portion of the peripheral region 203 and a portion of other adjacent sub-blocks (e.g., sub-blocks 201B to 201H). Then, optical approximation 202 is performed on the sub-block 201A and the edge region 201AS of the pattern 201 to be corrected. In this way, the optical proximity effect of the circular pattern units in the edge region 201AS on the sub-block pattern 201A1 of the sub-block 201A can be further considered and reduced during the optical approximation 202 process.

[0095] In this embodiment, the optical approximation correction step 202 is performed using simulation model software provided by Mentor Graphics and verified through chip testing. OPCverify performs optical simulation on each circular pattern unit in the sub-block 201A and edge region 201AS of the pattern 201 to be corrected, and adjusts the edges and sizes of each circular pattern unit according to the principle of optical diffraction to obtain the desired result. Figure 2C The enlarged correction template 221A is shown. It is desired that the actual exposure pattern (not shown) obtained after exposure of the correction template pattern 211A1 of the enlarged correction template 221A, after correction, can approximate as closely as possible to the sub-block pattern 201A1 of the sub-block 201A in the pattern 201 to be corrected. Then, the portion of the enlarged correction template 221A corresponding to the edge region 201AS is removed to form the correction template 211A.

[0096] Then, as shown in step S23: based on the other symmetrical sub-blocks (e.g., sub-blocks 201B to 201H) corresponding to the correction template 211A, at least one copy of the correction template (e.g., correction template copies 211B1 to 211B7) is generated. And as shown in step S24: the correction template 211A and these correction template copies 211B1 to 211B7 are spliced ​​together to form a combined correction pattern 211 to replace the original pattern 201 to be corrected.

[0097] In this embodiment, seven correction template copies 211B1 to 211B7 are generated based on the correction template 211A, corresponding to other sub-blocks 201B to 201H respectively. The correction template 211A and these seven correction template copies 211B1 to 211B7 are then concatenated together to form a combined correction pattern 211, replacing the original pattern 201 to be corrected. The correction template 211A and the correction template copies 211B1 to 211B7 are mirror images of each other with symmetry center P as the center to form the pattern 201. Figure 2D The illustrated combined correction pattern 211.

[0098] The following steps are as shown in step S25: other optical approximation corrections 212 are performed on the peripheral area 203 to complete the correction of the semiconductor mask pattern 200.

[0099] Because the combined correction pattern 211 after splicing is composed of eight symmetrical and overlapping correction template patterns 211A1, the result is the same as that obtained by performing optical approximation correction 202 on the pattern 201 to be corrected alone. In other words, the semiconductor mask pattern correction method used in this embodiment (such as...) Figure 2AAs illustrated, this can save 7 / 8 of the optical approximation correction 202 process and correction time. If the number of sub-blocks in the pattern 201 to be corrected is n, and the time for each optical approximation correction 202 is t, then (n-1)×t / n of correction time can be saved. Therefore, the costs of photomask processing, chip printing, measurement, and equipment calibration consumed in the overall optical approximation correction of the semiconductor mask pattern 200 can be greatly reduced, and correction time can be saved, thereby improving the efficiency of the photolithography process.

[0100] Please refer to Figures 3A to 3C , Figures 3A to 3C This is a further embodiment of the present specification, illustrating the use of... Figure 2A The method described above illustrates the changes in the semiconductor mask pattern 300 during the mask pattern correction process. Figures 3A to 3C The correction method shown is roughly the same as Figures 2B to 2D The steps of the correction method are the same (e.g.) Figure 2A The main difference lies in the edge pattern of the peripheral region 303 of the semiconductor mask pattern 300, the formation method of expanding the correction template 321A, the range of optical approximation correction 302, and the method of shaving the edge region 301AS.

[0101] Since the step of dividing a pattern 201 to be corrected in the semiconductor mask pattern 300 to be formed on the semiconductor mask (not yet formed, so not shown) into multiple symmetrical sub-blocks (e.g., 8 sub-blocks 201A to 201H) that can be symmetrically formed and overlapped with each other (as described in step S21) has been detailed in Figure 2B Therefore, it will not be elaborated further here. The correction method described in this embodiment is described starting from step S221.

[0102] In this embodiment, the edge pattern of the peripheral region 303 is the same as that of the pattern 201 to be corrected, and it can be divided into eight sub-blocks 303A to 303H that are symmetrical and overlapping with each other by a central angle θ of the center of symmetry P. The formation of the correction template 321A is to extend the range of the optical approximation correction 302 from the edge of the sub-block 201A outward by a distance H', so that the range of the optical approximation correction 302 includes not only the sub-block 201A, but also the edge region 301AS composed of a portion of the edge pattern of the peripheral region 303 (e.g., a portion of the sub-blocks 303A, 303B and 303H) and a portion of other adjacent sub-blocks (e.g., sub-blocks 201B to 201H).

[0103] Next, the sub-block 201A and edge region 301AS of the pattern 201 to be corrected are optically approximated and corrected 302 to form an enlarged correction template 321A. In this way, during the optical approximation correction 302 process, the effect of circular pattern units in the peripheral region 303 on sub-block 201A (see reference) can be further considered and reduced. Figure 2B The optical proximity effect produced by the sub-block pattern 201A1 of the pattern 201 to be corrected. It is desired that the actual exposure pattern (not shown) obtained after exposure of the corrected template pattern 311A1 of the enlarged corrected template 321A will approximate as closely as possible to the sub-block pattern 201A1 of the sub-block 201A in the pattern 201 to be corrected (see reference). Figure 2B ).

[0104] After shaving off the portion of the enlarged correction template 321A corresponding to the edge region 301AS to form the correction template 311A ​​(as shown in step S222), at least one copy of the correction template (e.g., correction template copies 311B1 to 311B7) is generated according to the other symmetrical sub-blocks (e.g., sub-blocks 201B to 201H) corresponding to the correction template 311A ​​(as shown in step S23). The correction template 311A ​​and these correction template copies 311B1 to 311B7 are then joined together to form a […]. Figure 3B The illustrated combined correction pattern 311 replaces the original pattern to be corrected 201 (as shown in step S24).

[0105] The subsequent steps are as follows: Further optical approximation corrections 312 are performed on the edge pattern of the peripheral region 303 (e.g., sub-blocks 303A-303H) to complete the correction of the semiconductor mask pattern 200 (e.g., ...). Figure 3C (As illustrated). Similarly, it can save 7 / 8 of the optical approximation correction 302 process and correction time, greatly reducing the cost of photomask processing, chip printing, measurement and equipment calibration consumed in the overall optical approximation correction of semiconductor mask pattern 200, and saving correction time, thereby improving the efficiency of photolithography process.

[0106] Please refer to Figures 4A to 4C , Figures 4A to 4C This is a further embodiment of the present specification, illustrating the use of... Figure 2A The method described herein is illustrated in the diagram showing the changes in the semiconductor mask pattern 400 during the mask pattern correction process. Figures 4A to 4C The correction method shown is roughly the same as Figures 2B to 2C The steps of the correction method are the same, the main difference is that the peripheral area 403 of the semiconductor mask pattern 400 has no edge pattern, and the formation method of expanding the correction template 421A, the range of optical approximation correction 402, and the method of shaving the edge area 401AS of the semiconductor mask pattern 400 are also different.

[0107] In this embodiment, as Figure 4A As illustrated, the semiconductor mask pattern 400 can be divided (as described in step S21) into eight symmetrical and overlapping sub-blocks (e.g., eight sub-blocks 401A to 401H) at a central angle θ around the center of symmetry P. Since step S21 has been detailed in... Figure 2B Therefore, it will not be elaborated further here. The correction method described in this embodiment is described starting from step S221.

[0108] like Figure 4B As illustrated, the formation of the expanded correction template 421A is to extend the range of the optical approximation correction 402 outward from the edge of the sub-block 401A by a distance H”, so that the range of the optical approximation correction 402 includes not only the sub-block 401A, but also the edge region 401AS composed of a portion of the sub-blocks 403B to 403H and a portion of the edge peripheral region 403 without any peripheral pattern.

[0109] Next, the sub-block 401A and edge region 401AS of the pattern 401 to be corrected are optically approximated and corrected 402 to form an enlarged correction template 421A. In this way, during the optical approximation correction 402 process, the peripheral region 403, which has no surrounding pattern, can further consider and reduce its impact on the sub-block pattern 401A1 of the sub-block 401A (see reference). Figure 4A The optical proximity effect produced by the correction template pattern 411A1 of the correction template 421A is expected to be as close as possible to the sub-block pattern 401A1 of the sub-block 401A in the pattern to be corrected 401.

[0110] After shaving off a portion of the edge region 403 corresponding to the enlarged correction template 421A to form the correction template 411A (as shown in step S222), at least one copy of the correction template (e.g., correction template copies 411B1 to 411B7) is generated according to the other symmetrical sub-blocks (e.g., sub-blocks 401B to 401H) corresponding to the correction template 411A (as shown in step S23). The correction template 411A and these correction template copies 411B1 to 411B7 are then joined together to form a […]. Figure 4C The illustrated combined correction pattern 411 replaces the original pattern to be corrected 401 (as shown in step S24). Since the peripheral area 403 no longer has an edge pattern, the optical approximation correction 402 can be completed.

[0111] In some embodiments, if other patterns that may produce an optical proximity effect on the combined correction pattern 411 are configured on the outer side of the peripheral area 403 in subsequent manufacturing processes, then as described in S25, another or more other optical approximation corrections (not shown) can be performed separately on the other patterns on the outer side of the peripheral area 403.

[0112] Please refer to Figure 5 , Figure 5 It is based on Figures 2A to 2D A schematic cross-sectional view of the semiconductor structure 50 fabricated by the semiconductor mask pattern 200 correction method described above. In this embodiment, the semiconductor structure 50 includes a light-transmitting substrate 51 and a planar optical matrix 500 formed by transferring the optically corrected semiconductor mask pattern 200 onto the surface 51a of the light-transmitting substrate, creating a plurality of columnar protrusions 511, a plurality of recesses 512, or a combination of both. Figures 2A to 2D The application scope of the semiconductor mask pattern 200 correction method is not limited to this; the semiconductor mask pattern 200 correction method is applicable to any semiconductor structure fabricated using photomask lithography.

[0113] According to the above embodiments, this specification provides a method for correcting a semiconductor mask pattern. The method involves providing or identifying a pattern to be corrected that can be divided into multiple symmetrical and overlapping sub-blocks within the semiconductor mask pattern. Only one sub-block undergoes optical approximation correction to obtain a correction template. Then, based on the number of symmetrical sub-blocks, the correction template is copied to generate at least one copy. These copies are then stitched together to form a combined correction pattern, directly replacing the original pattern to be corrected. Since only one sub-block of the pattern to be corrected needs optical approximation correction, the correction result of the entire pattern can be obtained by copying the correction template. This significantly reduces the number of steps and the scope of optical approximation correction, lowers the costs of photomask processing, chip printing, measurement, and equipment calibration required for pattern correction, saves correction time, and improves the efficiency of the photolithography process.

[0114] Although the present invention has been disclosed in conjunction with the above preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for correcting a semiconductor mask pattern, comprising: The pattern to be corrected in the semiconductor mask pattern is divided into multiple symmetrical sub-blocks that can be symmetrical to each other and overlapped, wherein each of the multiple symmetrical sub-blocks includes at least two different pattern units; An optical approximation correction is performed on one of the multiple symmetrical sub-blocks to obtain a correction template; Based on the modified template, at least one copy of the modified template is generated for each of the other multiple symmetric sub-blocks; as well as The correction template and at least one copy of the correction template are combined to form a combined correction pattern that replaces the pattern to be corrected. The step of performing the optical approximation correction to obtain the corrected template includes: The scope of this optical approximation correction is extended to the edge region of one of the plurality of symmetrical sub-blocks; This optical approximation correction is performed to form an enlarged correction template; as well as The portion of the enlarged correction template corresponding to the edge region is shaved off to form the correction template.

2. The method for correcting a semiconductor mask pattern as described in claim 1, wherein the pattern to be corrected is an axisymmetric pattern or a rotationally symmetric pattern.

3. The method for correcting a semiconductor mask pattern as claimed in claim 1, wherein after the step of forming the at least one copy of the corrected template, it further includes performing another optical approximation correction on a portion of one of a plurality of symmetrical sub-blocks that is far from the pattern to be corrected.

4. The method for correcting a semiconductor mask pattern as claimed in claim 3, wherein one of the plurality of symmetrical sub-blocks, the portion of which is far from the pattern to be corrected, has another portion that is symmetrical and can overlap.

5. The method for correcting a semiconductor mask pattern as claimed in claim 3, wherein one of the plurality of symmetrical sub-blocks, the portion of which is far from the pattern to be corrected, does not have another symmetrical and overlapping portion.

6. The method for correcting a semiconductor mask pattern as claimed in claim 1 further includes performing another optical approximation correction on at least a portion of the semiconductor mask pattern other than the pattern to be corrected.

7. The method for correcting a semiconductor mask pattern as claimed in claim 1, wherein the pattern to be corrected has a center of symmetry, and the step of dividing the pattern to be corrected into a plurality of symmetrical sub-blocks that are symmetrical to each other and can overlap includes dividing the pattern to be corrected at the central angle of the center of symmetry to form the plurality of symmetrical sub-blocks.

8. A semiconductor structure fabricated using a method for modifying the semiconductor mask pattern as described in any one of claims 1 to 7.

9. The semiconductor structure of claim 8, comprising: Translucent substrate; A planar optical matrix pattern having multiple axisymmetric columnar protrusions, multiple recesses, or a combination of both, is disposed on the surface of the light-transmitting substrate.

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