A method for improving the radiation resistance performance of an n-type Flash memory device

Abstract

The present invention relates to a method for improving the radiation resistance of an n-type Flash memory device, which includes the following steps: First, provide a P-type epitaxial layer, and sequentially form a silicon dioxide layer and a silicon nitride layer on the P-type epitaxial layer; then etch to form STI isolation trenches, and inject nitrogen and oxygen into the bottom and sidewalls of the STI isolation trenches; then perform high-temperature annealing, and regrow a layer of silicon nitride using LPCVD; fill the HDP medium and anneal it, and planarize the HDP medium; finally, perform Flash high-voltage well injection, tunnel oxide growth, floating gate polycrystalline deposition, ONO deposition, control gate polycrystalline deposition, polycrystalline etching, LDD injection, spacer deposition and etching, source / drain injection, and the subsequent processes follow the general 0.13μm Flash process. In the method provided by the present invention, the NON structure formed on the STI sidewall is stable and not affected by the thermal process of subsequent process manufacturing; it has strong compatibility with the general Flash process.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a method for improving the radiation resistance performance of an n-type Flash memory device. Background Art

[0002] Flash has the characteristics of being easy to integrate with CMOS technology, non-volatility, reprogrammability, fast read speed, low power consumption, high integration degree, etc., and is often integrated into integrated circuits such as SOC and DSP for data storage. With the development of aerospace technology, the requirement for the radiation resistance of Flash storage is also getting higher and higher.

[0003] Except for the influence of the peripheral CMOS circuit on the radiation resistance performance of the Flash memory, the radiation resistance performance of the Flash memory device itself is crucial. When the Flash is in a radiation environment, electron-hole pairs will be generated in the SiO2 layer wrapping the floating gate in the Flash memory device. The electrons generated by the electron-hole pairs move rapidly towards the gate direction under the action of an external electric field. The holes are trapped by the SiO2 traps and will cause the channel interface to invert, which often leads to an increase in the static current of the integrated circuit and even causes the integrated circuit function to fail. Due to the application of the STI (Shallow Trench Isolation) technology in large-scale integrated circuits, the field edge leakage caused by the SiO2 layer filled in the STI in a radiation environment has become an important factor affecting the radiation resistance performance of the Flash.

[0004] The early radiation hardening methods for Flash memory circuits often increased the shielding shell, which would lead to a relatively large volume and weight of the integrated circuit. The subsequent method of reinforcement through layout design would directly increase the area of the Flash memory device, greatly reducing the integration degree of the Flash. By performing sidewall implantation of P-type impurities on the STI to increase the inversion threshold and reduce the influence of radiation, this implantation technology would cause the Flash breakdown voltage to decrease, affecting the high-voltage programming effect; on the other hand, the implanted P-type impurities would be affected by the thermal process during the subsequent process manufacturing, and the implanted impurity concentration on the STI sidewall surface would decrease, thereby reducing the radiation resistance effect. Summary of the Invention

[0005] To solve the above technical problems, a method for improving the radiation resistance performance of an n-type Flash memory device of the present invention includes the following steps:

[0006] Step S1: Provide a P-type epitaxial wafer, grow a sacrificial oxide layer on the epitaxial wafer, then remove it by wet etching, and then form a silicon dioxide layer and a silicon nitride layer in sequence;

[0007] Step S2: Use an active region mask to etch and form STI isolation trenches;

[0008] Step S3: Inject nitrogen and oxygen into the bottom and sidewalls of the STI isolation trench in sequence, and then perform high-temperature annealing;

[0009] Step S4: Grow a layer of silicon nitride using LPCVD;

[0010] Step S5: Fill with HDP medium and anneal, and then planarize the HDP medium;

[0011] Step S6: Perform Flash high-voltage well injection, tunnel oxide growth, floating gate polycrystalline deposition, ONO deposition, control gate polycrystalline deposition, polycrystalline etching, LDD injection, spacer deposition and etching, source / drain injection, and subsequent processes follow the general 0.13μm Flash process.

[0012] In an embodiment of the present invention, the epitaxial layer thickness of the P-type epitaxial wafer in step S1 is 4.0 - 6.0μm.

[0013] In an embodiment of the present invention, in step S3, nitrogen is first injected into the bottom and sidewalls of the STI isolation trench, and then oxygen is injected; wherein, the energy of nitrogen injection is 3 - 5KeV, and the injection dose is 1.1 - 1.3E18cm -2 ; the energy of oxygen injection is 2 - 4keV, and the injection dose is 1.4 - 1.6E18cm -2 ;

[0014] In the high-temperature annealing, the annealing temperature is 1150 - 1200°C, and the annealing time is 0.5 - 1 hour;

[0015] After high-temperature annealing, a silicon dioxide layer and a silicon nitride layer are formed from the outside to the inside on the sidewalls and bottom of the STI isolation trench, where the thickness of the silicon dioxide is The thickness of the silicon nitride is

[0016] In an embodiment of the present invention, the thickness of the silicon nitride in step S4 is And it forms a NON structure with the silicon dioxide layer and silicon nitride layer formed by injecting nitrogen and oxygen into the bottom and sidewalls of the STI isolation trench.

[0017] The above technical solution of the present invention has the following advantages compared with the prior art: (1) By injecting nitrogen and oxygen in sequence and then performing high-temperature annealing in the STI region, a silicon dioxide layer and a silicon nitride layer can be formed from the outside (trench) to the inside (Si) on the STI sidewalls, avoiding the stress problem caused by directly depositing silicon nitride on the STI sidewalls and the Si interface;

[0018] (2) The nitrogen and oxygen injected into the STI sidewalls and the silicon nitride deposited by LPCVD form a NON structure, which can reduce the influence caused by the accumulation of positive charges in the oxide layer due to radiation;

[0019] (3) The NON structure formed on the STI sidewall is stable and not affected by the thermal processes in subsequent manufacturing processes.

[0020] (4) It has strong compatibility with general Flash processes, improving the radiation resistance of Flash memory devices without reducing the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 It is a schematic cross-sectional view of a Flash memory device, where a is a cross-sectional view along the Channel direction and b is a cross-sectional view along the polycrystalline direction;

[0023] Figure 2 It is a schematic diagram of STI sidewall leakage after radiation;

[0024] Figure 3 It is a schematic flow diagram of the method for improving the radiation resistance of n-type Flash memory devices provided by the present invention;

[0025] Figure 4 It is a schematic diagram of growing a sacrificial oxide layer on a P-type epitaxial wafer;

[0026] Figure 5 It is a schematic diagram of sequentially forming a silicon dioxide layer and a silicon nitride layer on a P-type epitaxial wafer substrate;

[0027] Figure 6 It is a schematic diagram of forming an STI isolation trench;

[0028] Figure 7 It is a schematic diagram of nitrogen-oxygen ion implantation on the STI sidewall and bottom;

[0029] Figure 8 It is a schematic diagram of forming silicon nitride and silicon dioxide after high-temperature annealing;

[0030] Figure 9 It is a schematic diagram of growing silicon nitride in the STI trench using LPCVD;

[0031] Figure 10 It is a schematic diagram of performing HDP dielectric filling and annealing treatment;

[0032] Figure 11 It is a schematic diagram of performing HDP dielectric planarization and removing the silicon nitride layer;

[0033] Figure 12 It is a schematic diagram of forming an n-type Flash structure;

[0034] Figure 13It is a schematic cross-sectional view of a SONOS Flash memory device, where c is a cross-sectional view along the Chanel direction and d is a cross-sectional view along the polycrystalline direction;

[0035] Figure 14 It is a schematic diagram of forming a Flash memory device in the second embodiment. Detailed implementation manners

[0036] The following further describes a method for improving the radiation resistance of an n-type Flash memory device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a simplified form and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] Embodiment 1

[0038] This embodiment provides a method for improving the radiation resistance of an n-type Flash memory device, and its process is as Figure 3 shown, including the following steps:

[0039] Step S1: Provide a P-type epitaxial wafer, grow a sacrificial oxide layer on the epitaxial wafer, then remove it by wet etching, and then form a silicon dioxide layer and a silicon nitride layer in sequence;

[0040] Step S2: Use an active area mask to etch and form STI isolation trenches;

[0041] Step S3: Inject nitrogen and oxygen into the bottom and side walls of the STI isolation trenches in sequence, and then perform high-temperature annealing;

[0042] Step S4: Use LPCVD to grow a layer of silicon nitride;

[0043] Step S5: Fill the HDP medium and anneal, and then planarize the HDP medium;

[0044] Step S6: Perform Flash high-voltage well injection, tunnel oxide growth, floating gate polycrystalline deposition, ONO deposition, control gate polycrystalline deposition, polycrystalline etching, LDD injection, sidewall deposition and etching, source / drain injection, and the subsequent processes follow the general 0.13μm Flash process.

[0045] Specifically, as Figure 4 shown, provide a P-type epitaxial wafer, which includes a P-type substrate 1 and an epitaxial layer 2. First, grow a sacrificial oxide layer on the surface of the epitaxial wafer, and then remove it by wet etching, as Figure 5 shown, and then grow a silicon dioxide layer 3 and a silicon nitride layer 4. Further, the thickness of the P-type epitaxial layer 2 is 4.0 - 6.0μm.

[0046] Next, according to the device requirements, use the active region mask to selectively lithograph the active region and etch to form the STI isolation trench 5, as Figure 6 shown. Please refer to Figure 7 , inject nitrogen into the bottom and side walls of the STI isolation trench first. The energy of nitrogen injection is 4 - 6 KeV, and the injection dose is 1.1 - 1.3E18 cm -2 . Then inject oxygen with an energy of 2 - 4 keV and an injection dose of 1.4 - 1.6E18 cm -2 . After nitrogen and oxygen injection, perform high-temperature annealing. The annealing temperature is 1150 - 1200 °C, and the annealing time is 0.5 - 1 hour. As Figure 8 shown, generate silicon dioxide layer and silicon nitride from the outside (trench) to the inside (Si) in the STI isolation trench and at the bottom, where the thickness of the silicon dioxide is about and the thickness of the silicon nitride is about

[0047] Then, as Figure 9 shown, grow a layer of silicon nitride using the LPCVD method, and the thickness of the silicon nitride is about

[0048] Next, as Figure 10 shown, perform HDP dielectric 6 filling and annealing treatment; then perform dielectric planarization and stop on the silicon nitride film 3. Finally, use STI wet etching to completely remove the silicon nitride layer to form the structure as Figure 11 shown.

[0049] Finally, technicians can, based on the knowledge in the field, follow the general 0.13 μm flash process technology, and perform Flash high-voltage well injection, tunnel oxide growth, floating gate polycrystalline deposition, ONO deposition, control gate polycrystalline deposition, polycrystalline etching, LDD injection, sidewall deposition and etching, source-drain injection as needed, and finally form the Flash memory device as Figure 12 shown.

[0050] Embodiment 2

[0051] A method for improving the radiation resistance of an n-type Flash memory device provided by the present invention can also be applied to the Flash process technology of the SONOS structure to form a SONOS FLASH memory device with high radiation resistance. The specific structure and process flow are as Figure 13 shown, and include the following steps:

[0052] Step S1: Provide a P-type epitaxial wafer, grow a sacrificial oxide layer on the epitaxial wafer, then remove it by wet etching, and then form a silicon dioxide layer and a silicon nitride layer in sequence;

[0053] Step S2: Use a mask to selectively etch to form an STI isolation trench;

[0054] Step S3: Inject nitrogen and oxygen into the bottom and side walls of the STI isolation trench in sequence, and then perform high-temperature annealing;

[0055] Step S4: Grow a layer of silicon nitride using LPCVD;

[0056] Step S5: Fill with HDP medium, and then planarize the HDP medium;

[0057] Step S6: Perform Flash high-voltage well injection;

[0058] Step S7: First grow a layer of tunnel oxide layer by thermal oxidation, then grow a layer of silicon nitride using LPCVD, and finally grow a layer of oxide layer by HTO method.

[0059] Step S8: Perform polycrystalline deposition and polycrystalline etching. When etching the polysilicon, the film layer structure is polysilicon and ONO from top to bottom, and stop on the tunnel oxide layer;

[0060] Step S9: Perform LDD injection, sidewall deposition and etching, source / drain injection, and the subsequent process follows the general 0.13μm Flash process.

[0061] Specifically, as Figure 6 shown, a silicon dioxide layer 2 and a silicon nitride layer 3 are grown on the P-type epitaxial wafer 1 in sequence. The thickness of the P-type epitaxial layer is 4.0 - 6.0μm. Using the active area mask, selectively photolithograph the active area and etch to form the STI isolation trench 5. Inject nitrogen into the bottom and side walls of the STI isolation trench first. The energy of nitrogen injection is 4 - 6KeV, and the injection dose is 1.1 - 1.3E18cm -2 . Then inject oxygen with an energy of 2 - 4keV and an injection dose of 1.4 - 1.6E18cm -2 . After injecting nitrogen and oxygen, perform high-temperature annealing. The annealing temperature is 1150 - 1200°C, and the annealing time is 0.5 - 1 hour. As Figure 8 shown, a silicon dioxide layer and a silicon nitride are formed from the outside (trench) to the inside (Si) in the STI isolation trench and at the bottom. The thickness of the silicon dioxide is about The thickness of the silicon nitride is about

[0062] Then, as Figure 9 shown, grow a layer of silicon nitride using LPCVD. The thickness of the silicon nitride is about Next, fill with the HDP medium 6, perform medium planarization after annealing, and stop on the silicon nitride film 3. Finally, completely remove the silicon nitride layer 3 using STI wet etching.

[0063] After the high-voltage well injection, first grow a layer of tunnel oxide layer by thermal oxidation, with a thickness Then, a layer of silicon nitride is grown by LPCVD with a thickness of Finally, a layer of oxide is grown by HTO with a thickness of

[0064] Polycrystalline deposition is carried out with a thickness of Then, polycrystalline etching is performed. During the polycrystalline silicon etching, the film layer structure is polycrystalline silicon, ONO, and finally it stops on the tunnel oxide layer.

[0065] Finally, technicians can, according to the knowledge in the field, follow the general 0.13μm flash memory process, and perform LDD implantation, spacer deposition and etching, source-drain implantation as needed, and finally form a Flash memory device as Figure 14 shown.

[0066] In summary, through the above process, a NON structure is formed on the sidewalls and bottom of the STI trench. In a radiation environment, since the silicon nitride layer has electron traps, it can capture the electrons in the electron-hole pairs generated by radiation, and self-recombination occurs at the junction of silicon nitride and silicon dioxide, which can significantly reduce the accumulation effect of holes in the oxide layer, effectively reducing the leakage current in the STI field region. Therefore, the above method greatly reduces the threshold drift probability of n-type Flash memory devices under total dose irradiation.

[0067] Obviously, the above embodiments are merely examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for improving the radiation resistance performance of an n-type Flash memory device, characterized in that, It includes the following steps: Step S1: Provide a P-type epitaxial wafer, grow a sacrificial oxide layer on the epitaxial wafer, then remove it by wet etching, and then form a silicon dioxide layer and a silicon nitride layer in sequence; Step S2: Use an active area mask to etch and form STI isolation trenches; Step S3: Inject nitrogen and oxygen into the bottom and sidewalls of the STI isolation trenches in sequence, and then perform high-temperature annealing. After high-temperature annealing, a silicon dioxide layer and a silicon nitride layer are formed from the outside to the inside on the sidewalls and bottom of the STI isolation trenches; Step S4: Use LPCVD to grow a layer of silicon nitride; Step S5: Fill with HDP dielectric and anneal, and then planarize the HDP dielectric; Step S6: Perform Flash high-voltage well injection, tunnel oxide growth, floating gate polycrystalline deposition, ONO deposition, control gate polycrystalline deposition, polycrystalline etching, LDD injection, sidewall deposition and etching, source / drain injection, and subsequent processes follow the general 0.13μm Flash process.

2. The method for improving the radiation resistance performance of an n-type Flash memory device according to claim 1, characterized in that: In step S1, the thickness of the epitaxial layer of the P-type epitaxial wafer is 4.0 - 6.0μm.

3. The method for improving the radiation resistance of an n-type Flash memory device according to claim 1, characterized in that: In step S3, nitrogen is first implanted into the bottom and sidewalls of the STI isolation trench, and then oxygen is implanted. Among them, the energy of nitrogen implantation is 3-5 keV, and the implantation dose is 1.1-1.3E18 cm -2 ; the energy of oxygen implantation is 2-4 keV, and the implantation dose is 1.4-1.6E18 cm -2 ; In the high-temperature annealing, the annealing temperature is 1150 - 1200°C, and the annealing time is 0.5 - 1 hour; Among them, the thickness of the silicon dioxide is 100 - 200 Å, and the thickness of the silicon nitride is 150 - 250 Å.

4. The method for improving the radiation resistance performance of an n-type Flash memory device according to claim 1, characterized in that: In step S4, the thickness of the silicon nitride is 250 - 350 Å; and it forms a NON structure with the silicon dioxide layer and the silicon nitride layer formed by injecting nitrogen and oxygen into the bottom and sidewalls of the STI isolation trenches.

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