Display substrate, manufacturing method thereof, and display device

Abstract

The embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device. The display substrate includes a first thin film transistor, and the first thin film transistor includes a first sub-gate, a second sub-gate, and a first active layer. The display substrate includes: a first sub-gate, located on one side of a base substrate; a first insulating layer, located on the side of the first sub-gate away from the base substrate; a first active layer, located on the side of the first insulating layer away from the base substrate, and the material of the first active layer includes an oxide semiconductor; a second insulating layer, located on the side of the first active layer away from the base substrate; a second sub-gate, located on the side of the second insulating layer away from the base substrate, and the orthographic projection of the second sub-gate on the base substrate includes the orthographic projection of the first sub-gate on the base substrate. The technical solution disclosed in the present disclosure can improve the stability of the characteristics of the first thin film transistor device, which is conducive to improving the resolution and aperture ratio of the product.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Low-temperature polysilicon (LTPS) and oxide semiconductors have attracted much attention in the field of display products. LTPS has the advantages of high mobility and fast charging, while oxide has the advantages of low leakage current and low power consumption. Display products that combine LTPS and oxide thin-film transistors, namely LTPO display products, greatly improve the user experience. However, there are significant differences in the preparation processes of LTPS and oxide, resulting in problems with process compatibility and difficulty in ensuring process stability. In addition, oxide thin-film transistors are large in size and occupy a large area in the pixel circuit, which is not conducive to improving the resolution (PPI) and aperture ratio of display products. Summary of the Invention

[0003] The embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display substrate, including a first thin film transistor, the first thin film transistor including a first sub-gate, a second sub-gate, and a first active layer, the display substrate including:

[0005] A first sub-gate is located on one side of the substrate;

[0006] a first insulating layer, located on a side of the first sub-gate facing away from the substrate;

[0007] a first active layer, located on a side of the first insulating layer facing away from the substrate, wherein the material of the first active layer includes an oxide semiconductor;

[0008] a second insulating layer, located on a side of the first active layer facing away from the substrate;

[0009] The second sub-gate is located on a side of the second insulating layer away from the base substrate, and the orthographic projection of the second sub-gate on the base substrate includes the orthographic projection of the first sub-gate on the base substrate.

[0010] In some embodiments, the channel corresponding to the second sub-gate on the first active layer includes an effective channel located in the middle and ineffective channels located on both sides of the effective channel. The size of the effective channel in the first direction is larger than the size of the first sub-gate in the first direction. The first direction is the arrangement direction of the effective channel and the ineffective channel.

[0011] In some embodiments, an orthographic projection of the second insulating layer on the base substrate includes an orthographic projection of the first active layer on the base substrate.

[0012] In some embodiments, an orthographic projection of the second insulating layer on the base substrate coincides with an orthographic projection of the second sub-gate on the base substrate.

[0013] In some embodiments, the display substrate further includes a third insulating layer, the third insulating layer is located on a side of the second sub-gate facing away from the base substrate, and the material of the third insulating layer includes silicon nitride.

[0014] In some embodiments, the display substrate further includes a second thin film transistor, the second thin film transistor includes a second active layer, and the material of the second active layer includes polycrystalline silicon semiconductor.

[0015] In some embodiments, the second thin film transistor also includes a second gate electrode, the second active layer is located on the side of the base substrate facing the first active layer, the display substrate also includes a first gate insulating layer and a second gate insulating layer, the first gate insulating layer is located on the side of the second active layer facing away from the base substrate, the second gate electrode is located on the side of the first gate insulating layer facing away from the base substrate, the second gate insulating layer is located on the side of the second gate electrode facing away from the base substrate, and the first sub-gate is located on the side of the second gate insulating layer facing away from the base substrate.

[0016] In some embodiments, the first sub-gate has a size in the first direction less than or equal to 3.5 μm, and the second sub-gate has a size in the first direction of 4.5 μm to 5.5 μm. The first direction is the arrangement direction of the conductive region and the channel region of the first active layer.

[0017] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for preparing a display substrate, the display substrate including a first thin film transistor, the first thin film transistor including a first active layer, a first sub-gate, and a second sub-gate, the method comprising:

[0018] forming a first sub-gate on one side of the substrate;

[0019] forming a first insulating layer on a side of the first sub-gate facing away from the substrate;

[0020] forming a first active layer on a side of the first insulating layer away from the substrate, wherein the material of the first active layer includes an oxide semiconductor;

[0021] forming a second insulating layer and a second sub-gate on a side of the first active layer away from the base substrate, wherein the second insulating layer is close to the first active layer, and an orthographic projection of the second sub-gate on the base substrate includes an orthographic projection of the first sub-gate on the base substrate;

[0022] The first active layer is conductively conductive to form a conductive region, wherein the orthographic projection of the conductive region on the base substrate is located on both sides of the orthographic projection of the second sub-gate on the base substrate.

[0023] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the display substrate in the embodiments of the present disclosure.

[0024] The technical solution of the embodiment of the present disclosure can improve the stability of the device characteristics of the first thin film transistor, which is conducive to realizing the miniaturization of the first thin film transistor and improving the resolution and aperture ratio of the product.

[0025] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0027] Figure 1 is a schematic cross-sectional view of a display substrate;

[0028] Figure 2 for Figure 1 Another schematic diagram of the display substrate is shown;

[0029] Figure 3 is a schematic cross-sectional view showing a substrate in one embodiment of the present disclosure;

[0030] Figure 4 is a schematic cross-sectional view showing a substrate in another embodiment of the present disclosure;

[0031] Figure 5 is a schematic cross-sectional view showing a substrate in another embodiment of the present disclosure;

[0032] Figure 6 is a schematic cross-sectional view showing a substrate in another embodiment of the present disclosure;

[0033] Figure 7 This is a schematic cross-sectional view showing a first active layer in a substrate after being converted into a conductor according to an embodiment of the present disclosure;

[0034] Figure 8 This is a cross-sectional schematic diagram showing another embodiment of the present disclosure after the first active layer in the substrate is conductively converted.

[0035] Description of reference numerals:

[0036] 10. Base substrate; 11. Substrate; 12. Base; 13. Barrier layer; 14. First buffer layer; 211. Second active layer; 221. Second gate electrode; 231. First sub-gate; 241. First active layer; 251. Second sub-gate; 261. First source electrode; 262. First drain electrode; 263. Second source electrode; 264. Second drain electrode; 31. First gate insulating layer; 32. Second gate insulating layer; 33. First insulating layer; 331. Interlayer insulating layer; 332. Second buffer layer; 34. Second insulating layer; 35. Third insulating layer. DETAILED DESCRIPTION

[0037] In the following, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined in any manner without conflict. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0038] Figure 1 is a cross-sectional schematic diagram of a display substrate. Figure 2 for Figure 1 Another schematic diagram of the display substrate is shown. Figure 2 The channel length of the first thin film transistor is shown in FIG. Figure 2 The source and drain electrode layers are not shown. Figure 1 As shown, the display substrate includes a first thin film transistor and a second thin film transistor. The first thin film transistor is a dual-gate thin film transistor, comprising a first active layer 241, a first sub-gate 231, a second sub-gate 251, a first source electrode 261, and a first drain electrode 262. The first active layer 241 is made of an oxide semiconductor, and therefore, the first thin film transistor can also be called a dual-gate oxide thin film transistor. The second thin film transistor includes a second active layer 211, a second gate electrode 222, a second source electrode 263, and a second drain electrode 264. The second active layer 211 is a low-temperature polycrystalline silicon semiconductor, and therefore, the second thin film transistor can also be called an LTPS thin film transistor.

[0039] like Figure 1As shown, the first thin-film transistor includes a first sub-gate 231 and a second sub-gate 251. The first sub-gate 231 is located below the first active layer 241 and can also be called a bottom gate. The second sub-gate 251 is located above the first active layer 241 and can also be called a top gate. The orthographic projection of the first sub-gate 231 on the substrate includes the orthographic projection of the second sub-gate 251 on the substrate. In other words, the first sub-gate 231 completely encloses the second sub-gate 251.

[0040] like Figure 1 and Figure 2 As shown, the second insulating layer 34 (also called the third gate insulating layer) covers the first active layer 241. A plasma implantation (Doping) process is required to conduct the conductive area of ​​the first active layer 241 to increase the on-state current I on .

[0041] exist Figure 1 In the embodiment, the third insulating layer 35 (also called the second interlayer insulating layer) can be a silicon nitride film, so as to avoid the problem of cracks in the third insulating layer 35 caused by buffered oxide layer etching (BOE Etch).

[0042] During the preparation of the display substrate, the ions in the plasma implantation process and the H in the third insulating layer 35 will diffuse into the channel of the first active layer 241, affecting the effective channel length L of the oxide thin film transistor. eff .

[0043] like Figure 2 As shown, the orthographic projection area of ​​the second sub-gate 251 on the first active layer 241 is the channel corresponding to the second sub-gate 251, and the orthographic projection area of ​​the first sub-gate 231 on the first active layer 241 is the channel corresponding to the first sub-gate 231. The dimension L1 of the second sub-gate 251 in the first direction X is the channel length corresponding to the second sub-gate 251, and the length L2 of the first sub-gate 231 in the first direction X is the channel length corresponding to the first sub-gate 231, and L2>L1. The first active layer 241 includes a channel region and conductive regions located at both ends of the channel region. The first direction X can be the arrangement direction of the channel region and the conductive region of the first active layer 241. Figure 2 In the embodiment, the first direction X is a horizontal direction, or the first direction X may be an arrangement direction of the source electrode and the drain electrode of the first thin film transistor. For example, the source electrode and the drain electrode of the first thin film transistor are respectively a first source electrode 261 and a first drain electrode 262, and the arrangement direction of the first source electrode 261 and the first drain electrode 262 is a horizontal direction. Therefore, in Figure 2 The first direction X is the horizontal direction.

[0044] The ions in the plasma implantation process and the H (hydrogen) in the third insulating layer 35 will diffuse to both ends of the channel region of the first active layer 241, namely the ΔL region (the ΔL region can be called the ineffective channel region), which makes the effective channel length L corresponding to the second sub-gate 251 of the oxide thin film transistor eff The effective channel length L corresponding to the first sub-gate 231 is reduced from L1 to L1-2ΔL. eff Also L1-2ΔL.

[0045] For oxide thin film transistors, the smaller the channel length of the thin film transistor, the worse the stability of the thin film transistor device characteristics. Affected by the ineffective channel region, the effective channel length L of the first thin film transistor is eff The decrease reduces the stability of the first thin film transistor device characteristics.

[0046] In oxide thin film transistors, the smaller the channel length, the better it is for improving the resolution and aperture ratio of LTPO products. The existence of the ineffective channel region, i.e., the ΔL region, limits the reduction of the channel length. For example, the effective channel length L of an oxide thin film transistor is eff The minimum value is Lx. If the effective channel length is less than Lx, the stability of the oxide thin-film transistor device characteristics cannot be guaranteed. In the absence of the ineffective channel region ΔL, the effective channel length is the same as the channel length, and the channel length can be reduced to Lx to improve the resolution and pixel aperture ratio. Due to the influence of the ineffective channel region, namely the ΔL region, the channel length of the oxide thin-film transistor needs to be increased from Lx to Lx+2ΔL. Lx+2ΔL is greater than Lx. Therefore, the ΔL region affects the reduction of the channel size of the oxide thin-film transistor, limiting the improvement of the resolution and pixel aperture ratio of LTPO products.

[0047] Figure 3 FIG. 1 is a schematic cross-sectional view of a display substrate in one embodiment of the present disclosure. Figure 3As shown, the display substrate includes a first thin film transistor. The first thin film transistor includes a first sub-gate 231, a first active layer 241, and a second sub-gate 251. The first thin film transistor can also be called a dual-gate oxide thin film transistor. The display substrate also includes a first insulating layer 33 and a second insulating layer 34. The first sub-gate 231 is located on one side of the base substrate 10. The first insulating layer 33 is located on the side of the first sub-gate 231 facing away from the base substrate 10. The first active layer 241 is located on the side of the first insulating layer 33 facing away from the base substrate 10. The material of the first active layer 241 includes an oxide semiconductor. Exemplarily, the material of the first active layer 241 is an oxide semiconductor, such as indium gallium zinc oxide (IGZO). The second insulating layer 34 is located on the side of the first active layer 241 facing away from the base substrate 10. The second sub-gate 251 is located on the side of the second insulating layer 34 facing away from the base substrate 10. The orthographic projection of the second sub-gate 251 on the base substrate 10 includes the orthographic projection of the first sub-gate 231 on the base substrate 10.

[0048] Exemplarily, the orthographic projection of the second sub-gate 251 on the base substrate 10 includes the orthographic projection of the first sub-gate 231 on the base substrate 10, so that the size of the second sub-gate 251 in the first direction X (i.e., the channel length L3 corresponding to the second sub-gate 251) is greater than the size of the first sub-gate 231 in the first direction (i.e., the channel length L4 corresponding to the first sub-gate 231).

[0049] For example, Figure 3 As shown, the channel length L3 corresponding to the second sub-gate 251 is greater than the channel length L4 corresponding to the first sub-gate 231 , so that the second sub-gate 251 completely covers the first sub-gate 231 .

[0050] For a dual-gate oxide thin-film transistor, the stability of its device characteristics is primarily determined by the gate with the smaller effective channel length. For example, if the effective channel length corresponding to the second sub-gate 251 is smaller than the effective channel length corresponding to the first sub-gate 231, the stability of the dual-gate oxide thin-film transistor's device characteristics is determined by the channel length corresponding to the second sub-gate 251. If the effective channel length corresponding to the first sub-gate 231 is smaller than the effective channel length corresponding to the second sub-gate 251, the stability of the dual-gate oxide thin-film transistor's device characteristics is determined by the channel length corresponding to the first sub-gate 231.

[0051] In the display substrate of the disclosed embodiment, the channel length L4 corresponding to the first sub-gate 231 is shorter than the channel length L3 corresponding to the second sub-gate 251. Therefore, the stability of the device characteristics of the first thin-film transistor is determined by the channel length corresponding to the first sub-gate 231. Due to the blocking effect of the second sub-gate 251, the second insulating layer 34, and the first active layer 241, ions during the plasma implantation process and hydrogen in the insulating layer above the second sub-gate 251 are difficult to diffuse into the channel corresponding to the first sub-gate 231. Therefore, the first sub-gate 231 does not have an inactive channel, and the effective channel length corresponding to the first sub-gate 231 is equal to the length corresponding to the first sub-gate 231.

[0052] In related technologies, such as Figure 2 As shown, the stability of the first thin-film transistor device characteristics is determined by the effective channel length corresponding to the second sub-gate 251, and the channel corresponding to the second sub-gate 251 has an ineffective channel. In the display substrate of the embodiment of the present disclosure, the stability of the first thin-film transistor device characteristics is determined by the effective channel length corresponding to the first sub-gate 231, and the channel corresponding to the first sub-gate 231 does not have an ineffective channel. Under the condition that the gate length that plays a decisive role in the stability of the device characteristics is the same, since the channel corresponding to the first sub-gate 231 of the display substrate of the embodiment of the present disclosure does not have an ineffective channel, the effective channel length corresponding to the first sub-gate 231 is larger, thereby improving the stability of the dual-gate Oxide thin-film transistor device characteristics. Under the condition that the stability of the dual-gate Oxide thin-film transistor device characteristics is the same, that is, under the condition that the gate length that plays a decisive role in the stability of the device characteristics is the same, Figure 3 L4 and Figure 2 When L1-2ΔL is the same, compared with Figure 2 As shown in the display substrate, the display substrate of the embodiment of the present disclosure can further reduce the size of the first sub-gate 231 and the second sub-gate 251 in the first direction, which is conducive to realizing the small size of the oxide thin film transistor and improving the resolution and aperture ratio of the display substrate.

[0053] In one embodiment, the channel corresponding to the second sub-gate 251 includes an effective channel located in the middle and ineffective channels located on both sides of the effective channel. The first direction can be the arrangement direction of the effective channel and the ineffective channel. Figure 3 The first direction is the horizontal direction. The channel length corresponding to the second sub-gate 251 is L3, wherein the effective channel length is L eff1, the ineffective channel length is ΔL. The channel length corresponding to the first sub-gate 231 is L4. Due to the blocking effect of the second sub-gate 251, the second insulating layer 34 and the first active layer 241, the ions in the plasma implantation process and the H in the insulating layer above the second sub-gate 251 are difficult to diffuse into the first sub-gate 231. Therefore, there is no ineffective channel in the channel corresponding to the first sub-gate 231. Therefore, the effective channel length corresponding to the first sub-gate 231 is the same as the channel length. The effective channel length L corresponding to the first sub-gate 231 eff2 =L4.

[0054] When the effective channel length corresponding to the top gate is smaller than the effective channel length corresponding to the bottom gate, it is the top gate that affects the stability of the thin film transistor device characteristics, that is, the stability of the dual-gate oxide thin film transistor device characteristics is mainly determined by the top gate. When the effective channel length corresponding to the top gate is larger than the effective channel length corresponding to the bottom gate, it is the bottom gate that affects the stability of the thin film transistor device characteristics, that is, the stability of the dual-gate oxide thin film transistor device characteristics is mainly determined by the bottom gate. Figure 2 As shown, the effective channel length L corresponding to the top gate (ie, the second sub-gate 251) and the bottom gate (the first sub-gate 231) is eff are both L1-2ΔL, so, Figure 2 The stability of the dual-gate thin-film transistor device characteristics is determined by both the top gate and the bottom gate.

[0055] For example, you can set Figure 3 The channel length corresponding to the second sub-gate 251 is Figure 2 The channel lengths corresponding to the first sub-gate 231 are the same, that is, L3 = L2; Figure 3 The channel length corresponding to the first sub-gate 231 is Figure 2 The channel lengths corresponding to the second sub-gate 251 are the same, ie, L4 = L1.

[0056] Figure 3 In the embodiment, the channel length L3 corresponding to the second sub-gate 251 is greater than the channel length L4 corresponding to the first sub-gate 231. The ions in the plasma implantation process and the H in the insulating layer above the second sub-gate 251 will diffuse to both sides of the channel of the first active layer 241, forming an ineffective channel ΔL. Therefore, the effective channel length L corresponding to the second sub-gate 251 is eff1 =L3-2ΔL. Figure 3 The effective channel length corresponding to the first sub-gate 231 is L eff2 =L4. L eff1 >L eff2 ,therefore, Figure 3 The stability of the device characteristics of the first thin film transistor is determined by the channel length L4 corresponding to the first sub-gate 231 . Figure 2The stability of the first thin film transistor device characteristics is determined by the effective channel length L corresponding to the second sub-gate 251. eff .

[0057] exist Figure 3 L4 and Figure 2 When L1 is the same, Figure 3 The effective channel length L corresponding to the first sub-gate 231 eff2 (Same as L4) greater than Figure 2 The effective channel length L corresponding to the second sub-gate 251 eff (L eff = L1-2ΔL). For dual-gate oxide thin film transistors, the longer the effective channel length is, the better the stability of the device characteristics is. Therefore, Figure 3 The stability of the first thin film transistor device characteristics in the display substrate is better than Figure 2 The figure shows the stability of the characteristics of the first thin film transistor device in the display substrate. The technical solution of the embodiment of the present disclosure improves the stability of the characteristics of the first thin film transistor device.

[0058] For example, in Figure 3 Medium L eff2 and Figure 2 Medium L eff Same Figure 3 Device characteristics of dual-gate oxide thin film transistors and Figure 2 Under the same stability of the characteristics of the dual-gate oxide thin film transistor device, that is, Figure 3 L4 and Figure 2 When L1-2ΔL is the same, compared with Figure 2 In the display substrate shown in the embodiment of the present disclosure, the channel length L4 corresponding to the first sub-gate 231 and the channel length L3 corresponding to the second sub-gate 251 can be smaller, thereby facilitating the miniaturization of oxide thin-film transistors and improving the resolution and aperture ratio of the display substrate. It is understood that the channel length corresponding to the first sub-gate 231 is the same as the dimension of the first sub-gate 231 in the first direction X, and the channel length corresponding to the second sub-gate 251 is the same as the dimension of the second sub-gate 251 in the first direction X.

[0059] Figure 4 FIG. 1 is a schematic cross-sectional view of a substrate in another embodiment of the present disclosure. Figure 4 As shown, the channel length corresponding to the second sub-gate 251 is L5, and the channel length corresponding to the first sub-gate 231 is L6. The channel corresponding to the second sub-gate 251 includes an effective channel and ineffective channels located on both sides of the effective channel. The effective channel length of the second sub-gate 251 is L eff3 , the ineffective channel length of the second sub-gate 251 is ΔL, then, Leff3 = L5 - 2ΔL. The effective channel length L of the first sub-gate 231 eff4 = L6.

[0060] In one embodiment, L5 = L2 - 2ΔL and L6 = L1 - 2ΔL.

[0061] For L6 = L1 - 2ΔL: Figure 4 The stability of the characteristics of the double-gate Oxide thin film transistor device is determined by the effective channel length L6 of the first sub-gate 231. Figure 2 The stability of the characteristics of the double-gate Oxide thin film transistor device is determined by the effective channel length L1 - 2ΔL of the second sub-gate 251. Since L6 = L1 - 2ΔL, therefore, Figure 4 and Figure 2 the stability of the characteristics of the double-gate Oxide thin film transistor devices in

[0062] For L5 = L2 - 2ΔL: Figure 4 The channel length corresponding to the second sub-gate 251 in the double-gate Oxide thin film transistor is L5, and L5 is a direct factor affecting the pixel aperture ratio and resolution of the display substrate. Figure 2 In the double-gate Oxide thin film transistor, the channel length L2 corresponding to the first sub-gate 231 is a direct factor affecting the pixel aperture ratio and resolution. Since L5 = L2 - 2ΔL and L5 < L2, therefore, compared with Figure 2 , Figure 4 the structure shown can improve the pixel aperture ratio and resolution of the display substrate.

[0063] As Figure 4 shown, L5 = L2 - 2ΔL and L6 = L1 - 2ΔL. Correspondingly, the length of the first active layer 241 can also be reduced by 2ΔL. Thus, the size of the first thin film transistor is reduced, and the pixel aperture ratio and resolution can be improved.

[0064] By comparing Figure 4 and Figure 2 , the display substrate of the embodiment of the present disclosure can reduce the size of the double-gate Oxide thin film transistor and improve the pixel aperture ratio and resolution while ensuring the stability of the device characteristics of the double-gate Oxide thin film transistor.

[0065] In one implementation manner, as Figure 3 and Figure 4 shown, the orthographic projection of the second insulating layer 34 on the substrate 10 includes the orthographic projection of the first active layer 241 on the substrate 10. Thus, the second insulating layer 34 can completely cover the first active layer 241. Therefore, a plasma implantation process needs to be used to conduct the conductive region of the first active layer 241, as Figure 3 and Figure 4 As shown, the first active layer 241 includes conductive regions located on both sides of the second sub-gate 251 .

[0066] Figure 5 FIG. 1 is a schematic cross-sectional view of a substrate in another embodiment of the present disclosure. Figure 5 As shown, the orthographic projection of the second insulating layer 34 on the base substrate 10 coincides with the orthographic projection of the second sub-gate 251 on the base substrate 10. In this structure, the conductive area of ​​the first active layer 241 is not blocked by the second insulating layer 34, and the conductive area of ​​the first active layer 241 is more easily conductive, which is beneficial to improving the on-state current I of the oxide thin film transistor. on .

[0067] For example, plasma gas (Plasma) such as He can be used to conduct the conductor area of ​​the first active layer 241, avoiding the use of a plasma implantation process for conductorization, simplifying the process and saving costs.

[0068] For example, Figure 5 and Figure 4 As shown, Figure 5 The channel length corresponding to the second sub-gate 251 is L7, L7 = L5; Figure 5 The channel length corresponding to the first sub-gate 231 is L8, L8 = L6. The effective channel length of the second sub-gate 251 is L eff5 = L7-2ΔL, the effective channel length L of the first sub-gate 231 eff6 =L8.

[0069] For example, Figure 5 As shown, the orthographic projection of the second insulating layer 34 on the base substrate 10 coincides with the orthographic projection of the second sub-gate 251 on the base substrate 10. Thus, the second insulating layer 34 and the second sub-gate 251 can be formed by a single patterning process using the same mask, thereby simplifying the process of the display substrate and reducing costs.

[0070] Figure 6 FIG. 1 is a schematic cross-sectional view of a substrate in another embodiment of the present disclosure. Figure 6 As shown, the display substrate may further include a third insulating layer 35, which may also be called a second interlayer insulating layer. The third insulating layer 35 is located on the side of the second sub-gate 251 facing away from the base substrate 10. For example, the material of the third insulating layer 35 may include silicon nitride. For example, the material of the third insulating layer 35 may be silicon nitride. A third insulating layer 35 made of such a material can reduce damage to the third insulating layer 35 caused by BOE etching, thereby preventing cracks in the third insulating layer 35.

[0071] In one embodiment, Figure 6 As shown, the display substrate may further include a second thin film transistor, which includes a second active layer 211. The material of the second active layer 211 includes a polycrystalline silicon semiconductor. Exemplarily, the material of the second active layer 211 is low-temperature polycrystalline silicon (LTPS), for example, the material of the second active layer 211 is P-Si. The second thin film transistor may further include a second gate electrode 221. Exemplarily, the second active layer 211 is located on the side of the base substrate 10 facing the first active layer 241. The display substrate may further include a first gate insulating layer 31. The first gate insulating layer 31 is located on the side of the second active layer 211 facing away from the base substrate 10, and the second gate electrode 221 is located on the side of the first gate insulating layer 31 facing away from the base substrate 10.

[0072] In one embodiment, Figure 6 As shown, the display substrate may further include a second gate insulating layer 32 , which is located on a side of the second gate electrode 221 away from the base substrate 10 , and the first sub-gate 231 is located on a side of the second gate insulating layer 32 away from the base substrate 10 .

[0073] The display substrate may further include a source / drain metal layer, such as Figure 6 As shown, the source-drain metal layer includes a first source electrode 261, a first drain electrode 262, a second source electrode 263, and a second drain electrode 264. The first source electrode 261 and the first drain electrode 262 are connected to the conductive region of the first active layer 241 through first vias 351a and 351b, respectively. The second source electrode 263 and the second drain electrode 264 are connected to the first active layer 211 through second vias 352a and 352b, respectively.

[0074] For example, Figure 6 As shown, the substrate 10 may include a substrate 11, a base 12, a barrier layer 13, and a first buffer layer 14 stacked in sequence. The second active layer 211 is located on a side of the first buffer layer 14 facing away from the substrate 11. Exemplarily, the material of the substrate 12 may include an organic material, for example, the material of the substrate 12 may include polyimide (PI).

[0075] For example, Figure 6 As shown, the first insulating layer 33 may include an interlayer insulating layer 331 and a second buffer layer 332 that are stacked, and the second buffer layer 332 is close to the first active layer 241 .

[0076] In one embodiment, the range of the size of the first sub-gate 231 in the first direction X is less than or equal to 3.5 μm. In one embodiment, the range of the size of the second sub-gate 251 in the first direction X is 4.5 μm to 5.5 μm (including endpoint values). Exemplarily, the size of the second sub-gate 251 in the first direction can be any value between 4.5 μm and 5.5 μm. Exemplarily, the difference between the size of the second sub-gate 251 in the first direction and the size of the first sub-gate 231 in the first direction is 1 μm to 2 μm. Such a size setting method can avoid problems caused by alignment deviation and uneven etching, and ensure that the orthographic projection of the second sub-gate 251 on the base substrate 10 includes the orthographic projection of the first sub-gate 231 on the base substrate 10.

[0077] In the specific implementation process of the technical solution disclosed in the present invention, the key to improving the aperture ratio and resolution is to reduce the channel length corresponding to the second sub-gate 251. In order to ensure that the orthographic projection of the second sub-gate 251 on the base substrate 10 can include the orthographic projection of the first sub-gate 231 on the base substrate 10, the channel length corresponding to the second sub-gate 251 should be reduced by the same amount while the channel length corresponding to the first sub-gate 231 is reduced by the same amount. For example, when the channel length corresponding to the second sub-gate 251 is 4.5μm and the channel length corresponding to the first sub-gate 231 is 3μm, in order to improve the aperture ratio and resolution of the product, the channel length corresponding to the second sub-gate 251 can be reduced by 0.5μm, so that the channel length corresponding to the second sub-gate 251 is reduced to 4μm. At this time, the channel length corresponding to the first sub-gate 231 needs to be reduced by 0.5μm by the same amount, so that the channel length corresponding to the first sub-gate 231 is reduced to 2.5μm. After reducing the channel length corresponding to the first sub-gate 231 to 2.5μm, it is necessary to consider the impact of the channel length corresponding to the first sub-gate 231 on the stability of the characteristics of the oxide thin-film transistor device. In other words, when adopting the technical solution of the present disclosure, when reducing the channel length corresponding to the second sub-gate 251, the channel length corresponding to the first sub-gate 231 must be reduced equally. At the same time, the impact on the stability of the characteristics of the oxide thin-film transistor device must be considered to avoid the channel length of the first sub-gate 231 failing to meet product requirements.

[0078] The display substrate of the present disclosure can be used in an organic light-emitting diode (OLED) display panel. For example, an OLED device can be fabricated on the side of the source and drain electrode layers facing away from the base substrate. The OLED device can be a top-emitting OLED device, meaning that the light-emitting side of the display panel is located away from the base substrate.

[0079] In an exemplary embodiment, the gate insulating layer, buffer layer, barrier layer, and interlayer insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The gate electrode, source electrode, and drain electrode may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Ti / Al / Ti.

[0080] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a first thin film transistor, and the first thin film transistor includes a first active layer, a first sub-gate, and a second sub-gate. The method includes:

[0081] forming a first sub-gate on one side of the substrate;

[0082] forming a first insulating layer on a side of the first sub-gate facing away from the substrate;

[0083] forming a first active layer on a side of the first insulating layer away from the substrate, wherein the material of the first active layer includes an oxide semiconductor;

[0084] forming a second insulating layer and a second sub-gate on a side of the first active layer away from the base substrate, wherein the second insulating layer is close to the first active layer, and an orthographic projection of the second sub-gate on the base substrate includes an orthographic projection of the first sub-gate on the base substrate;

[0085] The first active layer is conductively conductive to form a conductive region, wherein the orthographic projection of the conductive region on the base substrate is located on both sides of the orthographic projection of the second sub-gate on the base substrate.

[0086] Figure 7 The figure is a schematic cross-sectional view of a display substrate after the first active layer is conductively converted in one embodiment of the present disclosure. The technical solution of the embodiment of the present disclosure is further explained below through the preparation process of the display substrate in one embodiment of the present disclosure. It can be understood that the "patterning" mentioned herein includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant technology.

[0087] The base substrate 10 is formed. The process may include: forming a base 12, a barrier layer 13 and a first buffer layer 14 in sequence on one side of the substrate 11, such as Figure 7 shown.

[0088] A second active layer 211 and a second gate electrode 221 of a second thin film transistor are formed on one side of the base substrate 10. Figure 7 As shown, this step may include: forming a second active layer 211 on the side of 14 facing away from the substrate 11; forming a first gate insulating layer 31 on the side of the second active layer 211 facing away from the substrate 10; forming a second gate electrode 221 on the side of the first gate insulating layer 31 facing away from the substrate 10; and forming a second gate insulating layer 32 on the side of the second gate electrode 221 facing away from the substrate 10.

[0089] Forming a first sub-gate 231 on one side of the base substrate may include: forming the first sub-gate 231 on a side of the second gate insulating layer 32 away from the base substrate 10; Figure 7 shown.

[0090] A first insulating layer 33 is formed on the side of the first sub-gate 231 away from the substrate. For example, the first insulating layer 33 includes an interlayer insulating layer 331 and a second buffer layer 332 stacked together. The interlayer insulating layer 331 is close to the first sub-gate 231. Figure 7 shown.

[0091] A first active layer 241 is formed on a side of the first insulating layer 33 away from the substrate. The material of the first active layer 241 includes an oxide semiconductor. Figure 7 shown.

[0092] A second insulating layer 34 and a second sub-gate 251 are formed on the side of the first active layer 241 away from the substrate. Figure 7 As shown, this step may include: depositing a second insulating layer 34 on a side of the first active layer 241 facing away from the base substrate; depositing a gate film on a side of the second insulating layer 34 facing away from the base substrate 10, and patterning the gate film to form a second sub-gate 251. The orthographic projection of the second sub-gate 251 on the base substrate includes the orthographic projection of the first sub-gate 231 on the base substrate. The orthographic projection of the second insulating layer 34 on the base substrate includes the orthographic projection of the first active layer 241 on the base substrate, so that the second insulating layer 34 covers the first active layer 241.

[0093] Conduct the first active layer 241 to form a conductive region. Exemplarily, the conductive region of the first active layer 241 can be conductive by a plasma implantation process. The orthographic projection of the conductive region on the substrate is located on both sides of the orthographic projection of the second sub-gate 251 on the substrate. The first active layer 241 also includes a channel region, and the orthographic projection of the channel region on the substrate coincides with the orthographic projection of the second sub-gate 251 on the substrate. The conductive region is located on both sides of the channel region. The channel region includes an effective channel and an ineffective channel. Figure 7Where L3 is the length of the channel region, L eff1 is the effective channel length, and ΔL is the ineffective channel length.

[0094] Figure 8 This is a cross-sectional schematic diagram showing another embodiment of the present disclosure after the first active layer in the substrate is conductively converted.

[0095] A second insulating layer 34 and a second sub-gate 251 are formed on the side of the first active layer 241 away from the substrate. Figure 8 As shown, this step may include: depositing a second insulating film and a gate film in sequence on the side of the first active layer 241 away from the substrate; patterning the second insulating film and the gate film using a single mask process to form a second insulating layer 34 and a second sub-gate 251. For example, a photoresist may be coated on the gate film, exposed and developed, the photoresist remaining at the position of the second sub-gate 251 and the photoresist removed at other positions; etching the area without the photoresist to remove the second insulating film and the gate film, and the remaining second insulating film and the gate film are the second insulating layer 34 and the second sub-gate 251, as shown in FIG. Figure 8 The orthographic projection of the second insulating layer 34 on the substrate coincides with the orthographic projection of the second sub-gate 251 on the substrate.

[0096] Conduct the first active layer 241 to form a conductive region. Exemplarily, the conductive region of the first active layer 241 can be conductive using plasma gas (such as He). The orthographic projection of the conductive region on the substrate is located on both sides of the orthographic projection of the second sub-gate 251 on the substrate. The first active layer 241 also includes a channel region, and the orthographic projection of the channel region on the substrate coincides with the orthographic projection of the second sub-gate 251 on the substrate. The conductive region is located on both sides of the channel region. The channel region includes an effective channel and an ineffective channel. Figure 8 Where L7 is the length of the channel region, L eff5 is the effective channel length, and ΔL is the ineffective channel length.

[0097] In one embodiment, the method for preparing a display substrate may further include the following steps:

[0098] A third insulating layer 35 is deposited on the side of the second sub-gate 251 away from the substrate. The material of the third insulating layer 35 may include silicon nitride. The insulating layer is patterned to form first via holes 351a and 351b and second via holes 352a and 352b. The first via holes 351a and 351b penetrate the third insulating layer 35 and the second insulating layer 34 to expose the conductive area of ​​the first active layer 241. The second via holes 352a and 352b penetrate the third insulating layer 35, the second insulating layer 34, the first insulating layer 33, the third insulating layer 34, the first insulating layer 35, the second insulating layer 34, the first insulating layer 33, the third insulating layer 35, the second insulating layer 34, the first insulating layer 33, the third insulating layer 35, the second insulating layer 34, the first insulating layer 33, the third insulating layer 35, the second insulating layer 34, the first insulating layer 33, the first insulating layer 33, the second ... The second gate insulating layer 32 and the first gate insulating layer 31 expose the second active layer 211; a first source electrode 261, a first drain electrode 262, a second source electrode 263 and a second drain electrode 264 are formed on the side of the third insulating layer 35 away from the substrate, the first source electrode 261 and the first drain electrode 262 are connected to the first active layer 241 through first via holes 351a and 351b respectively, and the second source electrode 263 and the second drain electrode 264 are connected to the second active layer 211 through second via holes 352a and 352b respectively. Figure 6 shown.

[0099] Based on the inventive concepts of the aforementioned embodiments, embodiments of the present disclosure further provide a display device. For example, the display device may be an OLED display device. The display device includes the display substrate of any embodiment of the present disclosure. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0100] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0102] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0103] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0104] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0105] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this disclosure, and such modifications or substitutions should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: The display substrate includes a first thin film transistor, wherein the first thin film transistor includes a first sub-gate, a second sub-gate, and a first active layer. The display substrate includes: The first sub-gate is located on one side of the substrate; a first insulating layer, located on a side of the first sub-gate facing away from the substrate; The first active layer is located on a side of the first insulating layer away from the base substrate, and the material of the first active layer includes an oxide semiconductor; a second insulating layer, located on a side of the first active layer away from the base substrate; The second sub-gate is located on a side of the second insulating layer away from the base substrate, and the orthographic projection of the second sub-gate on the base substrate includes the orthographic projection of the first sub-gate on the base substrate; Among them, the channel corresponding to the second sub-gate on the first active layer includes an effective channel located in the middle and ineffective channels located on both sides of the effective channel, the size of the effective channel in the first direction is larger than the size of the first sub-gate in the first direction, and the first direction is the arrangement direction of the effective channel and the ineffective channel.

2. The display substrate according to claim 1, wherein: An orthographic projection of the second insulating layer on the base substrate includes an orthographic projection of the first active layer on the base substrate.

3. The display substrate according to claim 1, wherein An orthographic projection of the second insulating layer on the base substrate coincides with an orthographic projection of the second sub-gate on the base substrate.

4. The display substrate according to claim 1, wherein: The display substrate further includes a third insulating layer, the third insulating layer is located on a side of the second sub-gate away from the base substrate, and the material of the third insulating layer includes silicon nitride.

5. The display substrate according to claim 1, wherein The device further includes a second thin film transistor, which includes a second active layer. The material of the second active layer includes polycrystalline silicon semiconductor.

6. The display substrate according to claim 5, wherein: The second thin film transistor also includes a second gate electrode, and the second active layer is located on the side of the base substrate facing the first active layer. The display substrate also includes a first gate insulating layer and a second gate insulating layer, the first gate insulating layer is located on the side of the second active layer facing away from the base substrate, the second gate electrode is located on the side of the first gate insulating layer facing away from the base substrate, the second gate insulating layer is located on the side of the second gate electrode facing away from the base substrate, and the first sub-gate is located on the side of the second gate insulating layer facing away from the base substrate.

7. The display substrate according to claim 1, wherein: The first sub-gate has a size in the first direction less than or equal to 3.5 μm, and the second sub-gate has a size in the first direction of 4.5 μm to 5.5 μm. The first direction is the arrangement direction of the conductive region and the channel region of the first active layer.

8. A method for preparing a display substrate, characterized in that: The method is used to prepare a display substrate according to any one of claims 1 to 7; the display substrate includes a first thin film transistor, the first thin film transistor includes a first active layer, a first sub-gate, and a second sub-gate, and the method includes: forming the first sub-gate on one side of the base substrate; forming a first insulating layer on a side of the first sub-gate facing away from the substrate; forming a first active layer on a side of the first insulating layer away from the base substrate, wherein the material of the first active layer includes an oxide semiconductor; forming a second insulating layer and a second sub-gate on a side of the first active layer away from the base substrate, wherein the second insulating layer is close to the first active layer, and an orthographic projection of the second sub-gate on the base substrate includes an orthographic projection of the first sub-gate on the base substrate; The first active layer is conductively conductive to form a conductive region, wherein the orthographic projection of the conductive region on the base substrate is located on both sides of the orthographic projection of the second sub-gate on the base substrate.

9. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 7.

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