A novel high-transconductance enhanced HEMT device and a method for manufacturing the same

Abstract

The application relates to a novel high-transconductance enhanced HEMT device and a preparation method thereof, which comprises a substrate with a first surface and a second surface, an Al-component gradient buffer layer arranged on the first surface of the substrate, a multiple three-dimensional fin-shaped gate comprising at least two three-dimensional fin-shaped gate units, the three-dimensional fin-shaped gate unit being composed of a heterojunction channel layer, a cap layer and a gate metal layer which are sequentially stacked on the buffer layer; a source and a drain are respectively arranged on both sides of the multiple three-dimensional fin-shaped gate and are located on the buffer layer; a substrate electrode is located on the second surface of the substrate; the buffer layer, the channel layer and the cap layer form a PNP structure, and in the direction from the source to the drain, the gate metal also covers the sidewall of the three-dimensional fin-shaped gate, the device structure of the application realizes better gate control, and the transconductance value is obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of HEMT devices, in particular to a novel high-transconductance enhancement-mode HEMT device and a preparation method thereof. BACKGROUND

[0002] AlGaN / GaN HEMT devices, based on the high-concentration and high-mobility two-dimensional electron gas generated at the AlGaN and GaN heterojunction interface, can achieve high saturation current density and low on-resistance, and have been increasingly widely used in the fields of high frequency and high power, and have a good development prospect in academic research and production research and development.

[0003] However, the ordinary HEMT device has certain problems, that is, the electrons are not constrained on the two-dimensional interface of the heterojunction, so it is a normally-on (depletion-mode) device. Such a device may produce overshoot or lose power control during the starting process, so the existence of a normally-off (enhancement-mode) HEMT becomes very important. The existing common normally-off GaN HEMT devices are of two types: common-source common-gate and single-body enhancement mode. Since the common-source common-gate needs to be connected in series with a Si MOSFET and a depletion-mode HEMT, this leads to the generation of parasitic inductance when working at high frequency, and such a connection method makes the packaging more complex, so the single-body enhancement-mode HEMT with smaller parasitic parameters has a more extensive demand. For the single-body enhancement-mode HEMT, transconductance measures the speed of switching, and a substantial increase in transconductance is of great significance to the performance of the device.

[0004] At present, according to the content disclosed by the prior art, for the AlGaN / GaN HEMT, the best value obtained by the domestic high-transconductance research has not exceeded 400 mS / mm, so there is still a great development space in the research on the transconductance characteristics. SUMMARY

[0005] The purpose of the present application is to provide a high-quality enhancement-mode HEMT device with high transconductance and low leakage current and a preparation method thereof. The novel high-transconductance enhancement-mode HEMT device adopts a multi-finger interlocking gate control structure, a substrate electrode, and a P-type GaN cap layer, an N-type AlGaN / GaN heterojunction channel layer, and a P-type graded buffer layer to form a PNP structure. When the device is packaged, the multi-finger interlocking gate control structure and the substrate electrode at the bottom are short-circuited together. Under the condition of no power supply, the P-type GaN cap layer with high doping concentration and the graded buffer layer with high concentration 3DHG will interact with the AlGaN / GaN heterojunction channel layer sandwiched in between, and two depletion regions are formed by the PNP structure to consume a certain electron concentration. When the gate and the substrate electrode are simultaneously applied with a forward bias, the thickness of the depletion region rapidly decreases, which is helpful for the conduction of the device; and when the gate and the substrate electrode are simultaneously applied with a reverse bias, the thickness of the depletion region increases, which is helpful for the turn-off of the device.

[0006] The application adopts at least the following technical solutions:

[0007] A novel high-transconductance enhanced HEMT device, a substrate, having a first surface and a second surface; an Al composition gradient buffer layer, arranged on the first surface of the substrate;

[0008] A multiple three-dimensional fin-shaped gate comprising at least two three-dimensional fin-shaped gate units, the three-dimensional fin-shaped gate units being composed of a heterojunction channel layer, a cap layer and a gate metal layer which are sequentially stacked on the buffer layer;

[0009] A source electrode and a drain electrode, respectively arranged on both sides of the multiple three-dimensional fin-shaped gate and located on the buffer layer;

[0010] A substrate electrode located on the second surface of the substrate;

[0011] Wherein, the buffer layer, the channel layer and the cap layer form a PNP structure, and the gate metal also covers the sidewall of the three-dimensional fin-shaped gate in the direction from the source electrode to the drain electrode.

[0012] Further, the Al composition of the buffer layer decreases linearly or nonlinearly in the direction from the substrate to the gate.

[0013] Further, the buffer layer is made of Al x1 In y1 Ga (1-x1-y1) N or Al z1 Ga (1-z1) N, wherein 0

[0014] Further, the channel layer is made of a periodic Al z2 Ga (1-z2) N / GaN heterojunction or Al x2 In y2 Ga (1-x2-y2) N / GaN heterojunction, wherein 0

[0015] Further, in the channel layer, the thickness of Al z2 Ga (1-z2) N or Al x2 In y2 Ga (1-x2-y2) N is selected to be 15-30 nm, the thickness of the GaN channel layer is 10-50 nm, and preferably the thickness of the GaN layer is 10 nm.

[0016] Further, a passivation layer is arranged between the gate metal and the source and drain; the substrate is selected from a native GaN substrate, an AlGaN substrate or an AlInGaN substrate.

[0017] Further, the cap layer also covers the sidewall of the channel layer in the three-dimensional fin-shaped gate.

[0018] Further, the cap layers of adjacent multiple three-dimensional fin-shaped gates have a certain gap, and the gate metal layer also fills the gap.

[0019] Further, the cap layers of adjacent multiple three-dimensional fin-shaped gates are in contact.

[0020] The application also provides a preparation method of a novel high-transconductance enhanced HEMT device, comprising the following steps:

[0021] A graded buffer layer and a heterojunction channel layer are epitaxially grown on a first surface of a substrate in sequence;

[0022] The heterojunction channel layer is etched to a certain depth in the graded buffer layer to form a multi-fin structure;

[0023] A cap layer growth window is formed, and a cap layer is grown;

[0024] A passivation layer is deposited to form source and drain openings;

[0025] A source and drain metal layer is deposited to form ohmic-contact source and drain;

[0026] The passivation layer is etched to form a gate opening;

[0027] A gate metal layer is deposited to form a multiple three-dimensional fin-shaped gate;

[0028] A metal layer is deposited on a second surface of the substrate to form a Schottky-contact substrate electrode;

[0029] The buffer layer, the channel layer and the cap layer form a PNP structure.

[0030] Compared with the prior art, the application has at least the following beneficial effects:

[0031] The high-transconductance enhanced HEMT device of the application adopts a multi-fin interlocking gate control structure, and the cap layer, the heterojunction channel layer and the graded buffer layer form a PNP structure, the cap layer is located at the top of the channel layer in the fin-shaped structure or the cap layer is located at the top of the channel layer in the fin-shaped structure and the sidewall of the fin-shaped structure to form a semi-enclosed structure, which, together with the gate metal, realizes better gate control, and the transconductance value of the HEMT device of the application is significantly improved.

[0032] The application provides a novel high-transconductance enhanced HEMT device, wherein the graded buffer layer adopts a negative gradient Al component change along the growth direction, and high-concentration three-dimensional hole gas (3DHG) is generated in the buffer layer due to polarization doping, which significantly offsets the influence of donor impurities such as silicon (Si) and oxygen (O) introduced from the environment during the growth of the bulk material. The use of the Al component graded buffer layer on the native substrate greatly reduces the occurrence of mismatch dislocations and cracks in the buffer layer, and helps to obtain high-quality epitaxial layers. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 Figure 1 is a partial structure schematic diagram of the enhanced HEMT device of the application, which structure comprises three fin structures combined together, and the number of fin structures included in the structure can be flexibly adjusted according to needs.

[0034] Figure 2 Figure 2 is a three-dimensional preparation process schematic diagram of the novel high-transconductance enhanced HEMT device of Example 1, and only a single fin structure is shown for clearer display.

[0035] Figure 3 Figure 3 is a two-dimensional preparation process schematic diagram of the novel high-transconductance enhanced HEMT device of Example 1, and only a single fin structure is shown for clearer display.

[0036] Figure 4 Figure (a) is a growth mode structure schematic diagram of the p-type GaN cap layer in Example 1; Figure (b) is a growth mode structure schematic diagram of the p-type GaN cap layer in Example 2; and Figure (c) is a growth mode structure schematic diagram of the p-type GaN cap layer in Example 3.

[0037] Figure 5 Figure 4 is a transconductance comparison schematic diagram of the enhanced HEMT device of Example 1, Example 2, Example 3, the non-fin gate HEMT comparative structure (PNP-HEMT), and the common HEMT comparative structure (CON-HEMT) under the condition of a drain voltage of 10V. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present application. In the following embodiments, the experimental methods are all conventional methods unless otherwise specified, and the reagents and materials are all available from public commercial channels unless otherwise specified.

[0039] Spatial relative terms such as "under", "below", "lower", "on", "above", "upper" and the like, are used herein for ease of description to explain the positioning of one element relative to a second element. Except for different orientations than those shown in the figures, these terms are intended to encompass different orientations of the device.

[0040] In addition, terms such as "first", "second" and the like are used to describe various elements, layers, regions, sections and the like, and are not intended to be limiting. "Have", "contain", "include", "comprise" and the like are open terms, indicating the presence of the stated elements or features, but not excluding additional elements or features. Unless the context clearly dictates otherwise.

[0041] As Figure 1 shown, an embodiment of the present application provides a new high-transconductance enhanced HEMT device, which includes a substrate 1, an Al composition gradient buffer layer 2, a multi-three-dimensional fin-shaped gate, a source 7, a drain 8 and a substrate electrode 10.

[0042] The substrate 1 is selected from a GaN native substrate, an AlGaN substrate containing a certain Al composition or an AlInGaN substrate containing Al and In compositions. The Al composition gradient buffer layer 2 is located on the substrate 1, and is selected from an Al x1 In y1 Ga (1-x1-y1) N or Al z1 Ga (1-z1) N material, wherein 0 < x1 < 0.83, 0 < y1 < 0.17, 0 < z1 < 0.83, x1 represents the linear or nonlinear decrease of the Al composition content along the growth direction of the buffer layer (from the lower boundary to the upper boundary of the gradient buffer layer); y1 represents the linear or nonlinear decrease of the In composition content along the growth direction of the buffer layer (from the lower boundary to the upper boundary of the gradient buffer layer); z1 represents the linear or nonlinear decrease of the In composition content along the growth direction of the buffer layer (from the lower boundary to the upper boundary of the gradient buffer layer). Preferably, the Al composition gradient buffer layer 2 is selected from an Al z1 Ga (1-z1)N material, where z1 linearly varies from 0.5 to 0 along the direction from the lower boundary to the upper boundary of the buffer layer.

[0043] The multiple three-dimensional fin-shaped gates include at least two three-dimensional fin-shaped gate units, which are periodically distributed. The shape of each fin structure is a "convex" character in cross-section. Multiple fin regions are arranged side by side and are wrapped by gate metal, forming a multi-fin interlocked gate control structure. The three-dimensional fin-shaped gate units are arranged between the source 7 and the drain 8. Preferably, the width of a single three-dimensional fin-shaped gate unit is 40 nm, and the distance between adjacent gate units is 20 nm.

[0044] The three-dimensional fin-shaped gate unit is composed of a channel layer, a cap layer, and a gate metal layer stacked in sequence on the graded buffer layer 2. The channel layer is a heterojunction composed of periodically arranged first material layer 3 and second material layer 4. This heterojunction is, for example, an Al z2 Ga (1-z2) N / GaN heterojunction or an Al x2 In y2 Ga (1-x2-y2) N / GaN heterojunction, and the number of periods of the heterojunction does not exceed 5. In the channel layer, the thickness of Al z2 Ga (1-z2) N or Al x2 In y2 Ga (1-x2-y2) N is selected to be 15 - 30 nm. The thickness of the GaN layer is selected to be 10 nm to 50 nm. Preferably, the thickness of the GaN layer is selected to be 10 nm. In the Al z2 Ga (1-z2) N / GaN heterojunction, the range of the Al component is 0 < z2 < 0.83. Preferably, an AlGaN barrier layer with a thickness of 20 nm and z2 = 0.25 is selected; in the Al x2 In y2 Ga (1-x2-y2) N / GaN heterojunction, the Al component and the In component are respectively selected as 0 < x2 < 0.83, 0 < y2 < 0.17.

[0045] The cap layer 5 is a p-type GaN cap layer, and its doping concentration is greater than 5×10 19 cm -3 , and the thickness is 30 - 100 nm. The cap layer is selected in three growth modes. In a preferred embodiment, referring to Figure 4 Figure (a), the cap layer only covers the top of the channel layer; in another preferred embodiment, as shown in Figure 4 Figure (b), the cap layer covers the top of the channel layer and covers a certain thickness along the sidewall of the channel layer to form a thin layer. Horizontally, there is a certain gap between the p-type GaN cap layers of adjacent fin structures, and this gap is filled with gate metal in subsequent process steps; in another preferred embodiment, asFigure 4 As shown in (c), the cap layer covers the top of the channel layer and has a certain thickness along the sidewall of the channel layer. It is closely connected with the adjacent fin structure in the horizontal direction. In subsequent process steps, the gate metal 9 covers the top of the cap layer 5.

[0046] Passivation layer 6 covers the gate and drain, as well as the space between the gate and source. The material used for the passivation layer is SiN. x SiO2, Al2O3 or TiO2, with a thickness of 10 to 50 nanometers.

[0047] To make the enhanced HEMT device clearer, one aspect of the present invention also provides a method for fabricating the novel high transconductance enhanced HEMT device.

[0048] Example 1

[0049] See Figures 2-3 First, GaN native substrate 1 was selected and ultrasonically cleaned with acetone, ethanol and deionized water for 10 minutes each. Then it was rinsed with deionized water and finally dried with N2 to remove contaminants from the substrate surface.

[0050] Next, the gradient buffer layer 2 was grown: MOCVD was used, employing trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH3) as the aluminum source, gallium source, and nitrogen source, respectively. An Al layer with a thickness of 0.5 micrometers was grown at 500℃. z1 Ga (1-z1) The N buffer layer controls the Al composition to decrease linearly or non-linearly to 0 along the growth direction during growth.

[0051] Trimethylgallium (TMGa) and ammonia (NH3) were used as gallium and nitrogen sources, respectively, to grow a first material GaN layer 3 with a thickness of 0.01 micrometers at a temperature of 1050℃.

[0052] A second material, Al, was grown at 500°C using trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and ammonia (NH3) as the aluminum, gallium, indium, and nitrogen sources, respectively. x2 In y2 Ga (1-x2-y2) In N layers, by controlling different growth source flow rates and growth temperatures, where x² = 0.25 and y² = 0, second materials Al with different compositions were obtained. 0.25 Ga 0.75 N layer 4, Al 0.25 Ga 0.75 The N-layer has a growth thickness of 0.02 micrometers.

[0053] Then, the second material AlGaN layer 4 is etched by using an inductively coupled plasma etching technique (ICP) to form a plurality of fin structures. 0.25 Ga 0.75 The N layer 4 and the first material GaN layer 3 are etched to a certain depth in the graded buffer layer to form a plurality of fin structures, and the width of each fin structure is 40 nm.

[0054] Then, the P-type GaN cap layer 5 is grown according to the window defined by the photoetching plate. Trimethyl gallium (TMGa) is used as the gallium source, Cp2Mg is used as the magnesium source, and ammonia (NH3) is used as the nitrogen source. The P-type GaN cap layer 5 with a thickness of 20-100 nm is grown at a temperature of 950°C, the flow rate of the magnesium source is 150 sccm, and the molar ratio of the nitrogen source to the gallium source (V / III ratio) is 3060. After growth, the P-type GaN cap layer 5 is annealed in an N2 atmosphere containing Mg at 750°C for 30 min, as shown in Fig. (a) of the accompanying drawings. Figure 4 As shown in Fig. (a) of the accompanying drawings, the P-type GaN cap layer 5 is grown only on the top of the fin structures.

[0055] Then, a SiN4 passivation layer 6 is deposited on the surface obtained after the above steps by using a plasma enhanced chemical vapor deposition (PECVD) process.

[0056] Then, the passivation layer 6, the second material AlGaN layer 4, and the first material GaN layer 3 are etched by using a reactive ion etching (RIE) process to a certain depth below the surface of the graded buffer layer 2 to form source and drain openings.

[0057] The source and drain metal layers are deposited by using an electron beam evaporation process to deposit Ti / Al / Ni / Au (25 nm / 110 nm / 45 nm / 25 nm) metal electrodes on the surface obtained after the above steps, and the metal electrodes are annealed in an N2 atmosphere at a temperature of 850°C for 45 seconds to form the ohmic contact source 7 and the drain 8.

[0058] Then, the passivation layer is etched to form a gate opening on the passivation layer, and the fin structures are retained, and the remaining areas are etched to the surface of the P-type GaN cap layer 5.

[0059] The gate and substrate electrode metal layers are deposited by using an electron beam evaporation process to deposit Ni / Au (20 nm / 200 nm) metal electrodes on the upper and lower surfaces obtained after the above steps, and the metal electrodes are annealed in an N2 atmosphere at a temperature of 45°C for 8 minutes to form the Schottky contact gate 9 and the substrate electrode 10.

[0060] Example 2

[0061] The preparation steps of the HEMT device are basically the same as those of Example 1, and the only difference is that the P-type GaN cap layer is grown as shown in Fig. (a) of the accompanying drawings. Figure 4In the middle (b) of the figure, the P-type GaN cap layer is grown on the top of the fin structure and covers a certain thickness of the thin layer on the sidewall of the fin structure, and there is a certain gap between the P-type GaN cap layer of the horizontally adjacent fin structure, and the gap is filled with the gate metal in the subsequent process step.

[0062] Example 3

[0063] The preparation steps of the HEMT device are basically the same as those of Example 1, and the difference is only that the P-type GaN cap layer is grown, as shown in Figure 4 In the middle (c) of the figure, the P-type GaN cap layer is grown on the top of the fin structure and covers a certain thickness of the thin layer on the sidewall of the fin structure, and there is a certain gap between the P-type GaN cap layer of the horizontally adjacent fin structure, and the gap is filled with the gate metal in the subsequent process step.

[0064] As shown in Figure 5 , the transconductance comparison diagram under the HEMT device obtained by Example 1, Example 2, Example 3 of the present application, the non-fin gate HEMT comparison structure (labeled as PNP-HEMT) and the common HEMT comparison structure (labeled as Con-HEMT). Among them, the PNP-HEMT structure abandons the fin structure on the basis of the Fin-PNP-HEMT (structure of the present application), and becomes a structure with completely consistent cross-sectional view in all directions; the Con-HEMT structure abandons the P-type GaN cap layer 5 (the gate metal is directly deposited on the AlGaN barrier layer 4) and the Al x1 In y1 Ga (1-x1-y1) N or Al z1 Ga (1-z1) N material composition gradient buffer layer 2 (changed to GaN material composition buffer layer). Under the condition of drain voltage of 10V, the maximum transconductance of Example 1 is 474mS / mm, the maximum transconductance of Example 2 is 455mS / mm, the maximum transconductance of Example 3 is 167mS / mm, the maximum transconductance of PNP-HEMT is 85mS / mm, and the maximum transconductance of Con-HEMT is 335mS / mm. This shows that the enhancement mode HEMT device of the present application indeed effectively improves the transconductance of the HEMT device, and makes up for the defect of reduced transconductance caused by the PNP structure.

[0065] The novel high-transconductance enhancement mode HEMT device provided by the present application comprehensively considers the PNP structure composed of the multi-fin interlocking gate control structure, the P-type GaN cap layer, the N-type AlGaN / GaN heterojunction channel layer, the P-type gradient buffer layer and the substrate electrode, and the advantages of the two multi-fin interlocking gate control structures, optimizes the preparation process, and obtains a high-quality enhancement mode HEMT device with high transconductance value.

[0066] The above embodiments are the preferred embodiments of the present application, but the embodiments of the present application are not limited to the above embodiments, and any changes, modifications, substitutions, combinations, simplifications, etc. made without departing from the spirit and principles of the present application should be equivalent replacement manners and should be included in the protection scope of the present application.

Claims

1. A novel high transconductance enhancement mode HEMT device, characterized in that, a substrate having a first surface and a second surface; Al composition graded Al x1 In y1 Ga (1-x1-y1) N or Al z1 Ga (1-z1) N buffer layer arranged at a first surface of the substrate, the Al composition of the buffer layer decreasing linearly or non-linearly in a direction from the substrate towards the gate, wherein 0 < x1 < 0.83, 0 < y1 < 0.17, 0 < z1 < 0.83; a multi-three-dimensional fin-gate comprising at least two three-dimensional fin-gate units, the three-dimensional fin-gate units are composed of a heterojunction channel layer, a cap layer and a gate metal layer stacked in sequence on the buffer layer or the three-dimensional fin-gate units are composed of a heterojunction channel layer disposed on the buffer layer, a cap layer disposed on top and sidewall of the heterojunction channel layer, a gate metal layer disposed on top and sidewall of the cap layer; a source and a drain arranged on both sides of the multi-three-dimensional fin-gate respectively, located on the buffer layer and in contact with the surface of the buffer layer; a substrate electrode on the second surface of the substrate, the substrate electrode is shorted together with the multi-three-dimensional fin-gate; The buffer layer, the heterojunction channel layer and the cap layer constitute a PNP structure, and the gate metal covers the sidewall of the three-dimensional fin-shaped gate in the direction from the source to the drain. z2 Ga (1-z2) N / GaN heterojunction or Al x2 In y2 Ga (1-x2-y2) N / GaN heterojunction, wherein 0 < x2 < 0.83, 0 < y2 < 0.17, 0 < z2 < 0.83, and the period number of the heterojunction is not more than 5.

2. The enhancement mode HEMT device of claim 1, wherein, The thickness of Al z2 Ga (1-z2) N or Al x2 In y2 Ga (1-x2-y2) N is selected to be 15-30 nm, the thickness of GaN channel layer is 10-50 nm, and preferably, the thickness of GaN layer is 10 nm.

3. The enhancement mode HEMT device of claim 2, wherein, a passivation layer is disposed between the gate metal and the source and drain; the substrate is selected from native GaN substrate, AlGaN substrate or AlInGaN substrate.

4. A method of fabricating a novel high transconductance enhanced HEMT device, characterized by, comprising the following steps: Al of the Al composition graded buffer layer is grown on the first surface of the substrate in sequence x1 In y1 Ga (1-x1-y1) N or Al z1 Ga (1-z1) N and a heterojunction channel layer, an Al composition of the buffer layer decreases linearly or nonlinearly in a direction from the substrate to the gate, wherein 0 < x1 < 0.83, 0 < y1 < 0.17, and 0 < z1 < 0.

83. etching along the heterojunction channel layer to a certain depth in the graded buffer layer to form a multi-fin structure; forming a cap layer growth window, growing a cap layer, the cap layer is located on top of the heterojunction channel layer or the cap layer is located on top and sidewall of the heterojunction channel layer; depositing a passivation layer to form source and drain openings extending to a certain depth in the buffer layer; depositing a source and drain metal layer to form ohmic contact source and drain on both sides of the multi-fin structure; etching the passivation layer to form a gate opening; depositing a gate metal layer to form a multi-three-dimensional fin-gate, the gate metal layer is located on top of the cap layer or the gate metal layer is located on top and sidewall of the cap layer; depositing a metal layer on the second surface of the substrate to form a Schottky contact substrate electrode, the substrate electrode is shorted together with the multi-three-dimensional fin-gate; The buffer layer, the channel layer and the cap layer constitute a PNP structure, the heterojunction channel layer is selected from Al z2 Ga (1-z2) N / GaN heterojunction or Al x2 In y2 Ga (1-x2-y2) N / GaN heterojunction, wherein 0 < x2 < 0.83, 0 < y2 < 0.17, 0 < z2 < 0.83, and the number of periods of the heterojunction is not more than 5.

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