Band contact ring / multi-gate semiconductor device and manufacturing method and electronic device

Abstract

Disclosed is a vertical semiconductor device having a body contact, a method of manufacturing the same, and an electronic device including the same. According to an embodiment, the semiconductor device can include an active region vertically disposed on a substrate with respect to the substrate, including a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region to define a channel region; a first gate stack and a second gate stack disposed on first and second sides of the active region opposite each other in a lateral direction with respect to the substrate; and a body contact layer disposed on the second side of the active region to overlap a portion of the middle portion of the active region to apply a body bias to the active region, wherein the second gate stack includes a first portion under the body contact layer and a second portion above the body contact layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a ring-gate or multi-gate vertical semiconductor device with body contact and a method of manufacturing the same, and an electronic device including the same. BACKGROUND

[0002] To meet the demand for metal-oxide-semiconductor field-effect transistors (MOSFETs) to be increasingly miniaturized, various types of devices have been proposed, such as fin field-effect transistors (FinFETs), multi-bridge-channel field-effect transistors (MBCFETs), etc. However, they still have certain limitations.

[0003] Vertical FETs are a promising type of MOSFETs in terms of miniaturization. However, fully-depleted vertical FETs have a floating body effect, which can cause threshold voltage (Vt) shift and increase off-state current. Body contact can be used to suppress the floating body effect. However, body contact can increase channel thickness and degrade device performance, such as short-channel control. It is currently difficult to fabricate high-quality body contact on vertical devices. SUMMARY

[0004] In view of the above, it is at least in part an object of the present disclosure to provide a ring-gate or multi-gate vertical semiconductor device with body contact and a method of manufacturing the same, and an electronic device including the same.

[0005] According to an aspect of the present disclosure, there is provided a semiconductor device, comprising: an active region vertically disposed on a substrate with respect to the substrate, including a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region to define a channel region; a first gate stack and a second gate stack disposed on first and second sides of the active region opposite to each other in a lateral direction with respect to the substrate; and a body contact layer disposed on the second side of the active region to overlap with a portion of the middle portion of the active region to apply a body bias to the active region, wherein the second gate stack includes a first portion under the body contact layer and a second portion above the body contact layer.

[0006] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a stack of a first source / drain definition layer, a first channel definition layer, a body contact definition layer, a second channel definition layer, and a second source / drain definition layer on a substrate; forming an active layer on vertical sidewalls of the stack extending in a first direction; driving dopants in the first source / drain definition layer, dopants in the body contact definition layer, and dopants in the second source / drain definition layer into respective portions of the active layer to form a lower source / drain region, a body contact region, and an upper source / drain region, respectively; forming an isolation layer surrounding the stack; removing the first channel definition layer and the second channel definition layer; forming a gate stack on the isolation layer, the gate stack including a first gate stack and a second gate stack on a first side and a second side opposite to each other in a second direction intersecting the first direction, the second gate stack entering spaces between the first source / drain definition layer and the body contact definition layer and between the body contact definition layer and the second source / drain definition layer; and forming a body contact to the body contact definition layer.

[0007] According to another aspect of the present disclosure, there is provided an electronic device including the above semiconductor device.

[0008] According to embodiments of the present disclosure, a body contact is provided for a vertical semiconductor device, so that a floating body effect can be suppressed. In addition, due to the configuration of a ring gate or a multi-gate, gate control over a channel can be improved, and device performance (e.g., on-state current, etc.) can be enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 13(c) Schematic diagrams showing some stages in a flow of manufacturing a semiconductor device according to embodiments of the present disclosure are shown;

[0011] Figures 14(a) to 18(c) Schematic diagrams showing some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure are shown;

[0012] Figures 19 to 23(c) Schematic diagrams showing some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure are shown;

[0013] Figures 24(a) to 25(b) Schematic diagrams showing some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure are shown.

[0014] Throughout the drawings, same or similar reference numerals can represent same or similar functions in case of same or similar components. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary for the purpose of illustration and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0016] In the drawings, various structural diagrams according to embodiments of the present disclosure are illustrated. These diagrams are not drawn to scale in which certain details are exaggerated for the purpose of clarity and can omit certain details. The shapes of various regions, layers, and the relative size and positional relationship therebetween shown in the drawings are merely exemplary, and in actuality, can be deviated due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers having different shapes, sizes, and relative positions as needed.

[0017] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0018] According to embodiments of the present disclosure, a ring-gate or multi-gate vertical type semiconductor device having a body contact is provided. The vertical type device can include an active region disposed vertically (e.g., in a direction substantially perpendicular to a surface of a substrate) with respect to the substrate, including a lower source / drain region disposed at a lower end and an upper source / drain region disposed at an upper end. A middle portion of the active region between the lower source / drain region and the upper source / drain region can define a channel region. The lower source / drain region and the upper source / drain region can be electrically communicated with each other through the channel region. The lower source / drain region and the upper source / drain region can be defined by a doped region. The channel region can also be doped as needed.

[0019] A gate stack can be disposed to overlap the middle portion (or, the channel region) of the active region so as to control on / off of a conduction path in the channel region. The gate stack can include a first gate stack and a second gate stack disposed on a first side and a second side of the active region opposite to each other in a lateral direction (a direction substantially parallel to the surface of the substrate).

[0020] For optimization of device performance, the gate stack can have different configurations.

[0021] For example, the gate stack can have a gate-all-around (GAA) configuration, i.e., the gate stack including the first gate stack and the second gate stack can surround an outer periphery of the active region (particularly, the channel region). In this case, the first gate stack and the second gate stack can be portions of the same gate stack on the first side and the second side of the active region, respectively.

[0022] For another example, the first gate stack and the second gate stack can be electrically isolated from each other (e.g. by a dielectric layer in between), thereby forming a multi-gate configuration. The first gate stack and the second gate stack, which are isolated from each other, can be used for different purposes, e.g. one of them like the first gate stack can be used as a control gate, while the other like the second gate stack can be used for controlling threshold voltage (Vt). The first gate stack and the second gate stack can have different characteristics from each other, e.g. (effective) work function.

[0023] Such a ring gate or multi-gate configuration can improve the gate control over the channel, and enhance the device performance.

[0024] On the second side of the active region, a body contact layer can be provided. The body contact layer can overlap with the middle portion (or in other words, the body portion) of the active region, so as to apply a body bias to the active region, and thus control the floating body effect.

[0025] The active region, in particular the middle portion thereof, can be provided with a doped region as a body contact region, through which the body contact layer applies the body bias to the active region. Such a body contact region can only occupy a part of the range of the middle portion of the active region in the vertical direction, and thus can have different doping characteristics from the rest of the middle portion of the active region. For example, the rest of the middle portion of the active region can be not intentionally doped, or have a different doping concentration. As described below, the body contact region can be self-aligned to the body contact layer. For example, the body contact region can be formed by driving dopants into the active region (substantially laterally) from the body contact layer.

[0026] The spaced distance of the body contact layer (and thus the body contact region) from the lower source / drain region and the upper source / drain region in the vertical direction can be adjusted as desired, e.g. substantially the same, or biased towards the lower source / drain region or the upper source / drain region. As described below, such distance adjustment can be achieved by the film thickness of the epitaxial semiconductor layer, and thus the film thickness precision of the epitaxial growth process can be reached.

[0027] The second gate stack can include a first portion below the body contact layer and a second portion above the body contact layer. Specifically, the first portion of the second gate stack can overlap with the middle portion (or in other words, the channel region) of the active region in the region between the body contact layer (or in other words, the body contact region) and the lower source / drain region, and the second portion can overlap with the middle portion (or in other words, the channel region) of the active region in the region between the body contact layer (or in other words, the body contact region) and the upper source / drain region. Thus, on the second side, the middle portion (or in other words, the channel region) of the active region can on one hand receive the body bias applied by the body contact layer in the middle, and thus the floating body effect can be reduced; on the other hand, it can be controlled by the first portion and the second portion of the second gate stack below and above the body contact layer respectively, and thus the device performance, e.g. Vt adjustment, gate-induced drain leakage (GIDL) control, etc. can be optimized.

[0028] The first and second portions of the second gate stack can be portions of the same gate stack below and above the body contact layer, respectively, which can extend continuously (bypassing the body contact layer). Alternatively, the first and second portions of the second gate stack can be portions formed to have different characteristics such as (effective) work functions, respectively.

[0029] The first and second portions of the second gate stack can receive the same bias; or can be electrically isolated from each other, and thus can receive different biases. In addition, the second portion (and optionally, the first portion) of the second gate stack can also receive the same bias as the body contact layer.

[0030] Thus, a variety of different gate control schemes can be provided: the first and second gate stacks receive the same gate control voltage (particularly in the case of a ring gate configuration); the first gate stack receives a first gate control voltage, while the second gate stack including the first and second portions receives a second gate control voltage applied separately from the first gate control voltage; the first gate stack receives a first gate control voltage, while the first and second portions of the second gate stack can receive a second gate control voltage and a third gate control voltage applied separately from each other.

[0031] The body contact layer can laterally extend so as to enable a body contact portion for applying a body bias to be landed thereon.

[0032] Similarly, an upper source / drain region contact layer can be provided at the second side of the active region in contact with the upper source / drain region. The upper source / drain region contact layer can laterally extend so as to enable an upper source / drain region contact portion for applying / outputting an electrical signal to / from the upper source / drain region to be landed thereon. As will be described below, the upper source / drain region can be self-aligned to the upper source / drain region contact layer. For example, the upper source / drain region can be formed by implanting dopants (substantially laterally) from the upper source / drain region contact layer into the active region.

[0033] The spacing between the upper source / drain region contact layer and the body contact layer in the vertical direction can be substantially uniform. As will be described below, this spacing can be achieved by the film thickness of the epitaxial semiconductor layer, and thus can reach the film thickness precision of the epitaxial growth process.

[0034] The active region can be provided by an active layer of semiconductor. The active layer can be in the form of a nanosheet or a nanowire, and can include a vertically extending portion extending in the vertical direction to provide the vertically active region described above. In addition, the active layer can also include a laterally extending portion extending away from the vertically extending portion at the first side from the lower end of the vertically extending portion (more particularly, the lower source / drain region). Such a laterally extending portion facilitates the formation of a lower source / drain region contact portion to the lower source / drain region. For example, the laterally extending portion of the active layer can extend beyond the gate stack above, on which the lower source / drain region contact portion can be landed.

[0035] The active layer can be formed on the lower source / drain region-defining layer. The lower source / drain region-defining layer can extend from under the laterally extending portion of the active layer to the surface of the vertically extending portion of the active layer on the second side. As described below, the lower source / drain region can be self-aligned to the portion of the lower source / drain region-defining layer on the second side. For example, the lower source / drain region can be formed by implanting dopants from the lower source / drain region-defining layer into the active layer.

[0036] The spacing between the lower source / drain region-defining layer and the body contact layer in the vertical direction can be substantially uniform. As described below, this spacing can be achieved by the film thickness of the epitaxial semiconductor layer, and thus the film thickness accuracy of the epitaxial growth process can be achieved.

[0037] The active layer can be an epitaxial layer on the lower source / drain region-defining layer, the body contact layer, and the upper source / drain contact layer, and thus can have a crystal interface with each of the lower source / drain region-defining layer, the body contact layer, and the upper source / drain contact layer. Each of these layers can be a single-crystal semiconductor.

[0038] According to embodiments, such a vertical-type semiconductor device can be manufactured as follows.

[0039] A stack of a first source / drain-defining layer, a first channel-defining layer, a body contact-defining layer, a second channel-defining layer, and a second source / drain-defining layer can be provided on the substrate. This stack can be formed by epitaxial growth. Thus, the thickness of each layer in the stack can be well controlled. Each layer in the stack can be doped in situ while being grown, in order to achieve the desired doping characteristics. For example, the first source / drain-defining layer and the second source / drain-defining layer can be heavily doped to achieve source / drain regions; the body contact-defining layer can be lightly doped to achieve a body contact region; and the first channel-defining layer and the second channel-defining layer can be lightly doped or not intentionally doped. There can be a crystal plane / doping interface between each of the grown / doped layers.

[0040] The stack can have a vertical sidewall extending in the first direction. On this vertical sidewall, an active layer to define an active region can be formed. The active layer can be formed by epitaxial growth, and thus its thickness and the thickness of the channel region defined thereby can be well controlled. In addition, the material of the active layer can be appropriately selected depending on the application. Since the following processes, particularly the etching process, are mainly performed on the above-described stack, the selection of the active layer material can be less restricted.

[0041] The dopants in the first source / drain-defining layer, the dopants in the body contact-defining layer, and the dopants in the second source / drain-defining layer can be implanted into the respective portions of the active layer by, for example, heat treatment, to form a lower source / drain region, a body contact region, and an upper source / drain region, respectively. The lower source / drain region, the body contact region, and the upper source / drain region thus formed can be self-aligned to the first source / drain-defining layer, the body contact-defining layer, and the second source / drain-defining layer, respectively.

[0042] An isolation layer can be formed around the above stack, and a gate stack can be formed on the isolation layer after the first and second channel-defining layers are removed. The gate stack can thus include a first gate stack and a second gate stack on first and second sides opposite each other in a second direction intersecting (e.g., perpendicular to) the first direction. The gate stack can overlap the channel region to effectively control the channel region.

[0043] The isolation layer can have a substantially planar top surface, so that the gate stack formed on the isolation layer can extend continuously around the outer periphery of the active region, resulting in a GAA configuration. Alternatively, the isolation layer can have protruding portions on opposite sides of the above stack in the first direction, so that the gate stack formed on the isolation layer can be electrically isolated from each other by the protruding portions, resulting in a multi-gate configuration.

[0044] In addition, the gate stack can be formed in a self-aligned process. For example, the first and second channel-defining layers can be recessed opposite each other at the vertical sidewalls by selective etching to define a space to accommodate (at least part of) the gate stack, before the active layer is formed. A dummy gate can be formed to maintain the space thus defined.

[0045] On the second side of the active layer, i.e., the side on which the above stack is located, some contacts can be made, such as an upper source / drain contact to the upper source / drain region, a body contact to the body contact region, a contact to the second gate stack (and optionally, a contact to a well region in the substrate).

[0046] The present disclosure can be presented in various forms, some examples of which will be described below. In the following description, the selection of various materials is addressed. The selection of materials is considered in addition to their functionality (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) to etch selectivity. In the following description, the required etch selectivity can or can not be indicated. It will be apparent to those skilled in the art that when etching of a material layer is mentioned below, if it is not mentioned that other layers are also etched or if the figure does not show that other layers are also etched, then such etching can be selective and the material layer can have etch selectivity with respect to other layers exposed to the same etch recipe.

[0047] Figures 1 to 13(c) Schematic diagrams showing some stages in a flow of fabricating a semiconductor device according to embodiments of the present disclosure are shown.

[0048] As Figure 1As shown, a substrate 1001 is provided. The substrate 1001 can be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, etc. In the following description, bulk Si substrates such as Si wafers are used as examples for convenience of illustration.

[0049] In the substrate 1001, a well region 1001w can be formed by, for example, ion implantation. The well region 1001w can contain dopants of a certain conductivity type (e.g., p-type for n-type devices, n-type for p-type devices) and a certain concentration such as about 1E17-1E19 cm -3 Various ways exist in the art to provide such well regions, which are not described here again.

[0050] On the substrate 1001, a first source / drain definition layer 1003, a first channel layer definition 1005, a body contact definition layer 1007, a second channel definition layer 1009, and a second source / drain definition layer 1011 can be formed in sequence by, for example, epitaxial growth. The layers grown on the substrate 1001 can be single-crystalline semiconductor layers, and can have crystal interfaces with each other.

[0051] The first source / drain definition layer 1003 and the second source / drain definition layer 1011 can then define the locations of source / drain regions, and their respective thicknesses can be, for example, about 20 nm-200 nm. The first source / drain definition layer 1003 and the second source / drain definition layer 1011 can be doped with dopants of a certain conductivity type (e.g., n-type for n-type devices, p-type for p-type devices) and a certain concentration such as about 1E18-1E21 cm -3 .

[0052] The body contact definition layer 1007 can then define the location of a body contact, and its thickness can be, for example, about 2 nm-100 nm. To optimize device performance such as adjusting threshold voltage (Vt), the body contact definition layer 1007 can be doped with dopants of a certain conductivity type (e.g., p-type for n-type devices, n-type for p-type devices) and a certain concentration such as about 1E17-1E20 cm -3 .

[0053] The first channel layer definition 1005 and the second channel definition layer 1009 can then define the locations of channel regions together with the body contact definition layer 1007, and their respective thicknesses can be, for example, about 5 nm-50 nm. To optimize device performance such as adjusting Vt, at least one of the first channel layer definition 1005 and the second channel definition layer 1009 can be doped by, for example, in-situ doping during growth.

[0054] Because each layer is doped separately, there can be doping concentration interfaces between them.

[0055] The first source / drain defining layer 1003, the first channel layer defining layer 1005, the bulk contact defining layer 1007, the second channel layer defining layer 1009, and the second source / drain defining layer 1011 may comprise various suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. To provide appropriate etching selectivity in subsequent processes, there may be etching selectivity between adjacent layers. For example, in the case where the substrate 1001 is a Si wafer, the first source / drain defining layer 1003, the bulk contact defining layer 1007, and the second source / drain defining layer 1011 may comprise Si, while the first channel layer defining layer 1005 and the second channel layer defining layer 1009 may comprise SiGe (e.g., the atomic percentage of Ge is about 10%-30%).

[0056] For ease of composition, such as Figure 2 As shown, an etch stop layer 1013, a mandrel layer 1015, and a hard mask layer 1017 can be sequentially formed on the aforementioned semiconductor layer stack, for example, by deposition. For example, the etch stop layer 1013 may include an oxide (e.g., silicon oxide) with a thickness of about 2 nm to 15 nm; the mandrel layer 1015 may include amorphous silicon or polycrystalline silicon with a thickness of about 50 nm to 200 nm; and the hard mask layer 1017 may include a nitride (e.g., silicon nitride) with a thickness of about 20 nm to 100 nm.

[0057] Photoresist (not shown) can be formed on the hard mask layer 1017 and patterned by photolithography to have a shape along a first direction ( Figure 2 Vertical sidewalls extending in a direction perpendicular to the plane of the paper. A patternable photoresist is used as an etching mask. The hard mask layer 1017 and the core mold layer 1015 are selectively etched sequentially by, for example, reactive ion etching (RIE), transferring the photoresist pattern into the hard mask layer 1017 and the core mold layer 1015. RIE can be performed in a vertical direction. Etching can stop at an etch stop layer 1011. Afterwards, the photoresist can be removed. Thus, the core mold layer 1015 (and the hard mask layer 1017) can have vertical sidewalls extending in a first direction.

[0058] On the sidewall, a spacer 1019 can be formed. For example, a layer of nitride with a thickness of about 5 nm to 50 nm can be deposited in a substantially conformal manner, and then anisotropic etching such as RIE can be performed on the deposited nitride layer in the vertical direction (which can stop at the etch stop layer 1013) to remove the laterally extending portion thereof and leave the vertically extending portion thereof, thereby resulting in the spacer 1019. The spacer 1019 can then be used to at least partially define the dimensions of the upper source / drain region contact layer.

[0059] In Figure 2 For convenience, the curved shape of the top end of the spacer 1019 due to RIE is not shown. Such curved shape, if present, does not affect the subsequent processes. The same applies to the spacers shown in the following figures.

[0060] As shown in FIG. 3(a), the spacer 1019 and the hard mask layer 1017 can be used as etching masks to selectively etch (the etch stop layer 1013 and) the second source / drain-defining layer 1011, the second channel-defining layer 1009, the body contact-defining layer 1007, the first channel layer-defining 1005, and the first source / drain-defining layer 1003 in sequence by, for example, RIE, so that the semiconductor layer stack can have vertical sidewalls extending in the first direction as active layer growth surfaces. The RIE can be performed in the vertical direction and can stop within the first source / drain-defining layer 1003 without reaching the bottom surface of the first source / drain-defining layer 1003.

[0061] On the vertical sidewalls of the semiconductor layer stack, an active layer 1021 can be formed by, for example, selective epitaxial growth. The active layer 1021 can include various suitable semiconductor materials, such as elemental semiconductor materials like Si, compound semiconductor materials like III-V compound semiconductors, SiC, etc. The active layer 1021 can then define a channel region with a thickness of, for example, about 3 nm to 20 nm. According to embodiments of the present disclosure, the thickness of the active layer 1021 (and thus, the channel region) can be determined by the epitaxial growth process, and thus the thickness of the channel region can be better controlled and the fluctuation of the thickness can be reduced.

[0062] Dopants can be driven from the first source / drain-defining layer 1003 and the second source / drain-defining layer 1011 into the active layer 1021 by annealing to form lower source / drain regions S / D L and upper source / drain regions S / D Udopants, if present, from the body contact defining layer 1017 into the active layer 1021 to form a doped region as a body contact region BD in the active layer 1021 in a region corresponding to the body contact defining layer 1017. In addition, if dopants are also present in the first channel defining layer 1005 and / or the second channel defining layer 1009, these dopants can also be driven into the corresponding regions in the active layer 1021 in the annealing process.

[0063] Here, the conditions of the annealing process (e.g., annealing time) can be controlled such that the degree of diffusion of dopants from the first source / drain defining layer 1003, the second source / drain defining layer 1011 and the body contact defining layer 1017 into the active layer 1021 can be comparable to the thickness of the active layer 1021. In this way, the lower source / drain region S / D L , the body contact region BD and the upper source / drain region S / D U may be defined by the first source / drain defining layer 1003, the body contact defining layer 1007 and the second source / drain defining layer 1011, respectively. Accordingly, the location of the channel region between the lower source / drain region S / D L and the upper source / drain region S / D U may be defined by the first channel defining layer 1005, the body contact defining layer 1007 and the second channel defining layer 1009. That is, the length of the channel region can be determined by the thickness of the first channel defining layer 1005, the body contact defining layer 1007 and the second channel defining layer 1009, and the thickness of the first channel defining layer 1005, the body contact defining layer 1007 and the second channel defining layer 1009 can be determined by the epitaxial growth process, and thus the length of the channel region can be better controlled.

[0064] In this example, the upper source / drain region S / D U and the lower source / drain region S / D L may have the same conductivity type, and the body contact region BD can have a different conductivity type. However, the present disclosure is not limited thereto. For example, the upper source / drain region S / D U and the lower source / drain region S / D L may have different conductivity types (and thus a tunneling type device can be formed, for example), and the body contact region BD can have a different conductivity type from one of them.

[0065] In FIG. 3(a), the lower source / drain region S / D L , the body contact region BD and the upper source / drain region S / D U are shown in shadow for ease of understanding. In the following figures, these doped regions are not shown separately for the sake of convenience and clarity.

[0066] According to embodiments of the present disclosure, the size and relative position of the body contact region BD in the vertical direction can be adjusted by controlling the thickness of at least one of the first channel confinement layer 1005, the body contact confinement layer 1007, and the second channel confinement layer 1009. For example, in the case where the thicknesses of the first channel confinement layer 1005 and the second channel confinement layer 1009 are substantially the same, the body contact region BD can be located substantially in the middle of the channel region in the vertical direction. Alternatively, in the case where the thicknesses of the first channel confinement layer 1005 and the second channel confinement layer 1009 are different from each other, the body contact region BD can be located closer to the lower source / drain region S / D L (For example, in the case where the first channel confinement layer 1005 is thinner than the second channel confinement layer 1009) or the upper source / drain region S / D U (For example, in the case where the first channel confinement layer 1005 is thicker than the second channel confinement layer 1009).

[0067] In this example, the first source / drain confinement layer 1003 has a portion extending beyond the area defined by the sidewall 1019 and the hard mask layer 1017, and thus the active layer 1021 is also grown on this portion to have a laterally extending portion. This laterally extending portion of the active layer 1021 is doped due to the diffusion of dopants in the underlying first source / drain confinement layer 1003 during the annealing process, and thus can serve as a portion of the lower source / drain region S / D L . This laterally extending portion of the lower source / drain region S / D L facilitates the landing of the subsequently formed contact to the lower source / drain region S / D L .

[0068] According to another embodiment of the present disclosure, to achieve a self-aligned gate, as shown in FIG. 3(b), after the vertical sidewalls are patterned in the semiconductor layer stack using the sidewall 1019 and the hard mask layer 1017 as described above in connection with FIG. 3(a), the first channel layer confinement 1005 and the second channel layer confinement 1009 can be laterally recessed relative to each other by selective etching. To control the etching depth, atomic layer etching (ALE) can be employed.

[0069] Here, due to the etching selectivity, the body contact confinement layer 1007 protrudes relative to the first channel layer confinement 1005 and the second channel layer confinement 1009. However, the present disclosure is not limited thereto. For example, by selecting appropriate materials, an etching recipe can be employed that can selectively etch the first channel layer confinement 1005 and the second channel layer confinement 1009 as well as the body contact confinement layer 1007 (relative to the first source / drain confinement layer 1003 and the second source / drain confinement layer 1011) such that the first channel layer confinement 1005 and the second channel layer confinement 1009 as well as the body contact confinement layer 1007 can all be recessed, thereby defining a space for the gate stack.

[0070] Thereafter, the active layer 1021' can be similarly grown and doped with dopants. With regard to the active layer 1021' and dopant implantation, reference can be made to the above description with regard to the active layer 1021 and dopant implantation, except that the active layer 1021' can take a curved shape due to the relative recessing of the first channel-defining layer 1005 and the second channel-defining layer 1009.

[0071] In the recessing of the ends of the first channel-defining layer 1005 and the second channel-defining layer 1009 (and optionally, the body-contact-defining layer 1007), as shown in Figure 4 The dummy gate 1023 can be formed by, for example, deposition and vertical RIE. The dummy gate 1023 can include, for example, SiC, taking into account etch selectivity.

[0072] Hereinafter, the embodiment of Fig. 3(a) will be mainly described as an example. The descriptions are generally applicable to the embodiment of Fig. 3(b) as well, and separate descriptions with regard to the embodiment of Fig. 3(b) will be provided when necessary.

[0073] As shown in Figure 5(a) and 5(b) The masking layer 1025 can be formed to mask the active layer 1021, 1021'. For example, the masking layer 1025 can be formed by depositing an oxide layer to completely cover the structures already formed on the substrate 1001, and planarizing the deposited oxide layer, such as chemical mechanical polishing (CMP, which can be stopped on the nitride hard mask layer 1017 and / or the sidewall 1019). The masking layer 1025 can be formed by depositing an oxide layer to completely cover the structures already formed on the substrate 1001, and planarizing the deposited oxide layer, such as chemical mechanical polishing (CMP, which can be stopped on the nitride hard mask layer 1017 and / or the sidewall 1019).

[0074] With the active layer 1021, 1021' masked by the masking layer 1025, the above-described semiconductor layer stack can be patterned, so that landing pads for some contacts can be defined on one side (the right side in the figure) of the active layer 1021, 1021'. For example, the hard mask layer 1017 can be removed by selective etching, such as vertical RIE, to expose the template layer 1015. Here, the sidewall 1019, which is also nitride as the hard mask layer 1017, can be preserved due to its thickness. The template layer 1015 and the etch stop layer 1013 can be sequentially removed by selective etching, such as vertical RIE, to expose the second source / drain-defining layer 1011. Here, the remaining portion of the etch stop layer 1013 is shown as integral with the masking layer 1025, which is also oxide.

[0075] In this way, on this side (the right side in the figure) of the active layer 1021, 1021', the semiconductor layer stack is exposed for patterning.

[0076] Here, the side wall 1019 covers a portion of the second source / drain definition layer 1011, and the portion of the second source / drain definition layer 1011 covered by the side wall 1019 can define a landing pad for a contact to the upper source / drain region S / D U .

[0077] Next, a landing pad for a contact to the body contact region BD can be defined.

[0078] For example, as shown in FIG. 10(b), the side wall 1019 can be used as an etch mask to sequentially etch the second source / drain definition layer 1011 and the second channel definition layer 1009 by, for example, RIE in the vertical direction, to expose the body contact definition layer 1007. Thus, the body contact definition layer 1007 can protrude relative to the second source / drain definition layer 1011 above, and the protruding portion can define a landing pad for a contact to the body contact region BD. Figure 6 According to some embodiments, a contact to the well region 1001w in the substrate 1001 can also be made. In this case, to expose the well region 1001w below, a side wall 1027 can be formed on the body contact definition layer 1007 to define a landing pad for a contact to the body contact region BD, similar to the landing pad for a contact to the upper source / drain region S / D U as described above for the side wall 1019. The side wall 1027 can include SiC, taking into account the etch selectivity. The portion of the body contact definition layer 1007 covered by the side wall 1027 can define a landing pad for a contact to the body contact region BD.

[0079] Then, as shown in FIG. 10(c), the side wall 1027 (and the side wall 1019 and the masking layer 1025) can be used as an etch mask to sequentially etch the body contact definition layer 1007, the first channel definition layer 1005, and the first source / drain definition layer 1003 by, for example, RIE in the vertical direction, to expose the well region 1001w. In this example, since both the first source / drain definition layer 1003 and the substrate 1001 include Si, the etching of the first source / drain definition layer 1003 can proceed into the well region 1001w. Thereafter, the side wall 1027 can be removed by selective etching.

[0080] Figure 7 Additionally, to reduce contact resistance, vertical ion implantation and annealing can be performed to form relatively highly doped (of the same conductivity type as the body contact definition layer 1007 and the well region 1001w) contact regions in the body contact definition layer 1007 and the well region 1001w, respectively (see 1029 and 1031 in FIG. 8(b)).

[0081] Additionally, to reduce contact resistance, vertical ion implantation and annealing can be performed to form relatively highly doped (of the same conductivity type as the body contact definition layer 1007 and the well region 1001w) contact regions in the body contact definition layer 1007 and the well region 1001w, respectively (see 1029 and 1031 in FIG. 8(b)).

[0082] ​Thus, the semiconductor stack and the active layer 1021 formed on its vertical sidewalls can extend continuously in the first direction. They can be patterned into different segments for individual devices.

[0083] like Figure 8(a) , 8(b) As shown in 8(c), an oxide layer completely covering the structure formed on the substrate 1001 can be formed on the substrate 1001 by deposition, and the deposited oxide layer is planarized, such as by CMP (CMP can stop at the nitride sidewall 1019). Thus, oxide layers are formed on opposite sides (left and right sides in the figure) of the semiconductor layer stack extending along the first direction and the active layer 1021 (the left side is the previously formed shielding layer 1025, and the right side is the newly deposited oxide layer). The oxide layer is then etched back and forth by, for example, a vertical RIE to form an isolation layer 1033. The thickness of the isolation layer 1033 is such that the area of ​​the channel region in the active layer 1021 (i.e., the area corresponding to the first channel defining layer 1005, the body contact defining layer 1007, and the second channel defining layer 1009) can be exposed. For example, the top surface of the isolation layer 1033 may not be higher than, preferably (slightly) lower than, the bottom surface of the first channel defining layer 1005.

[0084] Photoresist 1035 can be formed on the isolation layer 1033 and patterned as strips extending along a second direction (e.g., a horizontal direction in the plane of the paper in the top view of FIG. 8(a)) that intersects (e.g., is perpendicular to) the first direction (vertical direction in the plane of the paper in the top view of FIG. 8(a)). Based on the photoresist 1035, the semiconductor stack and active layer 1021 can be cut into different segments separated in the first direction (only one segment is shown in the figure, i.e., the segment covered by photoresist 1035) by, for example, a vertical RIE, in order to define the active regions of different devices. The RIE can be performed into the substrate 1001. Afterwards, the photoresist 1035 can be removed.

[0085] In the top view of Figure 8(a), the cut-off points of the cross-sectional views in the other figures, lines AA′ and BB′, are also schematically shown.

[0086] Furthermore, an isolation layer 1033 exists on both sides of each segment. In the grooves formed by the cutting (the areas cut between segments, see Figure 8(c)), a dielectric material such as an oxide can also be formed, thus forming an isolation layer surrounding each segment together with the isolation layer 1033. For example, as... Figure 9(a) and 9(b)As shown, the isolation layer 1033' can be formed in a manner similar to that used to form the isolation layer 1033, by depositing, planarizing, and etching back oxide. Here, the isolation layer surrounding each section (including the remaining portion of the previously formed isolation layer 1033) is shown together as 1033'. Similarly, the thickness of the isolation layer 1033' allows the channel region in the active layer 1021 to be exposed; for example, the top surface of the isolation layer 1033' may not be higher than, and preferably (slightly) lower than, the bottom surface of the first channel defining layer 1005.

[0087] In this example, each segment protrudes relative to the surrounding isolation layer 1033', so that the gate stack subsequently formed on the isolation layer 1033' can surround the outer periphery of each segment (particularly the channel region therein), thus obtaining a GAA configuration.

[0088] Figure 10 It shows in Figure 3(b) and 4 The isolation layer 1033' is shown in the embodiment. In this case, the top surface of the isolation layer 1033' can be higher than the bottom surface of the first channel defining layer 1005. This is because the presence of the dummy gate 1023 prevents the lower end of the channel region from being blocked by the isolation layer 1033' (although its top surface is higher).

[0089] As shown in Figure 11(a), the first channel defining layer 1005 and the second channel defining layer 1009 can be removed by selective etching. This exposes the active layer 1021 on the right side as well. A gate stack can be formed on the isolation layer 1033'. The gate stack can include a gate dielectric layer 1039 and a gate conductor layer 1041. For example, the gate dielectric layer 1039 can include a high-k dielectric (such as HfO2) layer with a thickness of about 1 nm to 10 nm formed, for example, by deposition. The gate dielectric layer 1039 can be formed in a generally conformal manner. Before forming the gate dielectric layer 1039, a thin interface layer, such as an oxide of about 0.3 nm to 2 nm, can also be formed, for example, by oxidation or deposition. The gate conductor layer 1041 can include a work function layer such as TiN, TiAlN, Zr-, Ru-, or La-containing materials, and may also include a conductive material layer such as W, as needed. The gate conductor layer 1041 can be etched back so that its top surface can be higher than the bottom surface of the second source / drain defining layer 1011 to ensure overlap with the channel region (but should not be too high to reduce the upper source / drain region S / D corresponding to the second source / drain defining layer 1011). U (overlapping).

[0090] The resulting gate stack (1039 / 1041) is not self-aligned and therefore may be inconsistent with the lower source / drain S / D ratio. L and / or source / drain S / D U There is some overlap.

[0091] While in the above embodiments the gate stack is self-aligned to the channel region in the active layer 1021, in other embodiments the gate stack can be self-aligned to the channel region in the active layer 1021' as well. For example, as shown in FIG. 11(b), the gate stack (1039 / 1041) formed on the isolation layer 1033' can enter into the space previously occupied by the dummy gate 1023, thereby overlapping with the channel region in the active layer 1021'. Figure 3(b) And 4 In another embodiment as described above, the gate stack can be self-aligned to the channel region in the active layer 1021'. For example, as shown in FIG. 11(b), the gate stack (1039 / 1041) formed on the isolation layer 1033' can enter into the space previously occupied by the dummy gate 1023, thereby overlapping with the channel region in the active layer 1021'.

[0092] In this example, the gate conductor layer 1041 can be etched back so that its top surface is lower than the bottom surface of the second source / drain defining layer 1011, and in addition due to the arrangement of the top surface of the isolation layer 1033' as described above, the end of the gate stack close to the active layer 1021' is defined by the dummy gate 1023, and the location of the dummy gate 1023 is defined by the first channel-defining layer 1005 and the second channel-defining layer 1009 themselves, thus the gate stack can be self-aligned to the channel region in the active layer 1021'.

[0093] Next, various contacts can be made. According to embodiments of the present disclosure, in addition to making contacts to the source / drain regions and the gate stack of the device, contacts to the body contact regions can also be made.

[0094] At this point, the gate stack is exposed. The gate stack (and in particular the gate conductor layer therein) can be suitably patterned so as not to affect the formation of other contacts. For example, on the left side, the gate conductor layer can be suitably recessed so as not to interfere with the subsequent formation of contacts to the first source / drain defining layer 1003; on the right side, the gate conductor layer can be suitably recessed so as not to interfere with the subsequent formation of contacts to the body contact-defining layer 1017.

[0095] For example, as shown in FIG. 12(a), a photoresist 1049 can be formed on the gate conductor layer, and patterned so as to surround the outer periphery of the channel region (as schematically shown by the relatively smaller dashed rectangular box in FIG. 12(a) in plan view). In addition, the right side boundary of the photoresist 1049 in plan view can be shifted leftward relative to the right side boundary of the sidewall 1019, so as to utilize the sidewall 1019 (the portion thereof not overlapping with the photoresist 1049) as a (partial) etch mask. In this way, in plan view, the landing pad of the contact to the body contact region BD in the body contact-defining layer 1007 previously defined by the sidewall 1027 (as schematically shown by the dashed rectangular box outside of the photoresist 1049 in FIG. 12(a)) can not overlap with the photoresist 1049. Figure 12(a) And 12(b) For example, as shown in FIG. 12(a), a photoresist 1049 can be formed on the gate conductor layer, and patterned so as to surround the outer periphery of the channel region (as schematically shown by the relatively smaller dashed rectangular box in FIG. 12(a) in plan view). In addition, the right side boundary of the photoresist 1049 in plan view can be shifted leftward relative to the right side boundary of the sidewall 1019, so as to utilize the sidewall 1019 (the portion thereof not overlapping with the photoresist 1049) as a (partial) etch mask. In this way, in plan view, the landing pad of the contact to the body contact region BD in the body contact-defining layer 1007 previously defined by the sidewall 1027 (as schematically shown by the dashed rectangular box outside of the photoresist 1049 in FIG. 12(a)) can not overlap with the photoresist 1049.

[0096] Using the photoresist 1049 and the sidewall 1019 as described above as an etching mask, the gate conductor layer 1041 is etched by selective etching, such as vertical RIEs. Etching of the gate conductor layer 1041 can stop at the gate dielectric layer 1039. Thus, the gate conductor layer 1041 can be formed in a shape surrounding the active layer 1021 (particularly the channel region therein), and a GAA configuration can be obtained. Furthermore, the gate conductor layer 1041 can be removed from the portion of the contact pad in the body contact defining layer 1017 used to define the contact portion to the body contact region BD. Afterwards, the photoresist 1049 can be removed.

[0097] In the top view of Figure 12(a), for convenience, the undulations that the gate dielectric layer 1039 may have due to the undulations of the underlying structure are not shown. The same is true in the subsequent top views.

[0098] like Figure 13(a) and 13(b) As shown, an interlayer dielectric layer 1051 can be formed on a substrate. For example, an oxide layer that completely covers the structure formed on the substrate 1001 can be formed by deposition, and the deposited oxide layer can be planarized, such as by CMP (CMP can stop at the nitride sidewalls 1019), to form the interlayer dielectric layer 1051.

[0099] In the interlayer dielectric layer 1051, S / D to the lower source / drain region can be formed. L Contact part 1053 L , to the source / leakage area S / D U Contact part 1053 U , Contact portion 1053 of the body contact area BD BD Contact 1053 to the gate stack (specifically, gate conductor layer 1041) G and the contact portion 1053 to the well area 1001w W . Contact Department 1053 L It is attached to the portion of the first source / drain defining layer 1003 that extends relative to the upper conductive layer (e.g., gate conductor layer 1041). Contact portion 1053 U It is attached to the second source / drain limiting layer 1011 (the portion defined by the sidewall 1019) (the second source / drain limiting layer 1011 realizes the contact portion 1053) U To the source / leakage zone S / D U The electrical contact, and therefore can be called the upper source / drain contact layer). Contact portion 1053 BD It is attached to the body contact limiting layer 1007 (the portion defined by the side wall 1027) (the body contact limiting layer 1007 realizes the contact portion 1053) BDThis is a body contact to the active region, and therefore can be called a body contact layer. Here, since it is a GAA configuration, a single contact 1053 is configured for one device to the gate conductor layer 1041. c These contacts can be formed by etching holes in the interlayer dielectric layer 1051 and filling the holes with a conductive material such as metal.

[0100] like Figure 13(a) and 13(b) As shown, the semiconductor device according to this embodiment may include a vertical active region defined by the active layer 1021. The vertical active region may include a lower source / drain region S / D. L Source / Drain S / D U And the channel regions between them. The thickness and length of the channel regions, as described above, can be controlled by epitaxial growth, which can achieve control precision even at the single-atom-layer level.

[0101] A volume contact area BD may be present in the channel region. The volume contact area BD may occupy only a portion of the channel region in the vertical direction. As mentioned above, the volume contact area BD may be located substantially in the middle of the channel region in the vertical direction, or it may be offset towards the lower source / drain region S / D. L or source / leakage S / D U It can be achieved through contact part 1053 BD A volume bias is applied to the active region (via the volume contact region BD) to reduce the buoyancy effect. The position and size of the volume contact region BD in the vertical direction can be controlled by epitaxial growth, which can achieve control precision even at the single-atom-layer level.

[0102] The portion of the channel region other than the body contact region BD can also be doped (e.g., by diffusion from the first channel defining layer 1005 and / or the second channel defining layer 1009), and the doping characteristics can differ from those in the body contact region BD. For example, the doping concentration in the body contact region BD can be higher than that between the body contact region BD and the lower source / drain region S / D. L The doping concentration in the region between (defined by diffusion from the first channel defining layer 1005) and / or the bulk contact region BD and the upper source / drain region S / D U The doping concentration in the region between (defined by diffusion from the second channel defining layer 1009).

[0103] On one side of the vertical active region (the right side in FIG13(b)), a body contact limiting layer 1007 (or, body contact layer) and a contact portion 1053 may be provided. BD It can be attached to it. The body contact area BD can be self-aligned with the body contact layer.

[0104] The gate stack (1039 / 1041) can surround the vertical active region, particularly the channel region therein. On this side where the body contact layer is located, the gate stack sandwiches the body contact layer. The gate stack can be self-aligned to the channel region, as shown in Fig. 13(c).

[0105] According to other embodiments of the present disclosure, a split gate configuration can also be formed. For example, gate stacks can be formed on opposite sides (e.g., left and right sides) of the active layer, respectively. In the case of forming a split gate configuration, isolation between different gate stacks is also needed.

[0106] Figures 14(a) to 18(c) Fig. 18 shows a schematic diagram of some stages in a flow of fabricating a semiconductor device according to another embodiment of the present disclosure.

[0107] As Figure 14(a) , 14(b) and 14(c), in the process of forming the isolation layer 1033' as described above in connection with Figure 9(a) and 9(b) , after planarizing the oxide and before etching back the oxide, a photoresist 1037 can be formed on the planarized oxide. The photoresist 1037 can be patterned into a shape such that, on one hand, the sidewall of the active layer 1021 on the left side can be exposed so that the oxide left on the left side due to the photoresist 1037 later will not shadow the sidewall of the active layer 1021; on the other hand, the sidewall of the sidewall 1019 on the right side can be exposed so that the oxide left on the right side due to the photoresist 1037 later will not shadow the sidewall of the semiconductor layer stack, particularly the first and second channel-defining layers therein. Thus, the photoresist 1037 can be patterned into a strip shape extending in the first direction between the left sidewall of the active layer 1021 and the right sidewall of the sidewall 1019. The oxide can be etched back to form the isolation layer 1033' in the presence of the photoresist 1037, and other conditions of the etching back can be the same as described above in the embodiments. After that, the photoresist 1037 can be removed.

[0108] The isolation layer 1033' thus formed has a protruding portion (the portion shadowed by the photoresist 1037) in addition to surrounding each segment as described above, which extends from opposite sides of the active layer 1021 in the first direction (see Figure 14(a) and 14(c) , and see Fig. 18(c)), thereby separating the space on the isolation layer 1033' into a first space on the left side of the protruding portion and a second space on the right side of the protruding portion.

[0109] After that, the process can continue as described above in connection with Figure 11(a) , 11(b)The gate stack is formed. Due to the presence of the protruding portion of the isolation layer 1033', the formed gate stack can include two portions: a portion to the left of the protruding portion of the isolation layer 1033' (which can be referred to as "first gate stack") and a portion to the right of the protruding portion of the isolation layer 1033' (which can be referred to as "second gate stack"), which are electrically isolated from each other by the protruding portion of the isolation layer 1033'. The first gate stack and the second gate stack can be used for different purposes, e.g., one of them such as the first gate stack can be used as a control gate, and the other such as the second gate stack can be used to control Vt.

[0110] In this example, the first gate stack and the second gate stack include the same gate dielectric layer 1039 and gate conductor layer 1041. However, the present disclosure is not limited thereto. They can have different configurations, e.g., with different work function layers.

[0111] For example, as shown in Figure 15 the left first gate stack can be masked with, e.g., a photoresist 1043, while the right second gate stack is exposed. The gate conductor layer 1041 (for convenience, the gate conductor layer 1041 is referred to as "first gate conductor layer") in the second gate stack can be removed by selective etching. Thereafter, the photoresist 1043 can be removed. Then, as shown in Figure 16 a second gate conductor layer 1045 can be additionally formed on the gate dielectric layer 1039 by, e.g., deposition and etch-back. The top surface of the second gate conductor layer 1045 can be substantially flush with the top surface of the first gate conductor layer 1041. The second gate conductor layer 1045 can also include a work function layer (and optionally, a conductive material layer), but have different characteristics, e.g., different effective work function, from the first gate conductor layer 1041. Thus, the first gate stack and the second gate stack with different configurations can be formed on the left and right sides, respectively.

[0112] In this example, the gate dielectric layer 1039 is preserved when forming the different second gate stack. However, the present disclosure is not limited thereto. For example, the gate dielectric layer 1039 can also be removed, and an additional gate dielectric layer is additionally formed, and the second gate conductor layer 1045 is formed on the additional gate dielectric layer.

[0113] Contact portions can be formed to the first gate stack and the second gate stack, respectively.

[0114] As shown in Figure 17(a) and 17(b) a photoresist 1049' can be formed on the first gate conductor layer 1041 and the second gate conductor layer 1045, and patterned to expose the first gate conductor layer 1041 and the second gate conductor layer 1045, as shown in Figure 12(a) and 12(b)The photoresist 1049 is substantially the same shape except that it covers an additional portion of the area to the right of the active region 1021 (as schematically shown by the area to the right of the upper corner of the photoresist 1049' in the plan view of Figure 17(a)) so as to define a landing pad for a contact to the second gate stack. Here, this additional portion does not overlap at least a portion of the area of the body contact layer 1007 that is used to define a landing pad for a contact to the body contact region BD so as not to interfere with the subsequently formed contact to the body contact region BD. The photoresist 1049' and the sidewall 1019, which can be so patterned, act as etch masks for the selective etching, such as vertical direction RIE, of the first gate conductor layer 1041 and the second gate conductor layer 1045. Thereafter, the photoresist 1049' can be removed.

[0115] Figure 17(b) schematically shows a cross-sectional view along the CC' line of Figure 17(a), while the cross-sectional view along the AA' line of Figure 17(a) is substantially the same as that shown in Figure 12(b) except that the unitary gate stack is replaced by the first gate stack and the second gate stack that are isolated from each other.

[0116] Thereafter, as shown in Figures 17(c) and 18(c), the interlayer dielectric layer 1051 can be formed and various contacts can be formed in the interlayer dielectric layer 1051 as described above in connection with Figures 13(c) and 14(c). Figure 18(a) , 18(b) The first gate stack and the second gate stack are formed in the active region 1021 as described above in connection with Figures 13(a) and 14(a). Figure 13(a) and 13(b) The first gate stack and the second gate stack are formed in the active region 1021 as described above in connection with Figures 13(a) and 14(a). G1 The contact 1053 G2 to the second gate stack can land on the landing pad defined by the additional portion of the photoresist 1049' as described above. G2

[0117] In the cross-sectional view of Figure 18(b), the contact 1053 G2 to the second gate stack is schematically shown in dotted line because the contact 1053 G2 is not in the cross-section along the CC' line but in the cross-section along the DD' line as shown in Figure 18(c). In the subsequent figures, the cross-sections that are not related to the active region (e.g., the cross-section along the DD' line as shown in Figure 18(c)) are not specifically shown again if there is a contact in such cross-section, the corresponding contact will be marked on the relevant layer in dotted line in the manner as shown in Figure 18(b).

[0118] ​In the above embodiment, on the right side of the protruding portion of the isolation layer 1033', the second gate stack overlaps with the lower portion (corresponding to the region defined by the first channel layer 1005) and the upper portion (corresponding to the region defined by the second channel layer 1009) of the channel region in the active layer 1021, with a body contact defining layer 1007 sandwiched in between. The portions of the gate stack overlapping the lower and upper portions of the channel region have the same configuration. However, this disclosure is not limited thereto. They can have different configurations, such as having different work function layers, and can be used, for example, to optimize the bottom GIDL and the top GIDL.

[0119] Figures 19 to 23(c) A schematic diagram of a portion of the process for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown.

[0120] For example, such as Figure 19 As shown, in combination as described above Figure 15 and 16 After the second gate stack is formed, the first gate stack on the left can be masked using, for example, photoresist 1043', while exposing the second gate stack on the right (here, in combination as described above). Figure 15 and 16 The following description is based on the case where the second gate stack includes a second gate conductor layer 1045; however, the following description also applies to the case where the second gate stack includes a first gate conductor layer 1041. The second gate conductor layer 1045 in the second gate stack can be selectively etched back, exposing the upper part of the channel region while shielding the lower part of the channel region after the etch. For example, the height of the top surface may be between the height of the top surface and the height of the bottom surface of the body contact defining layer 1007. The gate dielectric layer 1039 exposed due to the etch-back of the second gate conductor layer 1045 can also be removed by selective etching. Thus, the second gate stack (1039 / 1045) can overlap with the lower part of the channel region, thereby controlling the lower part of the channel region and preventing it from overlapping with the upper part of the channel region. Afterwards, the photoresist 1043' can be removed.

[0121] For the upper part of the trench area, a separate grid stack can be formed. For example, such as... Figure 20As shown, a second gate dielectric layer 1039' and a second gate conductor layer 1047 (for convenience, the gate conductor layer 1047 is referred to as the "third gate conductor layer") can be sequentially formed on the second gate conductor layer 1045. The gate dielectric layer 1039' can be formed substantially conformally and can extend onto the first gate stack. The gate dielectric layer 1039' can include the same material as the gate dielectric layer 1039 or a different material. The third gate conductor layer 1047 can be etched back until its top surface is substantially flush with the top surface of the first gate conductor layer 1041. The third gate conductor layer 1047 can include a work function layer (and optionally, a conductive material layer), but has characteristics different from the second gate conductor layer 1045 (and may also be different from the first gate conductor layer 1041), such as a different effective work function. Thus, the second gate stack can be formed as two parts with different configurations.

[0122] Different gate configurations can be formed as needed: GAA gate configuration, separate gate configuration on opposite sides of the active region, and gate stacks with different portions on one side of the active region (specifically, the side where the body contact layer is located). Separate gate stacks or different portions of gate stacks can have different effective work functions. Different gate configurations can be used to optimize device performance, such as Vt control and GIDL optimization as mentioned above.

[0123] Contact portions can be formed in the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer, respectively.

[0124] like Figure 21(a) , 21(b) As shown in 21(c), photoresist 1049 can be formed on the first gate conductor layer 1041, the second gate conductor layer 1045, and the third gate conductor layer 1047, and patterned in conjunction with the above. Figure 17(a) and 17(b) The photoresist 1049' has a substantially the same shape, except that it covers an additional area on the right side of the active region 1021 (schematically shown in the lower right corner of the photoresist 1049' in the top view of FIG21(a)) to define the contact pads to the contact portion of the third gate conductor layer 1047 (the contact pads to the contact portion of the second gate conductor layer 1045 can be combined as described above). Figure 17(a) and 17(b)The area defined by the upper right corner of the photoresist 1049” is such that at least a portion of the area of ​​the bonding pad in the body contact layer 1007 used to define the contact portion to the body contact region BD does not overlap, so as not to interfere with the contact portion to the body contact region BD formed subsequently. The photoresist 1049” and the sidewall 1019 can be configured as an etching mask, and the first gate conductor layer 1041, (gate dielectric layer 1039′,), second gate conductor layer 1045 and third gate conductor layer 1047 are etched by selective etching such as vertical RIE. Afterwards, the photoresist 1049” can be removed.

[0125] Figure 21(b) schematically shows a cross-sectional view along line CC′ in Figure 21(a), and Figure 21(c) schematically shows a cross-sectional view along line EE′ in Figure 21(a). The cross-sectional view along line AA′ in Figure 21(a) is substantially the same as the cross-sectional view shown in Figure 12(b), except that the monolithic gate stack is replaced by a first gate stack and a second gate stack that are isolated from each other, and the second gate stack includes two parts with different configurations.

[0126] like Figure 22 As shown, the contact pad area of ​​the second gate conductor layer 1045 can be covered with photoresist (the area in the upper right corner of photoresist 1049" in the top view of FIG21(a), and the contact pad area of ​​the third gate conductor layer 1047 can be exposed (the area in the lower right corner of photoresist 1049" in the top view of FIG21(a). The second gate conductor layer 1045 can be further etched (which can stop at the gate dielectric layer 1039') by selective etching such as vertical RIE, so as to remove the second gate conductor layer 1045 from the third gate conductor layer 1047.

[0127] After that, as Figure 23(a) , 23(b) As shown in 23(c), it can be combined as described above. Figure 13(a) and 13(b) The interlayer dielectric layer 1051 is formed, and various contact portions are formed in the interlayer dielectric layer 1051. The difference from the above embodiment is that contact portions 1053 are formed to the first conductor layer 1041. G1 Contact portion 1053 to the second gate conductor layer 1045 G2 and the contact portion 1053 to the third gate conductor layer 1047 G3 Contact 1053 to the second gate conductor layer 1045 G2 and the contact portion 1053 to the third gate conductor layer 1047 G3 It can be attached to the attachment pad defined by the additional portion of the photoresist 1049”.

[0128] In the above embodiments, separate contacts are formed to the body contact layer and to the gate conductor layer. According to other embodiments of the present disclosure, the body contact layer can have a common contact with the gate conductor layer.

[0129] Figures 24(a) to 25(b) A schematic diagram showing part of a stage in a flow of fabricating a semiconductor device according to another embodiment of the present disclosure is shown.

[0130] As Figure 24(a) and 24(b) shown, a photoresist 1049"'" can be formed on the gate conductor layer and patterned to substantially the same shape as the photoresist 1049 described above in connection with Figure 12(a) and 12(b) except that it can overlap at least a portion of the landing pad of the contact to the body contact region BD previously defined in the body contact definition layer 1007 by the sidewall 1027 in plan view. The photoresist 1049"' thus patterned (and possibly the sidewall 1019, if there is a portion not covered by the photoresist 1049"') serves as an etch mask for etching the gate conductor layer by selective etching, such as RIE in the vertical direction. Thereafter, the photoresist 1049"' can be removed.

[0131] Thereafter, as Figure 25(a) and 25(b) shown, the interlayer dielectric layer 1051 can be formed as described above in connection with Figure 13(a) and 13(b) and various contacts can be formed in the interlayer dielectric layer 1051. Unlike the above embodiments, the contact 1053 BD may extend through the third gate conductor layer 1047, the body contact layer 1007, and into the second gate conductor layer 1045. Here, it can not be necessary to form the gate dielectric layer 1039' as described above in connection with Figure 20 but rather the gate dielectric layer 1039 can be retained and the third gate conductor layer 1047 can be formed directly after etching back the second gate conductor layer 1045, since the second gate conductor layer 1045 and the third gate conductor layer 1047 are electrically connected to each other in this example and do not need to be electrically isolated from each other using, for example, the gate dielectric layer 1039'.

[0132] Although in this example, the case where the second gate stack has the second gate conductor layer 1045 and the third gate conductor layer 1047 is illustrated, such a common contact 1053 BD may be applicable to other configurations of the second gate stack in the case of a separate gate stack, for example, in the case where the second gate stack includes a unitary structure (e.g., includes only the first gate conductor layer 1041 or only the second gate conductor layer 1045).

[0133] In addition, although in this example, the common contact 1053BD The common contact portion 1053 can be in contact with the third gate conductor layer 1047, the body contact layer 1007, and the second gate conductor layer 1045, but the present disclosure is not limited thereto. For example, the common contact portion 1053 BD The common contact portion 1053 can be in contact with the third gate conductor layer 1047, the body contact layer 1007, and the second gate conductor layer 1045, but the present disclosure is not limited thereto. For example, the common contact portion 1053

[0134] The semiconductor device according to the embodiments of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above-described semiconductor device. The electronic device can further include a display screen cooperating with the integrated circuit, a wireless transceiver cooperating with the integrated circuit, and the like. Such an electronic device is, for example, a smart phone, a personal computer (PC), a tablet PC, an artificial intelligence device, a wearable device, a mobile power supply, a car electronic device, a communication device, or an Internet of Things (IoT) device.

[0135] According to the embodiments of the present disclosure, a method of manufacturing a system on chip (SoC) is also provided. The method can include the above-described method. Specifically, a plurality of devices can be integrated on a chip, at least some of which are manufactured according to the method of the present disclosure.

[0136] In the above description, detailed descriptions of patterning, etching, and the like of each layer are not provided. However, it will be understood by those skilled in the art that the layers, regions, and the like having desired shapes can be formed by various technical means. In addition, those skilled in the art can design a method that is not exactly the same as the above-described method in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0137] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: An active region vertically disposed on a substrate relative to the substrate includes a lower source / drain region, an upper source / drain region, and a middle portion between the lower source / drain region and the upper source / drain region for defining a channel region; A first gate stack and a second gate stack are disposed on a first side and a second side opposite to each other in the lateral direction relative to the substrate in the active region; A body contact layer is disposed on the second side of the active region to overlap with a portion of the central part of the active region to apply a body bias to the active region; An upper source / drain contact layer is disposed on the second side of the active region to contact the upper source / drain region; as well as The upper source / drain contact portion is attached to the upper source / drain contact layer. The second gate stack includes a first portion below the body contact layer and a second portion above the body contact layer. The active region is defined by a single-crystal semiconductor layer, wherein the semiconductor layer is in the form of a nanosheet or nanowire. The semiconductor layer includes a vertically extending portion extending in a vertical direction to provide the active region and a laterally extending portion extending from the lower end of the vertically extending portion on the first side. The semiconductor device further includes: The lower source / drain contact portion of the lower source / drain region is attached to the lateral extension portion of the semiconductor layer; and A lower source / drain region defining layer extends from below the lateral extension portion of the semiconductor layer to the surface of the semiconductor layer on the second side.

2. The semiconductor device according to claim 1, wherein, The first gate stack and the second gate stack are integral to each other and extend continuously around the outer periphery of the active region.

3. The semiconductor device according to claim 1, wherein, The first gate stack and the second gate stack are electrically isolated from each other.

4. The semiconductor device according to claim 3, wherein, The first gate stack and the second gate stack have different effective work functions.

5. The semiconductor device according to claim 3, wherein, The first and second portions of the second gate stack are adjacent to each other.

6. The semiconductor device according to claim 3, wherein, The first portion of the second gate stack overlaps with the portion below the body contact layer in the middle of the active region, and the second portion of the second gate stack overlaps with the portion above the body contact layer in the middle of the active region, and the first and second portions of the second gate stack are electrically isolated from each other.

7. The semiconductor device according to claim 3, wherein, The first and second portions of the second gate stack have different effective work functions.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The active region contains a doped region in the middle, which serves as a body contact region, and the body contact layer is in contact with the body contact region.

9. The semiconductor device according to claim 8, wherein, The conductivity type of the body contact region is opposite to that of at least one of the lower source / drain region and the upper source / drain region.

10. The semiconductor device according to claim 8, wherein, The body contact area is self-aligned with the body contact layer.

11. The semiconductor device according to claim 8, wherein, The body contact layer contains dopants of the same conductivity type as the dopants in the body contact region.

12. The semiconductor device according to claim 8, wherein, The body contact region occupies only a portion of the central part of the active region in the vertical direction, and the body contact region has different doping characteristics from the rest of the central part of the active region.

13. The semiconductor device according to claim 12, wherein, The doping concentration in the body contact region is higher than the doping concentration in at least one of the regions between the body contact region and the lower source / drain region and between the body contact region and the upper source / drain region in the middle of the active region.

14. The semiconductor device according to any one of claims 1 to 7, wherein, The bulk contact layer comprises a single-crystal semiconductor.

15. The semiconductor device according to claim 1 or 2, further comprising: The body contact portion of the body contact layer is used to receive the body bias. The body contact layer extends away from the active region in the lateral direction, and the body contact portion contacts the body contact layer.

16. The semiconductor device according to any one of claims 3 to 7, further comprising: The body contact portion of the body contact layer is used to receive the body bias. The body contact layer extends away from the active region in the lateral direction, and the body contact portion contacts the body contact layer.

17. The semiconductor device according to claim 16, wherein, The body contact portion passes through and contacts at least the second portion of the first and second portions of the second gate stack.

18. The semiconductor device according to claim 1, wherein, The upper source / drain contact layer comprises a single-crystal semiconductor.

19. The semiconductor device according to claim 1, wherein, The upper source / drain contact layer contains dopants of the same conductivity type as the upper source / drain region, and the upper source / drain region is self-aligned to the upper source / drain contact layer.

20. The semiconductor device according to claim 1, wherein, The vertical spacing between the upper source / drain contact layer and the body contact layer is substantially uniform.

21. The semiconductor device according to claim 1, wherein, The lower source / drain region defining layer contains dopants of the same conductivity type as the lower source / drain region, and the lower source / drain region is self-aligned to the portion of the lower source / drain region defining layer on the second side.

22. The semiconductor device according to claim 1, wherein, The lower source / drain region defining layer includes a single-crystal semiconductor.

23. The semiconductor device according to claim 1, wherein, The vertical spacing between the lower source / drain region defining layer and the body contact layer is substantially uniform.

24. The semiconductor device according to any one of claims 1 to 7, wherein, The gate stack is self-aligned to the center of the active region.

25. The semiconductor device according to claim 5, further comprising: To the first gate contact portion of the first gate stack; as well as To the second gate contact portion of the second gate stack.

26. The semiconductor device according to claim 6, further comprising: To the first gate contact portion of the first gate stack; To the second gate contact portion of the first part of the second gate stack; as well as To the third gate contact portion of the second portion of the second gate stack.

27. A method of manufacturing a semiconductor device as claimed in claim 1, comprising: A stack of a first source / drain defining layer, a first channel defining layer, a body contact defining layer, a second channel defining layer, and a second source / drain defining layer is disposed on a substrate; An active layer is formed on the vertical sidewall of the stack extending in a first direction; The dopants in the first source / drain limiting layer, the dopants in the body contact limiting layer, and the dopants in the second source / drain limiting layer are respectively driven into the corresponding portions of the active layer to form the lower source / drain region, the body contact region, and the upper source / drain region, respectively. Form an isolation layer around the stacked layers; Remove the first channel defining layer and the second channel defining layer; A gate stack is formed on the isolation layer, the gate stack including a first gate stack and a second gate stack opposite to each other on a first side and a second side in a second direction intersecting the first direction, the second gate stack entering the space between the first source / drain defining layer and the body contact defining layer and between the body contact defining layer and the second source / drain defining layer; as well as A body contact portion is formed into the body contact defining layer.

28. The method according to claim 27, wherein, The stacked layers and the active layer are formed by an epitaxial growth process.

29. The method according to claim 27, wherein, The isolation layer surrounding the stack has a substantially flat top surface, such that the first and second gate stacks formed on the isolation layer are integral with each other and extend continuously around the outer periphery of the active region.

30. The method according to claim 27, wherein, The isolation layer has protrusions on opposite sides of the stack in the first direction, such that the first gate stack and the second gate stack formed on the isolation layer are electrically isolated from each other through the protrusions.

31. The method according to claim 30, wherein, The second grid stack comprises a first part and a second part stacked in the vertical direction.

32. The method of claim 27, further comprising: The stack is configured such that the body contact defining layer extends relative to the second source / drain defining layer. The body contact portion is attached to the portion of the body contact defining layer that extends relative to the second source / drain defining layer.

33. The method according to claim 30, wherein, Forming a gate stack includes: A first gate dielectric layer is formed on the isolation layer; A first gate conductor layer is formed on the first gate dielectric layer; Remove a portion of the first gate conductor layer on the second side of the protrusion; and On the second side of the protruding portion, a second gate conductor layer is formed on the first gate dielectric layer.

34. The method of claim 33, further comprising: Etching back the second gate conductor layer; Selectively etch the portion of the second gate conductor layer exposed by the etchback of the first gate dielectric layer; Forming a second gate dielectric layer; as well as A third gate conductor layer is formed on the second gate dielectric layer.

35. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 26.

36. The electronic device according to claim 35, wherein, The electronic device includes a smartphone.

37. The electronic device according to claim 35, wherein, The electronic device includes a personal computer.

38. The electronic device according to claim 35, wherein, The electronic device includes a tablet computer.

39. The electronic device according to claim 35, wherein, The electronic devices include artificial intelligence devices.

40. The electronic device according to claim 35, wherein, The electronic devices include wearable devices.

41. The electronic device according to claim 35, wherein, The electronic device includes a power bank.

42. The electronic device according to claim 35, wherein, The electronic devices include automotive electronic devices.

43. The electronic device according to claim 35, wherein, The electronic equipment includes communication equipment.

44. The electronic device according to claim 35, wherein, The electronic devices include Internet of Things (IoT) devices.

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