Light-emitting diode chip with improved transfer accuracy and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip with improved transfer accuracy and a preparation method thereof, which belongs to the field of optoelectronic manufacturing technology. The light-emitting diode chip has a first surface, a second surface and multiple side surfaces, the first surface and the second surface are opposite, and the first surface is the surface where the electrode is located, the multiple side surfaces are respectively connected to the first surface and the second surface, and the side surfaces have multiple guide grooves, and the multiple guide grooves are symmetrically distributed on the axis of the positive projection of the first surface. The guide grooves extend from the first surface to the second surface, and the cross-sectional area of ​​the guide grooves gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide grooves close to the first surface is larger than the cross-sectional area of ​​the end away from the first surface. The embodiment of the present disclosure can allow the chip to be smoothly transferred to the circuit board during the chip transfer process, thereby improving the chip transfer accuracy.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode chip with improved transfer accuracy and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness and energy saving.

[0003] In the related art, a mass transfer method is used to arrange LED chips on a circuit board. During mass transfer, a large number of LED chips are first adhered to a transfer plate, which is parallel to the circuit board, and the side of the LED chip with the electrode is facing the circuit board. When the position of the transfer plate is adjusted so that the LED chip is aligned with the area to be transferred on the circuit board, the adhesive between the LED chip and the transfer plate is decomposed by laser, allowing the LED chip to fall onto the circuit board to complete the transfer operation.

[0004] However, position deviation is prone to occur when the LED chips are placed on the circuit board, resulting in poor precision in mass transfer. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip with improved transfer accuracy and a method for manufacturing the same, which can smoothly transfer the chip to the circuit board during the chip transfer process, thereby improving the chip transfer accuracy. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip with improved transfer accuracy, wherein the light-emitting diode chip has a first surface, a second surface, and multiple side surfaces, wherein the first surface and the second surface are opposite to each other, and the first surface is the surface where the electrode is located, and the multiple side surfaces respectively connect the first surface and the second surface, and the side surfaces have multiple guide grooves, and the multiple guide grooves are symmetrically distributed on the axis of the positive projection of the first surface, and the guide grooves extend from the first surface to the second surface, and the cross-sectional area of ​​the guide grooves gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide groove at one end close to the first surface is larger than the cross-sectional area at the end away from the first surface.

[0007] Optionally, a width of the guide groove at an end portion close to the first surface is 8 μm to 12 μm, and a width of the guide groove at an end portion away from the first surface is 3 μm to 7 μm.

[0008] Optionally, the depth of the guide groove at its maximum depth is not greater than 3 μm, and the depth of the guide groove at its minimum depth is not less than 1 μm.

[0009] Optionally, the first surface and the second surface are rounded rectangles, and the guide grooves are located at the rounded corners of the rounded rectangles.

[0010] Optionally, the cross section of the guide groove is arc-shaped or V-shaped.

[0011] Optionally, the guide groove extends from the first surface to the second surface.

[0012] Optionally, the light-emitting diode chip includes: a substrate, an epitaxial layer, a leveling layer and the electrode; the epitaxial layer is located on the substrate, the leveling layer and the electrode are located on the surface of the epitaxial layer away from the substrate, and the leveling layer has a via hole exposing the electrode.

[0013] Optionally, the electrode is 0.3 μm to 0.7 μm higher than the filling layer.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode chip with improved transfer accuracy, the preparation method comprising: making a light-emitting diode chip, the light-emitting diode chip having a first surface, a second surface and multiple side surfaces, the first surface and the second surface being opposite to each other, and the first surface being the surface where the electrode is located, and the multiple side surfaces respectively connecting the first surface and the second surface; making multiple guide grooves on the side surfaces, the multiple guide grooves being symmetrically distributed on the axis of the positive projection of the guide grooves on the first surface, the guide grooves extending from the first surface to the second surface, the cross-sectional area of ​​the guide grooves gradually decreasing from one end to the other end, and the cross-sectional area of ​​the guide groove at one end close to the first surface being larger than the cross-sectional area at the end away from the first surface.

[0015] Optionally, making the guide groove on the side includes: introducing a mixed gas to dry-etch the first surface to form the guide groove, the mixed gas includes Cl2, BCl3 and O2, and when etching the guide groove, gradually increasing the proportion of O2 in the mixed gas.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The side surface of the light-emitting diode chip provided by the embodiment of the present disclosure has multiple guide grooves, which extend from the first surface to the second surface, and the cross-sectional area of ​​the guide groove gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide groove at one end close to the first surface is larger than the cross-sectional area at the end away from the first surface.

[0018] As the chip drops onto the circuit board, the electrode-side of the chip faces downward. Therefore, air flows through the guide grooves, whose cross-sectional area gradually decreases from bottom to top. As a result, the air is gradually compressed as it flows along the grooves, creating aerodynamic forces within the grooves. Because the multiple guide grooves are axially symmetrically distributed across the chip, the aerodynamic forces are also applied symmetrically, allowing the chip to drop more smoothly from the transfer plate onto the circuit board, effectively preventing positional deviations during the chip's drop, which could affect chip transfer accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a transfer diagram of a light-emitting diode chip provided by the related art;

[0021] Figure 2 is a top view of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 3 yes Figure 2 An AA cross-sectional view is provided;

[0023] Figure 4 is a partial schematic diagram of an epitaxial layer provided by an embodiment of the present disclosure;

[0024] Figure 5 is a top view of another light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 6 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0028] Figure 9 This is a schematic diagram of a process for preparing a light-emitting diode chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] Micro LEDs, as ultra-small chips, offer significantly improved display resolution. However, their small size makes them difficult to accurately sort with sorting equipment. Consequently, when transferring large numbers of LED chips, mass transfer is the only method used to arrange them on a circuit board.

[0032] Figure 1 This is a transfer diagram of a light-emitting diode chip provided by the related technology. Figure 1 As shown, during the transfer process, the LED chip C is first adhered to the transfer plate 51 by the adhesive X, with the side of the LED chip C having the electrode 30 away from the transfer plate 51. Then, the transfer plate 51 is moved so that the transfer plate 51 and the circuit board 52 are parallel and opposite each other. Next, when the LED chip C is aligned with the area to be transferred on the circuit board 52, the adhesive X between the LED chip C and the transfer plate 51 is decomposed by laser. Since the adhesive X is filled with nitrogen, after the laser decomposition, the nitrogen overflows and exerts a force on the LED chip C, causing the LED chip C to quickly fall onto the circuit board 52, completing the transfer operation.

[0033] However, position deviation is likely to occur when the LED chips are dropped onto the circuit board 52 , thereby causing poor precision in mass transfer.

[0034] To this end, an embodiment of the present disclosure provides a top view of a light emitting diode chip. Figure 2This is a top view of a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 3 yes Figure 2 An AA cross-section diagram is provided. Figure 2 、 3 As shown, the light-emitting diode chip has a first surface 101, a second surface 102 and multiple side surfaces, the first surface 101 and the second surface 102 are opposite to each other, and the first surface 101 is the surface where the electrode 30 is located, and the multiple side surfaces respectively connect the first surface 101 and the second surface 102, and have multiple guide grooves 20 on the side surfaces, and the multiple guide grooves 20 are symmetrically distributed about the axis of the positive projection on the first surface 101, and the guide grooves 20 extend from the first surface 101 to the second surface 102, and the cross-sectional area of ​​the guide grooves 20 gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide groove at one end close to the first surface is larger than the cross-sectional area at the end away from the first surface.

[0035] The side surface of the light-emitting diode chip provided by the embodiment of the present disclosure has multiple guide grooves, which extend from the first surface to the second surface, and the cross-sectional area of ​​the guide groove gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide groove at one end close to the first surface is larger than the cross-sectional area at the end away from the first surface.

[0036] As the chip drops onto the circuit board, the electrode-side of the chip faces downward. Therefore, air flows through the guide grooves, whose cross-sectional area gradually decreases from bottom to top. As a result, the air is gradually compressed as it flows along the grooves, creating aerodynamic forces within the grooves. Because the multiple guide grooves are axially symmetrically distributed across the chip, the aerodynamic forces are also applied symmetrically, allowing the chip to drop more smoothly from the transfer plate onto the circuit board, effectively preventing positional deviations during the chip's drop, which could affect chip transfer accuracy.

[0037] Alternatively, as Figure 2 As shown, the width H of the guide groove 20 at the end close to the first surface 101 is 8 μm to 12 μm, and the width of the guide groove 20 at the end away from the first surface 101 is 3 μm to 7 μm. The width at the end of the guide groove refers to the width of the opening of the guide groove.

[0038] In the embodiment of the present disclosure, the end of the guide groove 20 close to the electrode 30 is the end with a larger size, and the end of the guide groove 20 close to the substrate 10 is the end with a smaller size.

[0039] By limiting the length between the two farthest points on the cross section of the two ends of the guide groove 20 to the above range, it is possible to prevent the guide groove 20 from being too small and failing to guide the air to form aerodynamics; it is also possible to prevent the guide groove 20 from being too large, which would result in more epitaxial layers 2 being removed and affect the luminescence effect.

[0040] For example, the width H of the guide groove 20 at the end portion close to the first surface 101 is 10 μm, and the width of the guide groove 20 at the end portion away from the first surface 101 is 5 μm.

[0041] Optionally, the cross section of the guide groove 20 is arc-shaped or V-shaped.

[0042] When the cross section of the guide groove 20 is set to an arc, the groove wall of the guide groove 20 is smoother, and the resistance of air flowing along the guide groove 20 is smaller, so that it can better guide the air and form aerodynamics.

[0043] For example, Figure 2 As shown, the cross section of the guide groove 20 is V-shaped, wherein the angle between two lines of the cross section of the guide groove 20 exceeds 90 degrees.

[0044] For example, Figure 4 FIG. 1 is a partial schematic diagram of an epitaxial layer provided by an embodiment of the present disclosure. Figure 4 As shown, the cross section of the guide groove 20 is an arc.

[0045] It should be noted that the cross-section of the guide groove 20 can also be other shapes, which is not limited in the embodiment of the present disclosure.

[0046] Optionally, the maximum depth of the guide groove 20 is no greater than 3 μm, and the minimum depth is no less than 1 μm. The depth h of the guide groove 20 refers to the length of the guide groove 20 extending from the sidewall of the epitaxial layer 2 to the middle of the epitaxial layer 2. In other words, the depth of the guide groove 20.

[0047] In the embodiment of the present disclosure, the depth of the guide groove 20 at the end of the first surface 101 is not less than the depth of the end of the guide groove 20 close to the second surface 102 .

[0048] By limiting the depth of the guide groove 20 within the above range, it can prevent the depth of the guide groove 20 from being too small, thereby failing to guide the air to form aerodynamics; it can also prevent the depth of the guide groove 20 from being too large, thereby causing more epitaxial layers 2 to be dug out and affecting the luminescence effect.

[0049] Exemplarily, the maximum depth of the guide groove 20 at the end portion of the first surface 101 is 2 μm, and the maximum depth of the guide groove 20 at the end portion close to the second surface 102 is 1 μm.

[0050] Optionally, the orthographic projection of the epitaxial layer 2 on the surface of the substrate 10 is a rectangle, and the guide groove 20 is located at a side or corner of the rectangle.

[0051] For example, Figure 2 As shown, the orthographic projection of the epitaxial layer 2 on the surface of the substrate 10 is a rounded rectangle, the guide grooves 20 are located at the rounded corners of the rounded rectangle, and each rounded corner of the rounded rectangle has a plurality of guide grooves 20 distributed at intervals.

[0052] For example, Figure 2 As shown, each rounded corner of the rounded rectangle has three spaced-apart guide grooves 20. The middle guide groove 20 of the three guide grooves 20 is distributed on the diagonal of the rectangle, and the remaining two guide grooves 20 are distributed at the corners of the rectangle close to the side edges of the rounded rectangle. In this way, the guide grooves 20 located on the diagonal of the rounded rectangle can exert aerodynamic force on the rounded corners of the rounded rectangle during the falling process; and the two guide grooves 20 located on both sides of the diagonal of the rounded rectangle can also exert a certain amount of aerodynamic force on the side edges of the rounded rectangle because they are close to the side edges of the rounded rectangle. As a result, the forces at each position are more balanced during the falling process of the chip, thereby improving the stability of the chip falling.

[0053] Optionally, Figure 5 FIG. 1 is a top view of another light emitting diode chip provided by an embodiment of the present disclosure. Figure 5 As shown, the positive projection of the epitaxial layer 2 on the surface of the substrate 10 is a rectangle, the guide grooves 20 are located on the sides of the rectangle, the number of the guide grooves 20 on the two opposite sides of the rectangle is the same, and the guide grooves 20 on the two opposite sides of the rectangle are symmetrically distributed.

[0054] Since the side length of the guide groove 20 is large, more guide grooves 20 can be set. In this way, more areas of the chip will be affected by aerodynamics during the falling process of the chip, allowing the chip to fall more smoothly from the transfer plate 51 to the circuit board 52, effectively preventing position deviation during the falling process of the chip.

[0055] In other implementations, when the orthographic projection of the epitaxial layer 2 on the surface of the substrate 10 is a rectangle, the guide grooves 20 can be evenly distributed along the outer contour of the rectangle. In this way, during the chip's drop, all positions on the chip are affected by aerodynamic forces, ensuring balanced force on all sides of the chip, thereby improving the chip's falling stability.

[0056] Alternatively, as Figure 2 As shown, the guide groove 20 extends from the first surface 101 to the second surface 102 .

[0057] In the disclosed embodiment, the guide groove 20 extends from the surface of the epitaxial layer 2 close to the electrode 30 to the surface of the substrate 10 away from the epitaxial layer 2. In this way, when etching the guide groove 20, the epitaxial layer 2 and the substrate 10 can be directly etched through together, which is more convenient to manufacture.

[0058] Alternatively, as Figure 3 As shown, the light-emitting diode chip also includes a substrate 10, an epitaxial layer 2, a leveling layer 42 and an electrode 30; the epitaxial layer 2 is located on the substrate 10, the leveling layer 42 and the electrode 30 are located on the surface of the epitaxial layer 2 away from the substrate 10, and the leveling layer 42 has a via hole exposing the electrode 30.

[0059] The filling layer 42 may be a spin-on glass coating (SOG) layer.

[0060] In the disclosed embodiment, the curing temperature of the SOG layer can be controlled between 150°C and 250°C. This allows the SOG to be coated on the film surface before it is fully cured, resulting in a relatively flexible SOG layer. This allows the LED chip to act as a buffer after it falls onto the circuit board 52, preventing it from being damaged during the fall.

[0061] Optionally, the electrode 30 is 0.3 μm to 0.7 μm higher than the filling layer.

[0062] Exemplarily, the electrode 30 is 0.5 μm higher than the leveling layer.

[0063] The filling layer 42 fills the step between the electrode 30 and the surface of the epitaxial layer 2, so that the chip is subjected to symmetrical and balanced forces during transfer. After filling, the filling layer 42 is slightly lower than the end surface of the electrode 30 to provide power to the external power supply.

[0064] Optionally, substrate 10 is a sapphire substrate. Sapphire substrates have a relatively high light transmittance, i.e., substrate 10 is a transparent substrate. Furthermore, sapphire material is relatively hard and chemically stable, which enables the light-emitting diode to have good luminous effect and stability.

[0065] Alternatively, as Figure 3 As shown, the epitaxial layer 2 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 sequentially stacked on the substrate 10 . The surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0066] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0067] As an example, the first semiconductor layer 21 is a p-type layer, and one of the two electrodes 30 is a p-type electrode 30 . The second semiconductor layer 23 is an n-type layer, and the other of the two electrodes 30 is an n-type electrode 30 .

[0068] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0069] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0070] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0071] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0072] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0073] Alternatively, as Figure 3 As shown, the light-emitting diode chip further includes a passivation layer 41, which is located between the epitaxial layer and the fill layer 42. The passivation layer 41 is located at least on the second semiconductor layer 23 and the groove 24. Two electrodes 30 are located on the surface of the passivation layer 41 away from the substrate 10. The passivation layer 41 has two through holes 40, one through hole 40 exposing the second semiconductor layer 23, and the other through hole 40 exposing the surface of the groove 24. One of the two electrodes 30 is connected to the second semiconductor layer 23 through one through hole 40, and the other of the two electrodes 30 is connected to the first semiconductor layer 21 through the other through hole 40.

[0074] For example, the passivation layer 41 may be a distributed Bragg reflector (DBR layer), which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0075] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0076] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0077] Alternatively, as Figure 3 As shown, a protective layer 43 is further provided between the passivation layer 41 and the leveling layer 42 , and the protective layer 43 extends from the surface of the passivation layer 41 to the substrate 10 .

[0078] For example, in the embodiment of the present disclosure, the protective layer 43 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0079] like Figure 2 As shown, the two electrodes 30 are both rectangular blocks, and the two electrodes 30 are spaced apart to increase the area and facilitate electrical conduction.

[0080] Figure 6 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 3 The light emitting diode chip shown. Figure 6 As shown, the preparation method comprises:

[0081] S11: Making light-emitting diode chips.

[0082] The light emitting diode chip has a first surface, a second surface and a plurality of side surfaces. The first surface and the second surface are opposite to each other, and the first surface is the surface where the electrode is located. The plurality of side surfaces are respectively connected to the first surface and the second surface.

[0083] S12: Make multiple guide grooves on the side.

[0084] Among them, multiple guide grooves are axially symmetrically distributed on the first surface, the guide grooves extend from the first surface to the second surface, the cross-sectional area of ​​the guide grooves gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide grooves at one end close to the first surface is larger than the cross-sectional area of ​​the end away from the first surface.

[0085] The side of the light-emitting diode chip prepared by this preparation method has multiple guide grooves, which extend from the first surface to the second surface, and the cross-sectional area of ​​the guide grooves gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide grooves at the end close to the first surface is larger than the cross-sectional area at the end away from the first surface. Since the chip has an electrode side facing downward during the process of falling to the circuit board, the air will flow along the guide grooves during the falling process, and the cross-sectional area of ​​the guide grooves gradually decreases from bottom to top. Therefore, the air will be gradually compressed during the flow along the guide grooves, thereby forming aerodynamic forces in the guide grooves. Since the multiple guide grooves are axially symmetrically distributed on the chip, the aerodynamic forces are also symmetrically applied to the chip, so that the chip can fall from the transfer plate to the circuit board more smoothly, effectively preventing position deviations during the chip falling process, which affects the chip transfer accuracy.

[0086] Figure 7 FIG. 1 is a schematic diagram of a process for preparing a light-emitting diode chip according to an embodiment of the present disclosure. Figure 7 As shown, in step S11, the light emitting diode chip can be manufactured by first forming an epitaxial wafer. The process of preparing the epitaxial wafer may include the following steps:

[0087] In the first step, a GaAs wafer 11 is provided.

[0088] In the second step, an epitaxial layer 2 is grown on the GaAs wafer 11 . The epitaxial layer 2 includes a second semiconductor layer 23 , a multi-quantum well layer 22 and a first semiconductor layer 21 stacked in sequence.

[0089] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0090] For example, the second semiconductor layer 23 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0091] For example, the first semiconductor layer 21 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0092] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0093] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0094] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0095] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0096] For example, in the embodiment of the present disclosure, the first semiconductor layer 21 may be a p-type layer.

[0097] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 10,000 angstroms to 20,000 angstroms.

[0098] Illustratively, the thickness of the GaP window layer is 11,000 angstroms.

[0099] The third step, such as Figure 8 As shown, a bonding layer 44 is formed between the first semiconductor layer 21 and the sapphire substrate 10, the epitaxial layer 2 is bonded to the sapphire substrate 10, and the GaAs wafer 11 is removed.

[0100] Since the sapphire substrate 10 has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of the sapphire substrate 10 can enable the light-emitting diode to have good light-emitting effect and stability.

[0101] Specifically, the process may include coating silicon oxide liquid on the surface of the second semiconductor layer 23, placing the sapphire substrate 10 on the surface of the second semiconductor layer 23, and heating the epitaxial wafer to heat and solidify the silicon oxide liquid to form a bonding layer 44 between the second semiconductor layer 23 and the sapphire substrate 10.

[0102] Optionally, the heating temperature of the epitaxial wafer is 250° C. to 350° C. Exemplarily, the heating temperature may be 300° C.

[0103] like Figure 9 As shown, before step S12 , the preparation method further includes: etching the second semiconductor layer 23 to form a groove 24 exposing the second semiconductor layer 23 .

[0104] Specifically, the method may include: etching the second semiconductor layer 23 by dry etching to expose the first semiconductor layer 21 .

[0105] After the epitaxial wafer is formed in step S11, the preparation method may further include the following steps:

[0106] In the first step, a passivation layer 41 is formed on the epitaxial wafer. The passivation layer 41 is at least located on the second semiconductor layer 23 and the groove 24 .

[0107] The passivation layer 41 may be a distributed Bragg reflector layer, which may be a DBR layer. The DBR layer includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0108] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0109] In the second step, two through holes 40 are formed on the passivation layer 41 .

[0110] After the passivation layer 41 is formed, two through holes 40 are formed by etching on a surface of the passivation layer 41 away from the substrate 10 . The two through holes 40 expose the first semiconductor layer 21 and the second semiconductor layer 23 respectively.

[0111] Two electrodes 30 are formed on the surface of the passivation layer 41 by photolithography, so that one electrode 30 is connected to the first semiconductor layer 21 through the through hole 40 , and the other electrode 30 is connected to the second semiconductor layer 23 through the via hole.

[0112] In the embodiment of the present disclosure, the electrode 30 may include a Ti layer, a first Ni layer, an Au layer, a second Ni layer, and an In layer stacked in sequence.

[0113] Illustratively, the thickness of the Ti layer may be 500 angstroms to 1500 angstroms, for example, the thickness of the Ti layer may be 1000 angstroms.

[0114] Illustratively, the thickness of the first Ni layer may be 500 angstroms to 1500 angstroms. For example, the thickness of the first Ni layer may be 1000 angstroms.

[0115] Illustratively, the thickness of the Au layer may be 8000 angstroms to 12000 angstroms, for example, the thickness of the Au layer may be 5000 angstroms.

[0116] Illustratively, the thickness of the second Ni layer may be 2000 angstroms to 4000 angstroms. For example, the thickness of the second Ni layer may be 3000 angstroms.

[0117] Illustratively, the thickness of the In layer may be 30,000 angstroms to 80,000 angstroms. For example, the thickness of the In layer may be 50,000 angstroms.

[0118] In the embodiment of the present disclosure, after the two electrodes 30 are manufactured, the preparation method may further include: manufacturing a protective layer 43 on the surface of the passivation layer 41 .

[0119] For example, in the embodiment of the present disclosure, the protective layer 43 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0120] It should be noted that after the protective layer 43 is grown on the surface of the passivation layer 41 , a via hole exposing the electrode 30 may be etched on the surface of the protective layer 43 using a photolithography technique to facilitate electrical connection.

[0121] The third step is to prepare a filling layer 42 on the protective layer 43.

[0122] The leveling layer 42 may be a spin-coated glass layer.

[0123] In the disclosed embodiment, the curing temperature of the SOG layer can be controlled between 150°C and 250°C, and the curing time is 2 hours. This allows the SOG layer to be flexible after being coated on the film surface, but not fully cured. After the LED chip falls onto the circuit board 52, the SOG layer acts as a buffer, preventing it from being damaged during the fall.

[0124] Optionally, the distance between the surface of the filling layer 42 away from the substrate 10 and the end surface of the electrode 30 away from the substrate 10 is 0.3 μm to 0.7 μm.

[0125] Exemplarily, the distance between the surface of the leveling layer 42 away from the substrate 10 and the end surface of the electrode 30 away from the substrate 10 is 0.5 μm.

[0126] The step S12 of forming the plurality of guide grooves 20 may include: etching the epitaxial layer in the region where the guide grooves 20 are required to be etched, so as to carve out the guide grooves 20 .

[0127] A dry etching process is used to etch the chip using a gas mixture of Cl2, BCl3, and O2. The etcher's upper power is controlled at 600W, and its lower power is controlled at 300W. Etching proceeds from the chip's substrate 10 side toward the chip's electrode 30 side, thereby etching the flow grooves 20 on the first surface 101. During the etching process, the proportion of O2 in the gas mixture, i.e., the oxygen content introduced, is gradually increased, thereby gradually enlarging the cross-section of the flow grooves 20.

[0128] Optionally, the width of the guide groove 20 at the end close to the first surface 101 is 8 μm to 12 μm, and the width of the guide groove 20 at the end away from the first surface 101 is 3 μm to 7 μm.

[0129] Exemplarily, the width of the guide groove 20 at the end close to the first surface 101 is 10 μm, and the width of the guide groove 20 at the end away from the first surface 101 is 5 μm.

[0130] Optionally, the cross section of the guide groove 20 is arc-shaped or V-shaped.

[0131] For example, Figure 2 As shown, the cross section of the guide groove 20 is V-shaped, wherein the angle between two lines of the cross section of the guide groove 20 exceeds 90 degrees.

[0132] For example, Figure 4 As shown, the cross section of the guide groove 20 is an arc.

[0133] Optionally, the depth of the guide groove 20 at its maximum depth is not greater than 3 μm, and the depth of the guide groove 20 at its minimum depth is not less than 1 μm.

[0134] Optionally, the orthographic projection of the epitaxial layer 2 on the surface of the substrate 10 is a rectangle, and the guide groove 20 is located at a side or corner of the rectangle.

[0135] For example, Figure 2 As shown, the orthographic projection of the epitaxial layer 2 on the surface of the substrate 10 is a rounded rectangle, the guide grooves 20 are located at the rounded corners of the rounded rectangle, and each rounded corner of the rounded rectangle has a plurality of guide grooves 20 distributed at intervals.

[0136] Finally, the sapphire can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light-emitting diode chip is obtained by testing.

[0137] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light-emitting diode chip, characterized in that: The light-emitting diode chip has a first surface (101), a second surface (102) and a plurality of side surfaces, wherein the first surface (101) and the second surface (102) are opposite to each other, and the first surface (101) is the surface where the electrode (30) is located, and the plurality of side surfaces respectively connect the first surface (101) and the second surface (102), and the side surfaces have a plurality of guide grooves (20), and the plurality of guide grooves (20) are symmetrically distributed about the axis of the positive projection on the first surface (101), and the guide grooves (20) extend from the first surface (101) to the second surface (102), and the cross-sectional area of ​​the guide grooves (20) gradually decreases from one end to the other end, and the cross-sectional area of ​​the guide groove (20) at one end close to the first surface (101) is greater than the cross-sectional area at one end away from the first surface (101), and the cross-sectional area of ​​the guide groove (20) is the area of ​​the cross section of the guide groove (20) parallel to the first surface (101).

2. The light-emitting diode chip according to claim 1, characterized in that The width of the guide groove (20) at the end close to the first surface (101) is 8 μm to 12 μm, and the width of the guide groove (20) at the end away from the first surface (101) is 3 μm to 7 μm.

3. The light-emitting diode chip according to claim 1, characterized in that The depth of the guide groove (20) at its maximum depth is not greater than 3 μm, and the depth at its minimum depth is not less than 1 μm.

4. The light-emitting diode chip according to any one of claims 1 to 3, characterized in that: The first surface (101) and the second surface (102) are rounded rectangles, and the guide groove (20) is located at the rounded corners of the rounded rectangles.

5. The light-emitting diode chip according to any one of claims 1 to 3, characterized in that: The cross section of the guide groove (20) is arc-shaped or V-shaped.

6. The light-emitting diode chip according to any one of claims 1 to 3, characterized in that: The guide groove (20) extends from the first surface (101) to the second surface (102).

7. The light-emitting diode chip according to any one of claims 1 to 3, characterized in that: The light-emitting diode chip comprises: a substrate (10), an epitaxial layer (2), a filling layer (42), and the electrode (30); The epitaxial layer (2) is located on the substrate (10), the filling layer (42) and the electrode (30) are located on a surface of the epitaxial layer (2) away from the substrate (10), and the filling layer (42) has a via hole exposing the electrode (30).

8. The light-emitting diode chip according to claim 7, characterized in that: The electrode (30) is 0.3 μm to 0.7 μm higher than the leveling layer (42).

9. A method for preparing a light emitting diode chip, characterized in that: The preparation method comprises: Manufacturing a light-emitting diode chip, wherein the light-emitting diode chip has a first surface, a second surface, and a plurality of side surfaces, wherein the first surface is opposite to the second surface, the first surface is a surface where an electrode is located, and the plurality of side surfaces respectively connect the first surface and the second surface; A plurality of guide grooves are made on the side surface, and the plurality of guide grooves are symmetrically distributed in the axis of their projections on the first surface. The guide grooves extend from the first surface to the second surface, and the cross-sectional area of ​​the guide grooves gradually decreases from one end to the other end. The cross-sectional area of ​​the guide groove at one end close to the first surface is larger than the cross-sectional area at the end away from the first surface. The cross-sectional area of ​​the guide groove is the area of ​​the cross section of the guide groove parallel to the first surface.

10. The preparation method according to claim 9, characterized in that The manufacturing of the guide groove on the side surface comprises: A mixed gas is introduced to dry-etch the first surface to form the guide groove, wherein the mixed gas includes Cl2, BCl3 and O2. When etching the guide groove, the proportion of O2 in the mixed gas is gradually increased.

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