A low-power bidirectional data isolation circuit

Abstract

The present invention relates to the technical field of communication level conversion. To address the technical problems of high cost and power consumption in communication level conversion in the prior art, the present invention aims to provide a low-power bidirectional data isolation circuit, comprising a transistor Q1, a transistor Q7, an NMOS transistor Q2, an NMOS transistor Q3, an NMOS transistor Q4, and an NMOS transistor Q5, each of which is directly or through a resistor or diode connected to the positive power supply, clock signal, data signal, and negative power supply of a high-voltage side logic unit, and is connected to the positive power supply, clock signal, data signal, and negative power supply of a low-voltage side logic unit. By using a relatively small number of common resistors, transistors, and NMOS transistors, communication isolation between two high voltage differences can be achieved, effectively solving the problems of high cost caused by using an isolation chip, high power consumption during BMS operation, and inconsistent power consumption of the high- and low-voltage side logic units.

Description

Technical Field

[0001] The present invention relates to the technical field of communication level conversion, and in particular to a low-power bidirectional data isolation circuit. Background Art

[0002] With the widespread application of lithium batteries in electric motorcycles and electric bicycles, the battery voltage used has been continuously increasing from 12V, 24V, 36V, 48V, and 72V. However, the voltage acquisition IC of a single chip available on the market can accommodate 4 to 16 cells. When the voltage is higher than 48V, more chips must be used. When more chips are used, there are problems with inter-chip communication. Inter-chip communication on PCBs usually uses I2C communication, with a communication rate of 10k to 100kbps.

[0003] When more than two chips are used, the voltage difference between the two chips reaches more than 42V because they do not share a common ground. Therefore, optical isolation or magnetic isolation is usually used. However, using this method has the following advantages: first, the cost is high; second, it will cause the BMS to consume too much power when working; third, the power consumption of the two ICs of the high-voltage and low-voltage logic units is inconsistent, which will cause the power consumption of the IC of the high-voltage logic unit and the IC of the low-voltage logic unit to be different, eventually resulting in a voltage difference, capacity degradation of the battery pack, and affecting user use. Summary of the Invention

[0004] In order to solve the technical problems related to high cost and power consumption in existing communication level conversion, the present invention provides a low-power bidirectional data isolation circuit.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] A low-power bidirectional data isolation circuit includes a transistor Q1, a transistor Q7, an NMOS transistor Q2, an NMOS transistor Q3, an NMOS transistor Q4, and an NMOS transistor Q5, as well as an interface VCC for connecting to the positive power supply of a high-voltage side logic unit, a high-voltage side communication interface for connecting to the clock signal or data signal of the high-voltage side logic unit, an interface HGND for connecting to the negative power supply of the high-voltage side logic unit, an interface VCC_MCU for connecting to the positive power supply of the low-voltage side logic unit, a low-voltage side communication interface for connecting to the clock signal or data signal of the low-voltage side logic unit, and an interface GND for connecting to the negative power supply of the low-voltage side logic unit. The transistor Q1 and the transistor Q7 are PNP transistors; the base of the transistor Q1 is used to connect to the high-voltage side communication signal interface, the emitter of the transistor Q1 is connected to the interface VCC via a resistor R2, and the interface VCC is connected to the base of the transistor Q1. A pull-up resistor R5 is connected between the transistors. The collector of the transistor Q1 is connected to the GND interface via resistors R12 and R7 in sequence. The VCC interface is connected to the drain of the NMOS transistor Q3 via resistors R1 and R3 in sequence, and the source of the NMOS transistor Q3 is connected to the GND interface. The drain of the NMOS transistor Q2 is connected to the emitter of the transistor Q1, the source of the NMOS transistor Q2 is connected to the HGND interface, and the gate of the NMOS transistor Q2 is connected to the drain of the NMOS transistor Q3 via resistor R3. The VCC_MCU interface is connected to the GND interface via resistors R9 and R4 in sequence. The series circuit formed by resistors R9 and R4 is used to provide a voltage divider for the gate of the NMOS transistor Q3. A resistor R4 is connected between the drain and source of the NMOS transistor Q4, and a resistor R6 is connected between the gate and source of the NMOS transistor Q4. The gate of the NMOS transistor Q4 is connected to the collector of the transistor Q7, and the source of the NMOS transistor Q4 is connected to the GND interface. The base of transistor Q7 is connected to the VCC_MCU interface through resistors R10 and R11, respectively. The base of transistor Q7 is also connected to the low-voltage communication signal interface through resistor R10. The drain of NMOS transistor Q5 is connected to the VCC interface through resistor R8. The drain of NMOS transistor Q5 is connected to the emitter of transistor Q7, and the source of NMOS transistor Q5 is connected to the GND interface. Resistor R7 is connected between the gate and source of NMOS transistor Q5. The series circuit formed by resistors R7 and R12 provides a voltage divider for the gate of NMOS transistor Q5. The high-voltage side logic unit is isolated from the low-voltage side logic unit. The unique component connection method and conventional materials effectively utilize material properties, achieving high performance at a low cost, reducing costs and solving power consumption issues.

[0007] Furthermore, a diode D1 is connected in parallel between the base and emitter of the transistor Q1. The anode of the diode D1 is connected to the base of the transistor Q1, and the cathode of the diode D1 is connected to the emitter of the transistor Q1. The diode D1 is used to protect the transistor Q1 and prevent the base and emitter of the transistor from being broken down during the negative half cycle.

[0008] Furthermore, a voltage regulator tube Z1 is connected between the source and gate of the NMOS tube Q2. The anode of the voltage regulator tube Z1 is connected to the source, and the cathode of the voltage regulator tube Z1 is connected to the gate. This prevents overvoltage breakdown between the gate and the source, prevents excessive current change rate of the gate, and accelerates the cutoff of the MOS tube when it switches from on to off.

[0009] Furthermore, a diode D2 is included, the anode of the diode D2 is connected to the base of the transistor Q7 through the resistor R10, and the cathode of the diode D2 is connected to the emitter of the transistor Q7. The diode D2 is used to protect the transistor Q7 and prevent the base and emitter of the transistor Q7 from being broken down in the negative half cycle.

[0010] Furthermore, it also includes an NMOS tube Q15 for improving the switching speed of the NMOS tube Q4. The gate of the NMOS tube Q15 is connected to the low-voltage side communication interface, the drain of the NMOS tube Q15 is connected to the gate of the NMOS tube Q4, and the source of the NMOS tube Q15 is connected to the source of the NMOS tube Q4.

[0011] The beneficial effects brought about by implementing the embodiments of the present invention are:

[0012] By using fewer common resistors, transistors, and NMOS transistors, communication isolation between two devices with a high voltage difference can be achieved, effectively resolving the high cost, high power consumption, and inconsistent power consumption issues associated with using isolation chips. Furthermore, the diode protects the transistor, and the Zener diode protects the NMOS transistor, improving operational stability. NMOS transistor 15 achieves the same switching speed as NMOS transistor Q4, adapting to higher-speed communication signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A logic block diagram for use provided by an embodiment of the present invention;

[0014] Figure 2 A data signal isolation circuit diagram provided by an embodiment of the present invention;

[0015] Figure 3 A clock signal isolation circuit diagram provided by an embodiment of the present invention.

[0016] In the figure: G is the gate of the NMOS tube; S is the source of the NMOS tube; D is the drain of the NMOS tube; B is the base of the transistor; C is the collector of the transistor; E is the emitter of the transistor; VCC is the interface for connecting the positive power supply of the high-voltage side logic unit; SCL is the interface for connecting the clock signal of the high-voltage side logic unit; SDA is the interface for connecting the data signal of the high-voltage side logic unit; HGND is the interface for connecting the negative power supply of the high-voltage side logic unit; VCC_MCU is the interface for connecting the positive power supply of the low-voltage side logic unit; SCL_MCU is the interface for connecting the clock signal of the low-voltage side logic unit; SDA_MCU is the interface for connecting the data signal of the low-voltage side logic unit; GND is the interface for connecting the negative power supply of the low-voltage side logic unit. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0018] See Figure 1 , Figure 1 A logic block diagram is provided for use in an embodiment of the present invention. The present invention provides a low-power bidirectional data isolation circuit, wherein the two ends of the circuit are respectively connected to a high-voltage side logic unit and a low-voltage side logic unit for isolation and matching of logic levels. The circuit includes a data signal isolation circuit and a clock signal isolation circuit.

[0019] See Figure 2 , Figure 2 The data signal isolation circuit provided in the embodiment of the present invention includes a transistor Q1, a transistor Q7, an NMOS transistor Q2, an NMOS transistor Q3, an NMOS transistor Q4 and an NMOS transistor Q5. The transistor Q1 and the transistor Q7 are PNP transistors.

[0020] The base of the transistor Q1 is connected to the interface SDA, and the emitter of the transistor Q1 is connected to the interface VCC through the resistor R2. A pull-up resistor R5 is connected between the interface VCC and the base of the transistor Q1. A diode D1 is connected in parallel between the base and emitter of the transistor Q1. The anode of the diode D1 is connected to the base of the transistor Q1, and the cathode of the diode D1 is connected to the emitter of the transistor Q1. The diode D1 is used to protect the transistor Q1 to prevent the base and emitter of the transistor from being broken down during the negative half cycle. The collector of the transistor Q1 is connected to GND through the resistor R12 and the resistor R7 in sequence;

[0021] Interface VCC is connected to the drain of NMOS transistor Q3 through resistors R1 and R3 in sequence. The source of NMOS transistor Q3 is connected to GND. The series circuit composed of resistors R1 and R3 is used to provide voltage division for the gate of NMOS transistor Q2.

[0022] The drain of the NMOS tube Q2 is connected to the emitter of the transistor Q1, the source of the NMOS tube Q2 is connected to HGND, the gate of the NMOS tube Q2 is connected to the drain of the NMOS tube Q3 through the resistor R3, and a voltage regulator tube Z1 is connected between the source and the gate of the NMOS tube Q2. The anode of the voltage regulator tube Z1 is connected to the source, and the cathode of the voltage regulator tube Z1 is connected to the gate to prevent overvoltage breakdown between the gate and the source, and to prevent excessive current change rate of the gate, so that the NMOS tube is turned off faster when it switches from on to off.

[0023] The interface VCC_MCU is connected to the interface GND through resistors R9 and R4 in sequence. The series circuit formed by resistors R9 and R4 is used to provide a voltage divider for the gate of the NMOS transistor Q3. Specifically, the interface VCC_MCU is connected to the first end of the resistor R9, the second end of the resistor R9 is connected to the first end of the resistor R4, and the second end of the resistor R4 is connected to the interface GND; the second end of the resistor R9 is connected to the gate of the NMOS transistor Q3.

[0024] The drain and source of the NMOS transistor Q4 are connected in parallel with the resistor R4. Specifically, the drain of the NMOS transistor Q4 is connected to the first end of the resistor R4, and the source of the NMOS transistor Q4 is connected to the second end of the resistor R4.

[0025] The gate and source of the NMOS transistor Q4 are connected in parallel with the resistor R6. Specifically, the gate of the NMOS transistor Q4 is connected to the first end of the resistor R6, and the source of the NMOS transistor Q4 is connected to the second end of the resistor R6.

[0026] The gate of NMOS transistor Q4 is also connected to the collector of transistor Q7;

[0027] The source of the NMOS tube Q4 is connected to the interface GND.

[0028] The base of transistor Q7 is connected to the interface VCC_MCU through resistors R10 and R11 in sequence;

[0029] The base of transistor Q7 is connected to the interface SDA_MCU through resistor R10;

[0030] A diode D2 is also included. The anode of the diode D2 is connected to the base of the transistor Q7 through the resistor R10, and the cathode of the diode D2 is connected to the emitter of the transistor Q7. The diode D2 is used to protect the transistor Q7 and prevent the base and emitter of the transistor Q7 from being broken down during the negative half cycle.

[0031] The drain of the NMOS transistor Q5 is connected to the interface VCC through the resistor R8. The drain of the NMOS transistor Q5 is connected to the emitter of the transistor Q7. The source of the NMOS transistor Q5 is connected to the interface GND. The gate of the NMOS transistor Q5 is connected to the interface GND through the resistor R7. The series circuit composed of the resistors R7 and R12 is used to provide a divided voltage for the gate of the NMOS transistor Q5.

[0032] It also includes an NMOS transistor Q15 for increasing the switching speed of the NMOS transistor Q4. The gate of the NMOS transistor Q15 is connected to the low-voltage side communication interface, the drain of the NMOS transistor Q15 is connected to the gate of the NMOS transistor Q4, and the source of the NMOS transistor Q15 is connected to the source of the NMOS transistor Q4.

[0033] Working principle:

[0034] NMOS tube Q4, transistor Q7 and diode D2 realize the level conversion of low-level IC, NMOS tube Q3 realizes the level transmission to the high-level chip, and R11 is the level pull-up resistor of the low-level IC;

[0035] When SDA_MCU is at a low level, transistor Q7 is turned on, so that the gate of NMOS transistor Q4 obtains the conduction voltage. NMOS transistor Q4 is turned on, so that the gate of NMOS transistor Q3 is connected to GND, and NMOS transistor Q3 is cut off, so that resistor R3 is suspended relative to GND. NMOS transistor Q2 cannot obtain voltage division, so NMOS transistor Q2 is cut off, resulting in VCC and HGND being disconnected, there is no current loop, and SDA is actually without voltage, so SDA is at a low level;

[0036] When SDA_MCU is high, transistor Q7 is turned off, preventing the gate of NMOS Q4 from receiving a turn-on voltage. This turns off NMOS Q4, allowing the gate of NMOS Q3 to receive a turn-on voltage from the voltage divider circuit formed by resistors R9 and R4. This turns on NMOS Q3, connecting resistor R3 to GND. This voltage divider circuit forms the series voltage divider circuit of resistors R1 and R3, causing NMOS Q2 to conduct, forming a current loop and maintaining SDA at a high level. When SDA_MCU is high, NMOS Q15 quickly lowers the gate voltage of NMOS Q4, increasing switching speed and accommodating higher communication rates.

[0037] Q1, Q2 and D1 realize the level conversion of the high-level chip, Q5 realizes the level state conversion of the high-level chip to the low-level chip, and R5 realizes the pull-up function of the I2C interface of the high-level chip;

[0038] When SDA is at a low level, transistor Q1 is turned on, and the gate of NMOS transistor Q5 obtains a turn-on voltage on the voltage divider circuit composed of resistors R12 and R7, and NMOS transistor Q5 is turned on. In this embodiment, resistors R9, R8, and R11 have the same resistance value, for example, 3.3k ohms. At this time, SDA_MCU is at a low level;

[0039] When SDA is at a high level, transistor Q1 is turned off, and the gate of NMOS transistor Q5 cannot obtain the conduction voltage in the voltage divider circuit composed of resistors R12 and R7. NMOS transistor Q5 is turned off. In this embodiment, resistors R9, R8 and R11 have the same resistance value, for example, 3.3K ohms. At this time, SDA_MCU is at a high level.

[0040] The withstand voltage values ​​of Q1, Q3, and Q5 in the circuit determine the isolation voltage amplitude of the circuit. By changing the withstand voltage values ​​of these three components, a higher level of isolation function can be obtained.

[0041] See Figure 3 , Figure 2 The clock signal isolation circuit provided in an embodiment of the present invention includes a transistor Q9, a transistor Q13, an NMOS transistor Q2, an NMOS transistor Q8, an NMOS transistor Q10, an NMOS transistor Q12 and an NMOS transistor Q14, wherein the transistor Q9 and the transistor Q13 are PNP transistors.

[0042] The base of the transistor Q9 is connected to the interface SCL, and the emitter of the transistor Q9 is connected to the interface VCC through the resistor R15. A pull-up resistor R13 is connected between the interface VCC and the base of the transistor Q9. A diode D3 is connected in parallel between the base and emitter of the transistor Q9. The anode of the diode D3 is connected to the base of the transistor Q9, and the cathode of the diode D3 is connected to the emitter of the transistor Q9. The diode D3 is used to protect the transistor Q9 to prevent the base and emitter of the transistor from being broken down during the negative half cycle. The collector of the transistor Q9 is connected to the interface GND through the resistor R24 ​​and the resistor R19 in sequence;

[0043] The interface VCC is connected to the drain of the NMOS transistor Q10 through resistors R14 and R16 in sequence. The source of the NMOS transistor Q10 is connected to the interface GND. The series circuit composed of resistors R14 and R16 is used to provide a divided voltage for the gate of the NMOS transistor Q8.

[0044] The drain of the NMOS transistor Q8 is connected to the emitter of the transistor Q9, the source of the NMOS transistor Q8 is connected to HGND, and the gate of the NMOS transistor Q8 is connected to the drain of the NMOS transistor Q10 through the resistor R16. A voltage regulator tube Z2 is connected between the source and the gate of the NMOS transistor Q8. The anode of the voltage regulator tube Z2 is connected to the source, and the cathode of the voltage regulator tube Z2 is connected to the gate. This prevents overvoltage breakdown between the gate and the source, prevents excessive current change rate of the gate, and accelerates the NMOS tube's shutdown when it switches from on to off.

[0045] The interface VCC_MCU is connected to the interface GND through resistors R21 and R17 in sequence. The series circuit formed by resistors R21 and R17 is used to provide a voltage divider for the gate of the NMOS transistor Q10. Specifically, the interface VCC_MCU is connected to the first end of the resistor R21, the second end of the resistor R21 is connected to the first end of the resistor R17, and the second end of the resistor R17 is connected to the interface GND; the second end of the resistor R21 is connected to the gate of the NMOS transistor Q10.

[0046] The drain and source of the NMOS transistor Q11 are connected in parallel with the resistor R17. Specifically, the drain of the NMOS transistor Q11 is connected to the first end of the resistor R17, and the source of the NMOS transistor Q11 is connected to the second end of the resistor R17.

[0047] The gate and source of the NMOS transistor Q11 are connected in parallel with the resistor R18. Specifically, the gate of the NMOS transistor Q11 is connected to the first end of the resistor R18, and the source of the NMOS transistor Q11 is connected to the second end of the resistor R18.

[0048] The gate of the NMOS transistor Q11 is also connected to the collector of the transistor Q13;

[0049] The source of the NMOS transistor Q11 is connected to the interface GND.

[0050] The base of transistor Q13 is connected to the interface VCC_MCU through resistors R22 and R23 in sequence;

[0051] The base of transistor Q13 is connected to the interface SCL_MCU through resistor R22;

[0052] A diode D4 is also included. The anode of the diode D4 is connected to the base of the transistor Q13 through the resistor R10, and the cathode of the diode D4 is connected to the emitter of the transistor Q13. The diode D4 is used to protect the transistor Q13 and prevent the base and emitter of the transistor Q13 from being broken down during the negative half cycle.

[0053] The drain of the NMOS transistor Q12 is connected to the interface VCC_MCU through the resistor R20. The drain of the NMOS transistor Q12 is connected to the emitter of the transistor Q13. The source of the NMOS transistor Q12 is connected to GND. The gate of the NMOS transistor Q12 is connected to GND through the resistor R19. The series circuit formed by the resistors R19 and R24 is used to provide a voltage divider for the gate of the NMOS transistor Q12.

[0054] The gate of the NMOS tube Q14 is connected to SCL_MCU, the drain of the NMOS tube Q14 is connected to the collector of the transistor Q13, and the source of the NMOS tube Q14 is connected to GND.

[0055] Working principle:

[0056] NMOS tube Q11, transistor Q13 and diode D4 realize the level conversion of low-level IC, NMOS tube Q10 realizes the level transmission to the high-level chip, and R23 is the level pull-up resistor of the low-level IC;

[0057] When SCL_MCU is at a low level, NMOS transistor Q14 is turned off and transistor Q13 is turned on, so that the gate of NMOS transistor Q11 obtains the on-voltage. NMOS transistor Q11 is turned on, so that the gate of NMOS transistor Q10 is connected to GND. NMOS transistor Q10 is turned off, so that resistor R16 is suspended relative to GND. NMOS transistor Q8 cannot obtain voltage division, so NMOS transistor Q8 is turned off, resulting in the loop between VCC and HGND being disconnected. There is no current loop, and SCL is actually without voltage, so SCL is at a low level.

[0058] When SCL_MCU is at a high level, NMOS transistor Q14 is turned on and transistor Q13 is turned off, so that the gate of NMOS transistor Q11 cannot obtain the turn-on voltage. NMOS transistor Q11 is turned off, so that the gate of NMOS transistor Q10 obtains the turn-on voltage from the voltage divider circuit formed by resistors R17 and R21. NMOS transistor Q10 is turned on, so that resistor R16 is connected to GND. NMOS transistor Q8 obtains the divided voltage from the series voltage divider circuit formed by resistors R14 and R16, so that NMOS transistor Q8 is turned on, forming a current loop, so SCL is at a high level.

[0059] Q8, Q9 and D3 realize the level conversion of the high-level chip, Q12 realizes the conversion of the level state of the high-level chip to the low-level chip, and R13 realizes the pull-up function of the I2C interface of the high-level chip;

[0060] When SCL is at a low level, transistor Q9 is turned on, and the gate of NMOS transistor Q12 obtains a turn-on voltage on the voltage divider circuit composed of resistors R24 and R19, and NMOS transistor Q12 is turned on. In this embodiment, resistors R20, R21, and R23 have the same resistance value, for example, 3.3k ohms. At this time, SCL_MCU is at a low level;

[0061] When SCL is at a high level, transistor Q9 is turned off, and the gate of NMOS transistor Q12 cannot obtain the conduction voltage in the voltage divider circuit composed of resistors R24 and R19, so NMOS transistor Q12 is turned off. In this embodiment, resistors R20, R21 and R23 have the same resistance value, for example, 3.3K ohms. At this time, SCL_MCU is at a high level.

[0062] The withstand voltage values ​​of Q9, Q10, and Q12 in the circuit determine the isolation voltage amplitude of the circuit. By changing the withstand voltage values ​​of these three components, a higher level of isolation function can be obtained.

[0063] The circuit provided by the present invention uses a large number of discrete components and is suitable for application scenarios with a transmission rate of no more than 100kbps. Since the power supply of the power pin on the I2C of the high-level IC is derived from the total voltage of the battery pack, when the I2C is working, its level is relative to the GND ground of the low-level chip, that is, the power consumption of the two ICs is taken from the total power supply of the battery pack, so there will be no inconsistency in power consumption. At the same time, when the I2C communication interface is in an idle state, its interface is at a high level, and no ground loop is formed in the circuit, and there is no power consumption, which saves power switching in the idle state. The BMS is connected to this functional circuit to realize the function of sharing the ground with the low-level chip and communicating with the high-level chip at the same time, without affecting the low-level chip's collection of the battery pack's charge and discharge current.

[0064] In practical applications, the voltage difference between the high-voltage side of SCL and SDA and the low-voltage side of MCU_SCL and MCU_SDA can exceed 60V. The isolation voltage is solely dependent on the withstand voltage of Q1, Q3, Q9, and Q10. Replacing components with higher withstand voltages can achieve higher levels of isolation, effectively solving the problem of level isolation. Both pins feature bidirectional level transmission: when SCL is high relative to HGND, MCU_SCL is also high relative to GND. Conversely, when MCU_SCL is high, SCL is also high. The same applies to the low-level side, thus enabling efficient digital level transmission. The level conversion relationship between SDA and MCU_SDA is the same as that between SCL and MCU_SCL. Furthermore, when isolating battery packs in series, both VCC and VCC_MCU are set to the highest voltage in the battery pack, eliminating power consumption differences and voltage differences in the battery pack caused by level isolation. When used for electrical isolation, the communicating ends can be powered independently without affecting each other. Level transmission is achieved through voltage signal transmission, resulting in low power consumption. The drive current of the isolation chip exceeds mA, achieving a transmission power consumption of less than 200uA. By using a relatively small number of common resistors, transistors, diodes, and small-signal MOS transistors, I2C communication isolation can be achieved between two ICs with a voltage difference of up to 65V. This effectively solves the problems of high cost of using isolation chips, high power consumption during BMS operation, and inconsistent power consumption of logic units on the high and low voltage sides. It also solves the material supply problem during mass production. The components used are all common components, which are easy to purchase in batches.

[0065] This article uses I2C as an example to illustrate its operation. I2C has two communication lines: a clock signal line and a data signal line. The SCL and SDA interfaces can be summarized as high-voltage side communication interfaces, while the SCL_MCU and SDA_MCU interfaces can be summarized as low-voltage side communication interfaces. This circuit is not only suitable for I2C communication, but also for other types of communication.

[0066] It can be seen that the beneficial effects brought about by implementing the embodiments of the present invention are:

[0067] By using fewer general resistors, transistors and NMOS tubes, communication isolation between two high voltage differences can be achieved, which can effectively solve the problems of high cost of using isolation chips, large power consumption when BMS is working, and inconsistent power consumption of logic units on the high and low voltage sides; the components used are all general components, and materials are easy to purchase during mass production; the diode can protect the transistor, and the voltage regulator can protect the NMOS tube, thereby improving the stability of operation; the NMOS tube 15 increases the switching speed of the NMOS tube Q4 and can adapt to higher speed communication signals.

[0068] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low-power bidirectional data isolation circuit, characterized in that: It includes transistors Q1, Q7, NMOS transistors Q2, Q3, Q4, and Q5, as well as an interface VCC for connecting to the positive power supply of the high-voltage side logic unit, a high-voltage side communication interface for connecting to the clock signal or data signal of the high-voltage side logic unit, an interface HGND for connecting to the negative power supply of the high-voltage side logic unit, an interface VCC_MCU for connecting to the positive power supply of the low-voltage side logic unit, a low-voltage side communication interface for connecting to the clock signal or data signal of the low-voltage side logic unit, and an interface GND for connecting to the negative power supply of the low-voltage side logic unit. The transistors Q1 and Q7 are PNP transistors. The base of the transistor Q1 is used to be connected to the high-voltage side communication signal interface, the emitter of the transistor Q1 is connected to the interface VCC through the resistor R2, a pull-up resistor R5 is connected between the interface VCC and the base of the transistor Q1, and the collector of the transistor Q1 is connected to the interface GND through the resistor R12 and the resistor R7 in sequence; The interface VCC is connected to the drain of the NMOS transistor Q3 through the resistor R1 and the resistor R3 in sequence, and the source of the NMOS transistor Q3 is connected to the interface GND; The drain of the NMOS transistor Q2 is connected to the emitter of the transistor Q1, the source of the NMOS transistor Q2 is connected to the interface HGND, and the gate of the NMOS transistor Q2 is connected to the drain of the NMOS transistor Q3 via the resistor R3; The interface VCC_MCU is connected to the interface GND via resistors R9 and R4 in sequence. The series circuit formed by resistors R9 and R4 is used to provide a divided voltage to the gate of the NMOS transistor Q3. A resistor R4 is connected between the drain and source of the NMOS transistor Q4, a resistor R6 is connected between the gate and source of the NMOS transistor Q4, the gate of the NMOS transistor Q4 is connected to the collector of the transistor Q7, and the source of the NMOS transistor Q4 is connected to the interface GND; The base of the transistor Q7 is connected to the interface VCC_MCU through the resistor R10 and the resistor R11 in sequence, and the base of the transistor Q7 is connected to the low-voltage side communication signal interface through the resistor R10; The drain of the NMOS transistor Q5 is connected to the interface VCC through the resistor R8, the drain of the NMOS transistor Q5 is connected to the emitter of the transistor Q7, the source of the NMOS transistor Q5 is connected to the interface GND, and a resistor R7 is connected between the gate and source of the NMOS transistor Q5. The series circuit composed of the resistors R7 and R12 is used to provide a divided voltage for the gate of the NMOS transistor Q5; It also includes an NMOS tube Q15 for increasing the switching speed of the NMOS tube Q4. The gate of the NMOS tube Q15 is connected to the low-voltage side communication interface, the drain of the NMOS tube Q15 is connected to the gate of the NMOS tube Q4, and the source of the NMOS tube Q15 is connected to the source of the NMOS tube Q4.

2. A low-power bidirectional data isolation circuit according to claim 1, characterized in that: The device further comprises a diode D1 for protecting the transistor Q1 , wherein the anode of the diode D1 is connected to the base of the transistor Q1 , and the cathode of the diode D1 is connected to the emitter of the transistor Q1 .

3. The low-power bidirectional data isolation circuit according to claim 2, characterized in that: The device further comprises a voltage regulator tube Z1 for protecting the NMOS tube Q2 , wherein the anode of the voltage regulator tube Z1 is connected to the source of the NMOS tube Q2 , and the cathode of the voltage regulator tube Z1 is connected to the gate of the NMOS tube Q2 .

4. The low-power bidirectional data isolation circuit according to claim 3, characterized in that: The device further includes a diode D2 for protecting the transistor Q7 , wherein the anode of the diode D2 is connected to the base of the transistor Q7 via a resistor R10 , and the cathode of the diode D2 is connected to the emitter of the transistor Q7 .

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