Low-loss wire using bridge conductors

Abstract

A technique for designing and manufacturing a quantum circuit for quantum applications is proposed, the quantum circuit including a coplanar waveguide (CPW). With respect to the CPW, a center conductor and two return conductor lines may be formed on a dielectric substrate, wherein one return conductor line is on each side of the center conductor and is separated from the center conductor by a spacer. The center conductor may have a bridge portion that may be raised a desired distance above the substrate and a base conductor portion that is located between the bridge portions and in contact with the surface of the substrate; and / or a portion of the substrate below the bridge portion of the center conductor may be removed so that the bridge portion, whether raised or not, may be a desired distance above the surface of the remaining substrate, and the base conductor portion may be in contact with other portions of the substrate surface that have not been removed.

Description

Technical Field

[0001] The subject disclosure relates to quantum circuits and, more particularly, to low-loss wires using bridge conductors. Background Art

[0002] Quantum computing uses quantum physics technology rather than transistor-based binary digital technology to encode and process information. Quantum computing devices use quantum bits (also called qubits) that operate according to the laws of quantum physics and can exhibit phenomena such as superposition and entanglement. The superposition principle of quantum physics allows a qubit to be in a state that partially represents a value of "1" and a value of "0" at the same time. The entanglement principle of quantum physics allows qubits to be correlated with each other so that the combined state of the qubits cannot be decomposed into a single qubit state. For example, the state of a first qubit may depend on the state of a second qubit. In this way, quantum circuits can use qubits to encode and process information in a way that can be significantly different from transistor-based binary digital technology.

[0003] Regarding the fabrication of quantum circuits, some quantum circuits may utilize coplanar waveguides (CWPs) as transmission lines for quantum applications. A CWP may include a transmission line, which may be a center conductor (e.g., a conductor line) that may be formed on a dielectric substrate, and two return conductor lines, which may be formed on the dielectric substrate, with one return conductor line on each side of the center conductor and separated from the center conductor by a relatively small space. CWPs may be used to transmit microwave frequency signals for quantum applications. However, CPWs may have undesirable energy losses (e.g., microwave losses) in dielectric substrates.

[0004] A conventional approach to addressing this energy loss in the dielectric substrate is to perform a partial substrate etching of portions of the substrate near the space between the center conductor and the loop conductor of the CWP. However, even with aggressive or deep etching of those portions of the substrate near the space, there may still be a significant and undesirable amount of energy loss in the dielectric substrate. These and other deficiencies of conventional fabrication of quantum circuits can result in inefficiencies and / or inefficient circuits and / or inefficient performance of the quantum circuits. Summary of the invention

[0005] An overview is presented below to provide a basic understanding of one or more embodiments of the disclosed subject matter. This overview is not intended to identify key or important elements, or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to a more detailed description presented later. In one or more embodiments described herein, systems, devices, structures, computer-implemented methods, apparatus, and / or computer program products are provided that can assist in forming electronic devices including spiral conductive structures.

[0006] According to one embodiment, a device includes a substrate component. The device also includes a conductor component, the conductor component including a bridging portion disposed over a portion of the substrate component, wherein a gap of a defined distance is formed between the bridging portion of the conductor component and a surface of the portion of the substrate component facing the bridging portion. The device can have a number of advantages, including that the device can reduce the amount of energy loss associated with the substrate component.

[0007] In some embodiments, the bridging portion may be a first bridging portion, and the conductor component includes a bridging portion group and a base conductor portion, the bridging portion group includes a first bridging portion and a second bridging portion, the base conductor portion being disposed on the substrate component and located between the first bridging portion and the second bridging portion. In certain embodiments, the first bridging portion and the second bridging portion may be elevated above the surface of the base conductor portion and the substrate component to form a plurality of gaps including the gap between the substrate component and the first bridging portion and the second bridging portion. In other embodiments, the portion of the substrate component may be a first portion of the substrate component, the gap may be a first gap, and a first section of the substrate component may be removed to form the first gap between the first portion of the substrate component and a first bridging portion disposed above the first portion of the substrate component, and a second section of the substrate component may be removed to form a second gap between the second portion of the substrate component and a second bridging portion disposed above the second portion of the substrate component. These embodiments of the device can provide a number of advantages, including that the device can reduce energy losses associated with the substrate component by raising the first bridging portion and the second bridging portion above the surface of the substrate component to form a gap, and / or the device can reduce energy losses associated with the substrate component by removing a first section of the substrate component to form a first gap between the first portion of the substrate component and the first bridging portion, and removing a second section of the substrate component to form a second gap between the second portion of the substrate component and the second bridging portion.

[0008] Another embodiment relates to a method comprising forming a substrate. The method also includes forming a conductor path, the conductor path including a bridge conductor portion disposed on a portion of the substrate, wherein a gap of a defined distance is formed between the bridge conductor portion of the conductor path and a surface of the substrate facing the bridge conductor portion. The method can have a number of advantages, including that the method can reduce the amount of energy loss associated with the substrate.

[0009] In some embodiments, the bridging conductor portion may be a first bridging conductor portion, and the method may include forming the conductor line, the conductor line including a bridging conductor portion group and a base conductor portion, the bridging conductor portion group including a first bridging conductor portion and a second bridging conductor portion, the base conductor portion being arranged on the substrate and located between the first bridging conductor portion and the second bridging conductor portion. In some embodiments, the method may include that the first bridging conductor portion and the second bridging conductor portion may be formed at an elevated level relative to the base conductor portion and the substrate surface so as to form a plurality of gaps including the gap between the substrate and the first bridging conductor portion and the second bridging conductor portion. In other embodiments, the portion of the substrate may be a first portion of the substrate, the gap may be a first gap, and the method may further include removing a first section of the substrate to form the first gap between the first portion of the substrate and the first bridging conductor portion arranged above the first portion of the substrate; and removing a second section of the substrate to form a second gap between the second portion of the substrate and the second bridging conductor portion arranged above the second portion of the substrate. These embodiments of the method can provide a number of advantages, including that the method can reduce the amount of energy losses associated with the substrate by forming the first bridging conductor portion and the second bridging conductor portion at an elevated level relative to the surface of the substrate to form these gaps, and / or the method can reduce the amount of energy losses associated with the substrate by removing a first section of the substrate to form the first gap between the first portion of the substrate and the first bridging conductor portion, and removing a second section of the substrate to form the second gap between the second portion of the substrate and the second bridging conductor portion.

[0010] Another embodiment relates to a computer program product that facilitates forming a quantum computing circuit, the computer program product comprising a computer-readable storage medium having program instructions contained therein. The program instructions are executable by a processor to cause the processor to form a substrate comprising a dielectric material to enable creation of circuit components of the quantum computing circuit. The program instructions are also executable by the processor to create a conductor line of the quantum computing circuit, such that the conductor line includes a bridging conductor portion located above a portion of the substrate, wherein a space of a defined distance is formed between the bridging conductor portion of the conductor line and a surface of the substrate facing the bridging conductor portion. The computer program product can have a number of advantages, including that the computer program product can enhance the performance of the quantum computing circuit by reducing the amount of energy loss associated with the substrate.

[0011] In some embodiments, the bridging conductor portion may be a first bridging conductor portion, wherein the portion of the substrate may be a first portion of the substrate, wherein the space may be a first space, and the program instructions may be executed by the processor to cause the processor to: create a conductor line including a bridging conductor portion group and a base conductor portion, the bridging conductor portion group including the first bridging conductor portion and the second bridging conductor portion, the base conductor portion being disposed on the substrate and located between the first bridging conductor portion and the second bridging conductor portion. In some embodiments, the first bridging conductor portion and the second bridging conductor portion may be raised above the surface of the base conductor portion and the substrate to form a plurality of spaces including the first space between the substrate and the first bridging conductor portion and the second bridging conductor portion; or the first portion of the substrate may be removed to form a first space between the first portion of the substrate and the first bridging conductor portion located above the first portion of the substrate, and the second portion of the substrate may be removed to form a second space between the second portion of the substrate and the second bridging conductor portion located above the second portion of the substrate. These embodiments of the computer program product can provide multiple advantages, including that the computer program product can reduce the amount of energy loss associated with the substrate by raising the first bridging conductor portion and the second bridging conductor portion above the surface of the substrate to form a space between the substrate and the first bridging conductor portion and the second bridging conductor portion, and / or the computer program product can reduce the amount of energy loss associated with the substrate by removing a first section of the substrate to form a first space between a first portion of the substrate and the first bridging conductor portion, and removing a second section of the substrate to form a second space between a second portion of the substrate and the second bridging conductor portion.

[0012] According to yet another embodiment, a system may include a memory storing a computer executable component; and a processor operably coupled to the memory to execute the computer executable component. The computer executable component may include a substrate forming component that forms a dielectric substrate as part of a quantum computing circuit. The computer executable component may also include a conductor forming component that forms a conductor component, the conductor component including a bridging conductor portion located above a portion of the dielectric substrate component, wherein a space of a defined distance is formed between the bridging conductor portion of the conductor component and a surface of the dielectric substrate component facing the bridging conductor portion. The system may have a number of advantages, including that the system may reduce the amount of energy loss associated with the dielectric substrate component.

[0013] In some embodiments, the bridging conductor portion may be a first bridging conductor portion, and the conductor forming component may form the conductor component to include a bridging conductor portion group and a base conductor portion, the bridging conductor portion group including the first bridging conductor portion and the second bridging conductor portion, wherein the base conductor portion may be arranged on the dielectric substrate component and located between the first bridging conductor portion and the second bridging conductor portion, and wherein the first bridging conductor portion and the second bridging conductor portion may be at an elevated level compared to surfaces of the base conductor portion and the dielectric substrate component to form a plurality of spaces including the space between the dielectric substrate component and the first bridging conductor portion and the second bridging conductor portion. In other embodiments, the bridging conductor portions may be first bridging conductor portions, the portion of the dielectric substrate component may be a first portion of the dielectric substrate component, and the space may be a first space, wherein the substrate forming component may remove a first section of the dielectric substrate component to form the first portion of the dielectric substrate component, and form a first space between the first portion of the dielectric substrate component and a first bridging conductor portion located above the first portion of the dielectric substrate component, and wherein the substrate forming component may remove a second section of the dielectric substrate component to form a second portion of the dielectric substrate component, and form a second space between the second portion of the dielectric substrate component and a second bridging conductor portion located above the second portion of the dielectric substrate component. These embodiments of the system may provide a number of advantages, including that the system may reduce the amount of energy loss associated with the dielectric substrate component by having the first bridging conductor portion and the second bridging conductor portion be at an elevated level compared to the surface of the dielectric substrate component to form a space, and / or the system may reduce the amount of energy loss associated with the dielectric substrate component by removing a first section of the dielectric substrate component to form a first space between the first section of the dielectric substrate component and the first bridging conductor portion, and removing a second section of the dielectric substrate component to form a second space between the second section of the dielectric substrate component and the second bridging conductor portion.

[0014] Yet another embodiment relates to a computer program product for facilitating creation of a quantum computing circuit, the computer program product comprising a computer-readable storage medium having program instructions embodied therein. The program instructions are executable by a processor to cause the processor to form a dielectric substrate component comprising a dielectric material to enable creation of a circuit component of a quantum computing circuit. The program instructions are also executable by the processor to form a conductor component of a quantum computing circuit, such that the conductor component comprises a bridging portion disposed on a portion of the dielectric substrate component, wherein a gap of a defined distance is formed between the bridging portion of the conductor component and a surface of the substrate component facing the bridging portion, and wherein the conductor component comprises a superconductor material. The computer program product can have a number of advantages, including that the computer program product can enhance the performance of a quantum computing circuit by reducing energy losses associated with the dielectric substrate component.

[0015] In some example embodiments, the bridging portion may be a first bridging portion, the portion of the dielectric substrate component may be a first portion of the dielectric substrate component, the gap may be a first gap, and program instructions may be executed by a processor to cause the processor to form the conductor component including a bridging portion group and a base conductor portion, the bridging portion group including the first bridging portion and the second bridging portion, the base conductor portion being disposed on the dielectric substrate component and between the first bridging portion and the second bridging portion, wherein the first bridging portion and the second bridging portion may be at an elevated level relative to the surface of the base conductor portion and the dielectric substrate component to form a plurality of gaps including a first gap between the dielectric substrate component and the first bridging portion and the second bridging portion, or wherein a first section of the dielectric substrate component may be etched away to form a first gap between the first portion of the dielectric substrate component and the first bridging portion disposed above the first portion of the dielectric substrate component, and a second section of the dielectric substrate component may be etched away to form a second gap between the second portion of the dielectric substrate component and the second bridging portion disposed on the second bridging portion of the dielectric substrate component. These embodiments of the computer program product may provide a number of advantages, including that the computer program product may reduce energy losses associated with the dielectric substrate component by causing the first bridging portion and the second bridging portion to be at elevated levels relative to a surface of the dielectric substrate component to form a gap, and / or by causing a first section of the dielectric substrate component to be etched away to form a first gap between a first portion of the dielectric substrate component and the first bridging portion, and causing a second section of the dielectric substrate component to be etched away to form a second gap between a second portion of the dielectric substrate component and the second bridging portion.

[0016] These and other features will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A block diagram of an exemplary non-limiting system 100 is shown that can be used to desirably design circuits including coplanar waveguides (CPWs) that can be enhanced to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter.

[0018] Figure 2 Schematic diagrams showing various views of an exemplary non-limiting circuit that can include a CPW that can be enhanced to include a bridging conductor portion of a conductor line that is elevated above a substrate to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter.

[0019] Figure 3 An exemplary energy graph is shown illustrating energy concentration of a CPW where portions of the substrate associated with the space between the center conductor line and the return conductor line are etched away.

[0020] Figure 4 An energy graph is shown illustrating energy concentration of a CPW where a bridging conductor portion of a center conductor line of the CPW is elevated a desired distance above a substrate in accordance with various aspects and embodiments of the disclosed subject matter.

[0021] Figure 5 A schematic diagram illustrating an exemplary graph of signal attenuation as a function of bridge height of a bridge conductor portion relative to a center conductor line of a CPW in accordance with various aspects and embodiments of the disclosed subject matter.

[0022] Figure 6 A schematic diagram is shown of an example portion of a CPW that can include a bridging conductor portion of a center conductor line of the CPW, wherein the bridging conductor portion can be formed to have a circular shape, in accordance with various aspects and embodiments of the disclosed subject matter.

[0023] Figure 7 A schematic diagram is shown of an example portion of a CPW that can include a bridge conductor portion of a center conductor line of the CPW, wherein the bridge conductor portion can be formed to have a semi-rectangular shape, in accordance with various aspects and embodiments of the disclosed subject matter.

[0024] Figure 8Schematic diagrams showing various views of an exemplary non-limiting circuit according to various aspects and embodiments of the disclosed subject matter, which circuit may include a CPW that may be enhanced to include a bridging conductor portion of a center conductor line that may be disposed over a remainder of a substrate that may remain after removing portions of the substrate to mitigate energy losses in or associated with the substrate.

[0025] Fig. 9 An exemplary graph illustrating signal attenuation as a function of etch depth of a substrate portion underlying a bridge conductor portion of a center conductor line of a CPW is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0026] Fig.10 A schematic diagram illustrating a cross-sectional side view of an exemplary non-limiting circuit according to various aspects and embodiments of the disclosed subject matter, the circuit may include a CPW that may be enhanced to include a bridging conductor portion of a conductor line that may be elevated above a remainder of a substrate, wherein portions of the substrate may be removed to form the remainder of the substrate to form a desired gap of a desired distance between the bridging conductor portion and a corresponding remainder of the substrate to mitigate energy losses.

[0027] Fig.11 A flow chart is shown of an exemplary non-limiting method that can be used to desirably design a circuit (eg, a quantum computing circuit) that includes a CPW that can be enhanced to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter.

[0028] Fig.12 A flow chart is shown of another exemplary non-limiting method for forming a CPW that can be enhanced to include a bridging conductor portion of the wire that can be elevated above the substrate to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter.

[0029] Fig.13 A flow chart is shown of an exemplary non-limiting method for forming a CPW that may be enhanced to include a bridging conductor portion of a center conductor line that may be disposed over a remainder of a substrate that may remain after removing portions of the substrate in order to mitigate energy losses in or associated with the substrate in accordance with various aspects and embodiments of the disclosed subject matter.

[0030] Fig.14 A block diagram is shown of an example, non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0031] Fig.15Schematic diagram of the cross section of the traditional CWP.

[0032] Fig.16 An exemplary energy graph of a conventional CWP is shown, illustrating energy losses associated with a conventional CPW, including energy losses in or associated with the substrate and energy losses associated with the top vacuum region associated with the CPW. DETAILED DESCRIPTION

[0033] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. In addition, it is not intended to be bound by any express or implied information presented in the previous background or summary or detailed description.

[0034] One or more embodiments are now described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to represent the same elements. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, in various cases, it is apparent that the one or more embodiments described may be practiced without these specific details.

[0035] Quantum circuit design can utilize superconducting quantum devices to perform various functions and operations. Regarding the fabrication of quantum circuits, some quantum circuits can utilize coplanar waveguides (CWP) as transmission lines for quantum applications. Fig.15 , Fig.15 A cross-sectional view of a conventional CPW 1500 is shown. The CPW 1500 may include a substrate 1502, which may be formed on a ground plane layer 1504, as desired. The substrate 1502 may be formed of a dielectric material, and the ground plane layer 1504 may be formed of a conductive material. The substrate 1502 may have a desired size (e.g., length, width, height), and the ground plane layer 1504 may also have a desired size, where the length and width of the ground plane layer 1504 may generally correspond to the size of the substrate 1502. For example, the substrate 1502 associated with the CPW 1500 may have a size such as a width of about 40 micrometers (μm) or more or less than 40 μm, a length (L) that may be the same as or different from the width, and a height (H) of about 20 μm or more or less than 20 μm.

[0036] The CPW 1500 may include a central conductor line 1506 that may be formed on a substrate 1502, which may be a transmission line for transmitting signals (e.g., transmitting information via the signals), and two return conductor lines 1508 and 1510 that may be formed on the substrate 1502, wherein the return conductor line 1508 is on one side of the central conductor line 1506 and the return conductor line 1510 is on the other side of the central conductor line 1506, wherein each of the return conductor line 1508 and the return conductor line 1510 may be separated from the central conductor line 1506 by a desired amount of space (S). The central conductor line 1506 may have a desired width (W), such as about 10 μm or less, and the return conductor lines 1508 and 1510 may each have a width of, for example, about 10 μm. The central conductor line 1506 and / or the return conductor lines 1508 and 1510 may have a desired thickness (T met ), for example, about 0.2 nanometers (nm). Center conductor line 1506, return conductor lines 1508 and 1510, and / or ground plane layer 1504 may include a desired superconducting material.

[0037] CWPs, such as CPW 1500, can be used to transmit signals, such as microwave frequency signals for quantum applications. However, superconducting quantum devices can be very sensitive to energy losses (e.g., microwave losses) in dielectric substrates, and CPWs, such as CPW 1500, can have undesirable energy losses (e.g., microwave losses) in substrates (e.g., dielectric substrates), such as substrate 1502.

[0038] Reference Fig.16 , Fig.16 An exemplary energy graph 1600 of a conventional CWP (e.g., CPW 1500) is shown, illustrating energy losses associated with the conventional CPW, including energy losses in or associated with a substrate (e.g., substrate 1502) and energy losses associated with a top vacuum region associated with the CPW. The exemplary energy graph 1600 may illustrate respective energies in or associated with respective regions of the CPW 1602, which may include a substrate 1604 (e.g., a silicon-type dielectric substrate) having a height of approximately 20 μm, and a center conductor line 1606 and return conductors 1608 and 1610 each including a niobium-type superconducting material and having a thickness of approximately 0.2 nm.

[0039] As can be observed in the example energy graph 1600, in conventional CPW 1602, the energy in or associated with substrate 1604 can be of substantial magnitude. For example, a relatively (and undesirably) large amount of energy (e.g., ranging from 8.0E-011 to 1.0E-010) can be present in substrate 1604 in region 1612 in substrate 1604, which can be beneath center conductor line 1606 and a portion of return conductor lines 1608 and 1610, spanning from an area beneath a portion of return conductor line 1608 to an area beneath center conductor line 1606 and to an area beneath a portion of return conductor line 1610, and extending approximately 5 μm downward in the area beneath center conductor line 1606. There is also a comparable and still undesirably high amount of energy (e.g., ranging from 6.0E-011 to 8.0E-011) in the substrate 1604 in a region 1614 of the substrate 1604 beneath a portion of the center conductor line 1606 and the return conductor lines 1608 and 1610, and extending downward from a location where the region 1612 terminates deeper in the substrate 1604 by about 1 μm. Additionally, there may be a slightly lower, but still undesirably high amount of energy (e.g., ranging from 4.0E-011 to 6.0E-011) in the substrate 1604 in a region 1616 of the substrate 1604 beneath a portion of the center conductor line 1606 and the return conductor lines 1608 and 1610, and extending downward from a location where the region 1614 terminates deeper in the substrate 1604 by about 1 μm to 2 μm. Comparable and still undesirably high energies may also be present in portions of the vacuum region 1618 associated with the CPW 1602, such as in regions 1620 and 1622 associated with (e.g., near) respective edges (e.g., sides) of the center conductor line 1606 and extending approximately 1.5 μm outward from respective edges of the center conductor line 1606.

[0040] A conventional approach to addressing energy losses in or associated with a CPW-related dielectric substrate may be to perform a partial substrate etching of portions of the substrate near the space between the center conductor line and the return conductor line of the CWP. However, even with an aggressive or deep etch of those portions of the substrate near the space, there may still be a significant and undesirable amount of energy lost in the dielectric substrate. These and other deficiencies in conventional fabrication of quantum circuits may result in inefficiencies and / or inefficient circuits and / or inefficient performance of the quantum circuits.

[0041] The disclosed subject matter can be implemented to produce solutions to all or at least some of these problems and / or other problems of conventional quantum computing circuits including conventional CPWs in the form of creating a desired gap between a significant portion of a center conductor line of a CPW and a portion of a substrate that may be beneath or near the center conductor line. By creating a desired gap between a significant portion of a center conductor line of a CPW and a portion of a substrate beneath or near the center conductor line, the disclosed subject matter can mitigate (e.g., reduce or minimize) energy losses (e.g., microwave losses) in or associated with a substrate associated with the CPW and / or energy losses associated with a vacuum region associated with the CPW.

[0042] To this end, various embodiments herein relate to techniques for designing and manufacturing quantum circuits including CPWs for quantum applications. According to the disclosed subject matter, regarding the design and manufacture of the CPW, a center conductor line and two return conductor lines can be formed on a dielectric substrate, wherein one return conductor line is on each side of the center conductor line and is separated from the center conductor line by a space of a defined size. In some embodiments, the center conductor line can have a bridging portion (e.g., a bridging conductor portion) of a defined length and a base conductor portion, the bridging portion can be raised a desired distance above the dielectric substrate, the base conductor portion can be located between the bridging portions and / or adjacent to the bridging portions and in contact with the surface of the dielectric substrate. Raising the bridging portion to a defined distance above the dielectric substrate can form a desired gap (e.g., a desired distance) between the bridging portion of the center conductor line and the surface of the dielectric substrate. By raising the bridging portion to form a desired gap between the bridging portion of the center conductor line and the surface of the dielectric substrate, the disclosed subject matter can desirably and significantly reduce energy losses in the dielectric substrate or energy losses associated with the dielectric substrate. Furthermore, in accordance with the disclosed subject matter, the CPW can have a desired amount of impedance (eg, 50 ohms).

[0043] In other embodiments, as an alternative to raising the bridging conductor portion of the center conductor line above the substrate component, the disclosed subject matter can remove (e.g., etch away or otherwise remove) a portion of the dielectric substrate below the bridging portion of the center conductor line so that the bridging portion of the center conductor line can be a desired distance above the surface of the remaining portion of the dielectric substrate (e.g., the dielectric substrate remaining after removing the portion of the dielectric substrate), and the base conductor portion of the center conductor line can be in contact with other portions of the surface of the dielectric substrate that have not been removed and located between and / or adjacent to (e.g., located adjacent to or between) the spaces formed by removing the portions of the dielectric substrate. Removing the portion of the dielectric substrate below the bridging portion of the center conductor line can form a desired gap (e.g., a desired distance) between the bridging portion of the center conductor line and the surface of the remaining portion of the dielectric substrate. By removing a portion of the dielectric substrate beneath the bridge portion of the center conductor line to form a desired gap between the bridge portion of the center conductor line and the surface of the remaining portion of the dielectric substrate, the disclosed subject matter can desirably and significantly reduce energy losses in or associated with the dielectric substrate and / or energy losses associated with vacuum regions associated with the CPW. Additionally, according to the disclosed subject matter, the CPW can have a desired amount of impedance (e.g., 50 ohms).

[0044] In other embodiments, the disclosed subject matter may employ a hybrid approach in which a portion of the dielectric substrate below the bridge portion of the center conductor line may be removed, and the bridge portion of the center conductor line may be raised (e.g., raised above the dielectric substrate and the base conductor portion of the center conductor line) such that the bridge portion of the center conductor line may be a desired distance above the surface of the remaining portion of the dielectric substrate (e.g., the dielectric substrate remaining after the portion of the dielectric substrate is removed). For example, if the desired gap between the bridge portion of the center conductor line and the dielectric substrate is 4 μm, the disclosed subject matter may raise the bridge portion of the center conductor line by 2 μm relative to other portions of the dielectric substrate on which the base conductor portion of the center conductor line is disposed, and may remove portions of the dielectric substrate below the bridge portion to a depth of 2 μm to form a total gap of 4 μm between the bridge portion of the center conductor line and the surface of the remaining portion of the dielectric substrate below the bridge portion.

[0045] It should be understood and appreciated that, in accordance with various aspects and embodiments of the disclosed subject matter, the desired gap between the bridge portion of the center conductor line and the surface of the remaining portion of the dielectric substrate below the bridge portion can be 4 μm, or greater or less than 4 μm, ranging from about 1 μm to 10 μm. It should also be understood and appreciated that if a hybrid approach is used, the amount by which the bridge portion of the center conductor line is raised above the dielectric substrate (e.g., above other portions of the dielectric substrate on which the base conductor portion of the center conductor line is disposed) can be the same or different than the depth of the space formed by removing portions of the dielectric substrate below the bridge portion of the center conductor line.

[0046] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the figures.

[0047] Figure 1 A block diagram of an exemplary non-limiting system 100 is shown that can be used to desirably design a circuit (e.g., a quantum computing circuit) that includes a CPW that can be enhanced to mitigate energy losses, in accordance with various aspects and embodiments of the disclosed subject matter. System 100 can include design component 102 that can be used to design a circuit, such as circuit 104, that can include a CPW, such as CPW 106, that can be enhanced to mitigate (e.g., reduce or minimize) energy losses, such as energy losses (e.g., microwave losses) associated with a substrate (e.g., a dielectric substrate) of circuit 104. For example, a substrate associated with the CPW can have a desired size, such as a width of about 40 μm or more or less than 40 μm, a length that can be the same as or different from the width, and a height of about 20 μm or more or less than 20 μm. In some embodiments, circuit 104 can be or can include a quantum computing circuit that can include CPW 106 and / or qubits.

[0048] The design component 102 may include a substrate forming component 108, which may be used to form, construct, or build a substrate component of the CPW 106. The substrate forming component 108 may form a substrate component of a desired dielectric material and may have a desired size (e.g., length, width, and height) and shape. According to various embodiments, the substrate component may be formed of a dielectric material that may have a desired high thermal conductivity of less than 1K.

[0049] The design component 102 may also include a conductor forming component 110, which may be used to form, construct, or construct a conductor component including a conductor (e.g., a center conductor line, a return conductor line, and / or a ground plane layer, etc.) of the CPW 106 on the substrate component. For example, the conductor forming component 110 may form the CPW 106 to include a center conductor line that may be positioned approximately along a centerline on the substrate component relative to the return conductor line, wherein the conductor forming component 110 may form the return conductor line of the CPW 106 on an opposite side of the center conductor line, wherein the return conductor line is separated from the center conductor line on the substrate component by a space having a defined size (e.g., a defined width, which may be uniform or substantially uniform). The center conductor line and / or the return conductor line may each have a desired thickness (e.g., height). For example, the center conductor line and / or the return conductor line may each have a thickness of approximately 0.2 nm, or another desired thickness on the nanometer scale.

[0050] In some embodiments, the conductor forming component 110 may include a bridge forming component 112 that may form, construct, or construct a center conductor line that may include a bridge conductor portion (e.g., a set or series of bridge conductor portions) of a defined size (e.g., a defined length and a defined width) that may be raised a desired distance above the substrate component and a base conductor portion that may be located between and / or adjacent to the bridge conductor portions and in contact with a surface (e.g., a top-facing surface) of the substrate component. According to various embodiments, the bridge forming component 112 may raise the bridge conductor portion of the center conductor line above the surface of the substrate component to form a gap of a defined distance, such as 4 μm, or another other desired distance in the range of approximately 1 μm to 10 μm, between the bridge conductor portion and the surface of the substrate component. By raising the bridge conductor portion to form a desired gap between the bridge conductor portion and the surface of the substrate component, the disclosed subject matter may have the advantage of desirably and significantly mitigating (e.g., reducing or minimizing) energy losses (e.g., microwave losses) in or associated with the substrate component. Furthermore, in accordance with the disclosed subject matter, conductor forming member 110 can form CPW 106 to have a desired amount of impedance, such as 50 ohms.

[0051] In other embodiments, instead of raising the bridge conductor portion of the center conductor line above the substrate component, the substrate forming component 108 can remove (e.g., etch away, use chemical etching or other desired etching techniques, or otherwise remove) a portion of the substrate component below the bridge conductor portion so that the bridge conductor portion can be a desired distance above the surface of the remaining substrate component below the bridge conductor portion (e.g., the remaining portion of the substrate component remaining after removing the portion of the substrate). There can be a base conductor portion of the center conductor line that can be located between and / or adjacent to the bridge conductor portions, and the conductor forming component 110 can form the base conductor portion to contact other portions of the surface of the substrate component that have not been removed and to be located between and / or adjacent to the space formed by removing the portion of the substrate component. Removing the portion of the substrate component below the bridge conductor portion of the center conductor line can form a desired gap of a desired distance (e.g., 4 μm, or another other desired distance in the range of about 1 μm to 10 μm) between the bridge conductor portion and the lower surface of the remaining portion of the substrate component. By removing portions of the substrate component below the bridging conductor portion of the center conductor line to form a desired gap between the bridging conductor portion of the center conductor line and the underlying surface of the remaining portion of the substrate component, the disclosed subject matter can have the advantage of desirably and significantly mitigating (e.g., reducing or minimizing) energy losses in or associated with the substrate component. In addition, according to the disclosed subject matter, the conductor forming component 110 can form the CPW 106 to have a desired amount of impedance (e.g., 50 ohms or other desired impedance).

[0052] In other embodiments, the design component 102 can employ a hybrid approach to forming the CPW 106. For example, the substrate forming component 108 can remove a portion of the substrate component that can be located below the bridge conductor portion of the center conductor line (when the center conductor line is formed on the substrate component) to form a remaining portion of the substrate component that can be at a desired depth relative to other portions of the substrate component that can be adjacent to the remaining portion of the substrate component. In addition, the bridge forming component 112 can form the bridge conductor portion of the center conductor line to be elevated (e.g., elevated above the substrate component and the base conductor portion of the center conductor line) so that the bridge conductor portion can be a desired distance above the surface of the remaining portion below the substrate component. For example, if the desired gap between the bridge conductor portions and the base component is 4 μm, the base forming component 108 (e.g., before forming the center conductor line) can remove the portion of the base component below the location of the bridge conductor portions (e.g., where the bridge conductor portions will be located) to a depth of 2 μm, and when forming the center conductor line including the raised bridge conductor portions on the substrate component, the bridge forming component 112 can raise the bridge conductor portions by 2 μm relative to the rest of the substrate component to form a total gap of 4 μm between the bridge conductor portions and the surface of the remaining portion below the substrate component, where the base conductor portions of the center conductor line are disposed. In addition, according to the disclosed subject matter, the conductor forming component 110 can form the CPW 106 to have a desired impedance amount (e.g., 50 ohms or other desired impedance amount), as described more fully herein.

[0053] It should be understood and appreciated that, according to various aspects and embodiments of the disclosed subject matter, the desired gap between the bridge conductor portion of the center conductor line and the underlying surface of the remaining portion of the substrate component can be 4 μm, or greater or less than 4 μm, ranging from about 1 μm to 10 μm. It should also be understood and appreciated that if a hybrid approach is used, the amount by which the bridge conductor portion is raised above the substrate component (e.g., above the other portion of the substrate element on which the base conductor portion of the center conductor line is disposed) can be the same or different than the depth of the space formed by removing the portion of the substrate component below the bridge conductor portion of the center conductor line. As a non-limiting example, to achieve a total gap of 4 μm, the bridge forming component 112 can raise the bridge conductor portion 3 μm above the other portion of the substrate component on which the base conductor portion is disposed, and the substrate forming component 108 can remove a 1 μm deep portion of the substrate component below the bridge conductor portion, so that the remaining portion of the substrate component below can have a depth of 1 μm relative to the other portion of the substrate component adjacent to the remaining portion of the substrate component. As another non-limiting example, to achieve a total gap of 5 μm, the bridge forming component 112 may raise the bridge conductor portion 2 μm above the other portions of the substrate component on which the base conductor portion of the center conductor line is disposed, and the substrate forming component 108 may remove a 3 μm deep portion of the substrate component below the bridge conductor portion so that the remaining portion below the substrate component may have a depth of 3 μm relative to the other portions of the substrate component adjacent to the remaining portion of the substrate component.

[0054] refer to Figure 2 (Together with Figure 1 ), Figure 2Schematic diagrams showing various views of an example, non-limiting circuit 200, which may include a CPW, which may be enhanced to include a bridging conductor portion of a conductor, which may be elevated above a substrate to mitigate energy loss, according to various aspects and embodiments of the disclosed subject matter. As shown in top view 202, cross-sectional side view 204 (view A-A'), and cross-sectional front view 206 (view B-B') of circuit 200, circuit 200 may be or may include a CPW, which may include a substrate 208, which may be formed of a desired substrate material (e.g., a desired dielectric material). Substrate forming component 108 may form substrate 208 to have a defined size and a defined shape, which may be suitable for forming a CPW of circuit 200. In some embodiments, substrate 208 may be a dielectric substrate, which may be formed of a dielectric material, which may have a thermal conductivity level that may meet a defined threshold thermal conductivity level according to a defined circuit design standard. For example, the dielectric material of substrate 208 may have a desired (e.g., appropriately, acceptably, or optimally) high thermal conductivity level below 1 K according to (e.g., it may meet) a defined threshold thermal conductivity level, wherein the desired high thermal conductivity level may be high enough to be suitable for quantum computing circuits. Dielectric materials that may have a desired high thermal conductivity level below 1 K may include, for example, silicon, silicon-based materials, sapphire, sapphire-based materials, or other desired (e.g., suitable) dielectric materials.

[0055] The conductor forming component 110 may form a conductor line 210 (also referred to as a center conductor line), which may be a center conductor line of a CPW, which may be associated with (e.g., at least partially in contact with) a substrate 208 (e.g., a surface of the substrate 208) in a desired region of the substrate 208 (e.g., a center or substantially center region of the substrate 208). As part of forming the CPW, the conductor forming component 110 may also form a first return conductor line 212 and a second return conductor line 214, which may be disposed (e.g., deposited or placed) on the substrate 208 on respective (e.g., opposite or different) sides of the conductor line 210, wherein the first return conductor line 212 may be separated from the center conductor line 210 by a space 216 of a desired size (e.g., a desired width), and wherein the second return conductor line 214 may be separated from the center conductor line 210 by a space 218 of a desired size. In some embodiments, the space 216 and the space 218 may be uniform, or only the center conductor line 210 and the first return conductor line 212 and the second return conductor line 214 may be at least substantially uniform. The first return conductor line 212 and the second return conductor line 214 can each have a desired size (e.g., width, length, and height) that can be suitable for the CPW. In some embodiments, the center conductor line 210 and / or the return conductor lines 212 and 214 can each have a desired thickness (e.g., height). For example, the center conductor line 210 and / or the return conductor lines 212 and 214 can each have a thickness of approximately 0.2 nm, or can be another desired thickness on the order of nanometers.

[0056] The conductor line 210 and / or the first return conductor line 212 and the second return conductor line 214 may be formed of a desired conductive material to enable transmission of signals (e.g., transmission of signals through the conductor 210). In some embodiments, the conductor line 210 and / or the first return conductor line 212 and the second return conductor line 214 may be formed of a superconducting material. For example, the conductor line 210 and / or the first return conductor line 212 and the second return conductor line 214 may be formed of a superconducting material, such as niobium, niobium-based materials, aluminum, aluminum-based materials, or other desired (e.g., suitable) superconducting materials.

[0057] According to various embodiments, the conductor-forming component 110 (e.g., using the bridge-forming component 112) can form the center conductor line 210 to include bridge conductor portions (e.g., bridge conductor portions 220, 222, and 224) and base conductor portions (e.g., base conductor portions 226, 228, 230, and 232), which can alternate and / or be adjacent to the bridge conductor portions along the center conductor line 210. The base conductor portions (e.g., 226, 228, 230, and 232) can be disposed on and in contact with the substrate 208 in a desired area (e.g., a central area) of the substrate 208. The conductor forming member 110 may form a bridging conductor portion (e.g., 220, 222, and 224) that is elevated above the substrate 208 by a defined distance and disposed thereon to form a gap of a defined distance (e.g., height (h)) between the bridging conductor portion and the substrate 208 to facilitate mitigation (e.g., reduction or minimization) of energy losses (e.g., microwave losses) associated with or in the substrate 208. In some embodiments, the conductor forming component 110 can form or construct the bridge conductor portions (e.g., 220, 222, and 224) to extend upward from the associated (e.g., connected) base conductor portions (e.g., 226, 228, 230, and 232) to a defined distance at a desired angle (e.g., 45°, 60°, 30°, or other desired angle) relative to the associated (e.g., connected) base conductor portions, wherein each bridge conductor portion can extend above the substrate 208 at a defined distance across a desired length of the substrate 208 (e.g., about 40 μm, or greater or less than 40 μm), and wherein each bridge conductor portion at the other end can extend downward at a desired angle to its associated (e.g., connected) adjacent base conductor portion at the other end of the bridge conductor portion. According to various embodiments, the bridge forming component 112 can form the bridge conductor portions 220, 222, and 224 of the center conductor line 210 using a wire forming technique or an air bridging technique.

[0058] In some embodiments, according to the disclosed subject matter, the conductor forming component 110 can form the CPW to have a desired impedance amount, such as 50 ohms. For example, the conductor forming component 110 can adjust the geometry or size (e.g., width and / or thickness) of the center conductor line 210 to achieve the desired impedance amount.

[0059] By raising the bridging conductor portions (e.g., 220, 222, and 224) a defined distance above the substrate 208, the disclosed subject matter can have the advantage of desirably and significantly mitigating (e.g., reducing or minimizing) energy losses in or associated with the substrate 208 and / or energy losses associated with vacuum regions associated with the CPW, as compared to conventional techniques for forming a CPW.

[0060] Brief reference Figure 3 , Figure 3 A schematic diagram of an exemplary energy graph 300 is shown, which illustrates energy concentration of a CPW in which a portion of the substrate associated with the space between the center conductor line and the return conductor line is etched away. The exemplary energy graph 300 may include an energy graph 302 of a CPW 304, which illustrates energy concentration in various regions of a substrate 306, and an energy graph 308, which illustrates energy concentration in various regions of a top vacuum 310 associated with the CPW 304. The CPW 304 may include a center conductor line 312 and return conductor lines 314 and 316. In this example CPW 304, a portion of the substrate 306 associated with the space between the center conductor line 312 and the return conductor lines 314 and 316 may be removed (e.g., etched away) to form opening areas 318 and 320, which may be 10 μm deep relative to the top surface of the substrate 306 associated with (e.g., in contact with) the center conductor line 312 and the return conductor lines 314 and 316. As can be observed in energy graph 302, even though substrate portions of substrate 306 are removed to create open regions 318 and 320, after the substrate portions are removed, a significant and undesirable amount (e.g., a majority) of energy (e.g., electromagnetic field energy) may still be present in substrate 306 including region 322. As can be observed in energy graph 308, even though substrate portions of substrate 306 are removed to create open regions 318 and 320, significant and undesirable energy may still be present in top vacuum 310 associated with CPW 304, particularly near center conductor line 312 (e.g., in regions 324 and 326).

[0061] Temporarily go to Figure 4 , Figure 4A schematic diagram of an energy graph 400 is shown illustrating energy concentration of a CPW wherein a bridge conductor portion of a center conductor line of the CPW is elevated a desired distance above a substrate in accordance with various aspects and embodiments of the disclosed subject matter. The bridge conductor portion 402 of the center conductor line of the CPW 404 can be at a desired distance, such as 10 μm, above a substrate 406. The CPW 404 can also include return conductor lines 408 and 410 that can be on opposite sides of the center conductor line with corresponding spaces between the center conductor line (including the bridge conductor portion 402) and the return conductor lines 408 and 410. As can be observed in energy graph 400, by raising bridging conductor portion 402 a desired distance of 10 μm above substrate 406, there can be no or little (e.g., a very small or minimal amount) of energy in substrate 406, and there can be only a relatively small amount of energy (e.g., electromagnetic field energy) in the top vacuum, primarily in region 412 near bridging conductor portion 402 (e.g., region 412 partially extends downward from bridging conductor portion 402 by approximately 4 μm).

[0062] Temporarily go to Figure 5 , Figure 5 A schematic diagram of an exemplary graph 500 of signal attenuation as a function of the bridge height of a bridge conductor portion relative to a center conductor line of a CPW is shown in accordance with various aspects and embodiments of the disclosed subject matter. As can be seen from graph 500, as the height (h) of the bridge conductor portion of the center conductor line of the CPW above the substrate increases, the amount of signal attenuation can be significantly reduced. For example, as can be seen in graph 500, even when the bridge conductor portion is raised to a height of 1 μm above the substrate, the signal attenuation has been significantly reduced (as shown at reference numeral 502 of graph 500). As can also be seen in graph 500, in the case of raising the bridge conductor portion to a height of 4 μm above the substrate, the amount of signal attenuation can be further reduced (as shown at reference numeral 504 of graph 500) compared to the signal attenuation reduction associated with a 1 μm height of the bridge conductor portion relative to the substrate, wherein even greater signal attenuation reduction can be achieved at heights of the bridge conductor portion greater than 4 μm. These graphical results regarding graph 500 of reduction in signal attenuation as a function of height of the bridging conductor portion above the substrate may correspond to (e.g., be associated with) a significant and increased mitigation (e.g., reduction) in energy losses in or associated with the substrate as the bridging conductor portion of the center conductor line of the CPW is raised or otherwise further above or separated from the substrate.

[0063] Reference again Figure 2 , although in Figure 2In the present invention, the bridging conductor portions (e.g., 220, 222, and 224) of the conductor line 210 are shown and described as being formed to extend upward and downward at a desired angle (e.g., 45°, 60°, 30°, or other desired angles), but according to the disclosed subject matter, the bridging conductor portions may be connected to the conductor line 210 at the same time. Figure 2 As a non-limiting example, briefly refer to Figure 6 (Together with Figure 1 ), Figure 6 A schematic diagram of an example portion of a CPW 600 is shown, which can include a bridge conductor portion of a center conductor line of the CPW, wherein the bridge conductor portion can be formed to have a circular shape, in accordance with various aspects and embodiments of the disclosed subject matter. The example portion of the CPW 600 can include a substrate 602 formed of a desired substrate material (e.g., a dielectric material as described herein). The conductor forming component 110 can form a center conductor line 604 that can be disposed on or over the substrate 602. The conductor forming component 110 employing the bridge forming component 112 can form the center conductor line 604 to include a bridge conductor portion 606 and base conductor portions 608 and 610, which can be on each side of the bridge conductor portion 606 (e.g., adjacent to and connected to) and can be disposed on and / or in contact with the substrate 602. In some embodiments, the conductor forming member 110 (e.g., using the bridge forming member 112) can form the bridge conductor portion 606 to have a circular shape (e.g., a semicircular or semi-elliptical shape), which can extend upward from the base conductor portion 608 and the substrate 602 to a defined distance above the substrate 602 (e.g., a desired height (H)), extend on the substrate and span a defined length of the substrate (e.g., approximately 40 μm, or greater or less than 40 μm), and extend downward to the base conductor portion 610.

[0064] As another non-limiting example, briefly refer to Figure 7 (Together with Figure 1 ), Figure 7A schematic diagram of an example portion of a CPW 700 is shown that can include a bridge conductor portion of a center conductor line of the CPW, wherein the bridge conductor portion can be formed to have a semi-rectangular shape, in accordance with various aspects and embodiments of the disclosed subject matter. The example portion of the CPW 700 can include a substrate 702 formed of a desired substrate material (e.g., a dielectric material as described herein). The conductor forming component 110 can form a center conductor line 704 that can be disposed on or over the substrate 702. The conductor forming component 110 employing the bridge forming component 112 can form the center conductor line 704 to include a bridge conductor portion 706 and base conductor portions 708 and 710, which can be located on each side of the bridge conductor portion 706 (e.g., adjacent to and connected to the bridge conductor portion), and can be disposed on and / or in contact with the substrate 702. In some embodiments, the conductor forming member 110 (e.g., using the bridge forming member 112) can form the bridge conductor portion 706 to have a semi-rectangular shape, which can extend upward from the base conductor portion 708 and the substrate 702 at a right angle (e.g., 90°) or substantially at a right angle to a defined distance (e.g., a desired height (h)) above the substrate 702, extend on and across a defined length of the substrate (e.g., approximately 40 μm, or greater or less than 40 μm), and extend downward at a right angle or substantially at a right angle to the base conductor portion 710.

[0065] refer to Figure 8 (Together with Figure 1 ), Figure 8Schematic diagram showing various views of an exemplary non-limiting circuit 800 according to various aspects and embodiments of the disclosed subject matter, the circuit may include a CPW that may be enhanced to include a bridging conductor portion of a center conductor line that may be disposed over a remaining portion of a substrate that may remain after removing portions of the substrate in order to mitigate energy losses in or associated with the substrate. As shown in top view 802, cross-sectional side view 804 (view C-C'), and cross-sectional front view 806 (view D-D') of circuit 800, circuit 800 may be or may include a CPW that may include a substrate 808 that may be formed of a desired substrate material (e.g., a desired dielectric material). Substrate forming component 108 may form substrate 808 to have a defined size and a defined shape that may be suitable for forming a CPW of circuit 800. In some embodiments, substrate 808 may be a dielectric substrate that may be formed of a dielectric material (e.g., silicon or sapphire-like material) that may have a thermal conductivity level that may meet a defined threshold thermal conductivity level according to defined circuit design criteria. For example, the dielectric material of substrate 808 may have a desirably (eg, suitably, acceptably, or optimally) high thermal conductivity level below 1 K according to (eg, it may meet) a defined threshold thermal conductivity level.

[0066] The conductor forming component 110 can form a conductor line 810, which can be a center conductor line of a CPW, which can be associated with (e.g., at least partially in contact with) a substrate 808 (e.g., a surface of the substrate 808) in a desired area of ​​the substrate 808 (e.g., a center or substantially center area of ​​the substrate 808). As part of forming the CPW, the conductor forming component 110 can form a first return conductor line 812 and a second return conductor line 814, which can be disposed (e.g., deposited or placed) on the substrate 808, on opposite sides or adjacent sides of the conductor line 810, wherein the first return conductor line 812 can be separated from the center conductor line 810 by a space 816 of a desired size, and wherein the second return conductor line 814 can be separated from the center conductor line 810 by a space 818 of a desired size (e.g., width). The first return conductor line 812 and the second return conductor line 814 can each have a desired width and length, which can be suitable for the CPW.

[0067] The conductor line 810 and / or the first return conductor line 812 and the second return conductor line 814 may be formed of a desired conductive material (e.g., a superconducting material or other desired conductive material) to enable transmission of signals (e.g., transmission of signals through the conductor line 810). For example, the conductor line 810 and / or the first return conductor line 812 and the second return conductor line 814 may be formed of a superconducting material, such as a niobium type material or an aluminum type superconducting material.

[0068] According to various embodiments, to facilitate forming a CPW (e.g., enhancing a CPW), the substrate forming component 108 may form the substrate 808 to remove (e.g., etch away) a portion of the substrate 808 in a desired area of ​​the substrate 808 on or above which the center conductor line 810 may be disposed, so that there may be a remaining portion of the substrate 808, including remaining portions 820, 822, and 824 of the substrate 808, which may be a desired depth below other portions 826, 828, 830, and 832 of the substrate 808, which may be between and / or adjacent to the remaining portions 820, 822, and 824 of the substrate 808. The length and width of the remaining portions 820, 822, and 824 of the substrate 808 may be desired according to defined circuit design standards. For example, the length of each of the remaining portions 820, 822, and 824 may be relatively longer (e.g., significantly longer) than the length of each of the other portions 826, 828, 830, and 832 of the substrate 808. In some embodiments, the width of the remaining portions 820, 822, and 824 of the substrate 808 may extend from a portion of the substrate below the return conductor line 812 to another portion of the substrate below the return conductor line 814 (eg, Figure 8 800 (view B-B'). In other embodiments, the width of the remaining portion (e.g., 820, 822, or 824) of the substrate 808 can be smaller, so that the substrate can extend beyond the overlying return conductor lines 812 and 814 toward the center conductor line 810. Depending on the defined circuit, the depth of the remaining portions 820, 822, and 824 relative to the height of the other portions 826, 828, 830, and 832 of the substrate 808 and the overlying center conductor line 810 can be as desired, for example, to achieve a desired reduction in energy losses in or associated with the substrate 808. According to various embodiments, the depth of the remaining portions 820, 822, and 824 of the substrate 808 can be in a range from about 1 μm to about 10 μm. In an example embodiment, the depth of the remaining portions 820, 822, and 824 can be 4 μm.

[0069] According to various embodiments, the conductor forming member 110 may form the center conductor line 810 to include bridge conductor portions such as bridge conductor portions 834, 836, and 838 and base conductor portions such as base conductor portions 840, 842, 844, and 846, which may alternate with or be adjacent to the bridge conductor portions along the center conductor line 810. The corresponding base conductor portions (e.g., 840, 842, 844, and 846) may be disposed on and in contact with the corresponding other portions 826, 828, 830, and 832 of the substrate 808 in a desired area of ​​the substrate 808, and the corresponding bridge conductor portions 834, 836, and 838 of the center conductor line 810 are disposed on the corresponding remaining portions 820, 822, and 824 of the substrate 808. According to some embodiments, the center conductor line 810 may be flat or substantially flat, such that the bridge conductor portions and the base conductor portions of the center conductor line may be at the same level relative to each other.

[0070] Given the depth of the remaining portions 820, 822, and 824 of the substrate 808, there can be respective gaps of a defined distance (d) (e.g., a distance equal to the depth of the remaining portions 820, 822, and 824) between respective surfaces of the remaining portions 820, 822, and 824 of the substrate 808 (e.g., top-facing surfaces) and respective surfaces of the bridging conductor portions 834, 836, and 838 of the center conductor line 810. By removing portions of the substrate 808 to form the remaining portions 820, 822, and 824, thereby forming gaps of a defined distance between the remaining portions 820, 822, and 824 and the bridging conductor portions 834, 836, and 838, the disclosed subject matter can have the advantage of desirably and significantly mitigating (e.g., reducing or minimizing) energy losses in or associated with the substrate 808 and / or energy losses associated with vacuum regions associated with the CPW, as compared to conventional techniques for forming a CPW.

[0071] In some embodiments, in accordance with the disclosed subject matter, conductor forming component 110 can form a CPW to have a desired amount of impedance (e.g., 50 ohms or other desired impedance). For example, conductor forming component 110 can adjust the geometry or size (e.g., width and / or thickness) of center conductor line 810 to achieve a desired amount of impedance, thereby offsetting or mitigating any impedance changes that may occur due to etching to remove portions of substrate 808.

[0072] Briefly refer to Fig. 9 , Fig. 9An exemplary graph 900 of signal attenuation as a function of etch depth of a substrate portion located below a bridge conductor portion of a center conductor line of a CPW according to various aspects and embodiments of the disclosed subject matter is shown. As can be seen from graph 900, as the etch depth of the substrate portion below the bridge conductor portion of the center conductor line increases, the amount of signal attenuation can be significantly reduced. For example, as can be observed in graph 900, even if 1 μm of the substrate portion below the bridge conductor portion of the center conductor line is removed to form a 1 μm gap between the bridge conductor portion and the remaining portion below the substrate, the signal attenuation can already be significantly reduced (as shown at reference numeral 902 of graph 900). As can also be seen in graph 900, where a 4 μm portion of the substrate beneath the bridge conductor portion of the center conductor line is removed to form a 4 μm gap between the bridge conductor portion and the remaining portion beneath the substrate, the amount of signal attenuation can be further reduced (as shown at 904 of graph 900) compared to the reduction in signal attenuation associated with a 1 μm gap between the bridge conductor portion and the remaining portion of the substrate, wherein even greater reductions in signal attenuation can be achieved at gaps greater than 4 μm between the bridge conductor portion and the remaining portion of the substrate. These graphical results of graph 900 regarding reductions in signal attenuation as a function of gap between the bridge conductor portion and the remaining portion of the substrate can correspond to (e.g., be associated with) significantly and gradually mitigating (e.g., reducing) energy losses in or associated with the substrate as the gap between the bridge conductor portion of the center conductor line of the CPW and the remaining portion beneath the substrate is increasingly increased.

[0073] According to various embodiments, the disclosed subject matter can employ a hybrid approach, wherein a bridge conductor portion of a center conductor line of a CPW can be raised to a certain height above a substrate, and a portion of the substrate below the bridge conductor portion can be removed to a certain depth to form a gap of a desired distance (e.g., total gap height) between the bridge conductor portion and the remainder of the substrate (e.g., having a surface at a certain depth). Fig.10 (Together with Figure 1 ), Fig.10 A schematic diagram illustrating a cross-sectional side view of an exemplary non-limiting circuit 1000 that can include a CPW that can be enhanced to include a bridging conductor portion of a conductor that can be elevated above a remainder of a substrate from which portions of the substrate can be removed to form a desired gap of a desired distance between the bridging conductor portion and a corresponding remainder of the substrate to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter.

[0074] As shown in the cross-sectional side view of the exemplary non-limiting circuit 1000, the circuit 1000 may be or may include a CPW that may include a substrate 1002 that may be formed of a desired substrate material, such as a desired dielectric material, as described more fully herein. The substrate forming component 108 may form the substrate 1002 to have a defined size and a defined shape, which may be suitable for forming the CPW of the circuit 1000.

[0075] The conductor forming component 110 can form a conductor line 1004, which can be a center conductor line of the CPW, which can be associated with (e.g., at least partially in contact with) the substrate 1002 (e.g., a surface of the substrate 1002) in a desired area of ​​the substrate 1002 (e.g., a center or substantially center area of ​​the substrate 1002). As part of forming the CPW, the conductor forming component 110 can form a return conductor line ( Fig.10 ), which can be arranged (e.g., deposited or placed) on the substrate 1002, on the opposite side or adjacent side of the conductor line 1004, wherein the return conductor line can be separated from the center conductor line 1004 by a corresponding spacing of a desired size (e.g., width).

[0076] According to various embodiments, to facilitate forming a CPW (e.g., enhancing the CPW), substrate forming component 108 may form substrate 1002 to remove (e.g., etch away) a portion of substrate 1002 in a desired area of ​​substrate 808 on or over which center conductor line 1004 may be disposed, such that a remaining portion of substrate 1002 may exist, including remaining portions 1006, 1008, and 1010 of substrate 1002, which may be a desired depth below other portions 1012, 1014, 1016, and 1018 of substrate 1002 that may be adjacent to remaining portions 1006, 1008, and 1010 of substrate 1002. The length and width of remaining portions 1006, 1008, and 1010 of substrate 1002 may be as desired according to defined circuit design standards. For example, the length of each remaining portion 1006, 1008, and 1010 of the substrate 1002 can be relatively longer (e.g., significantly longer) than the length of each other portion 1012, 1014, 1016, and 1018 of the substrate 1002. In some embodiments, the width of the remaining portions 1006, 1008, and 1010 of the substrate 1002 can extend from a portion of the substrate under the first return conductor line to another portion of the substrate under the second return conductor line. In other embodiments, the width of the remaining portions (e.g., 1006, 1008, and 1010) of the substrate 1002 can be smaller so that the substrate can extend beyond the covered return conductor toward the center conductor line 1004. Depending on defined circuit design criteria, for example, in order to achieve a desired reduction in energy losses in or associated with the substrate 1002, the depth of the remaining portions 1006, 1008 and 1010 of the substrate 1002 relative to the other portions 1012, 1014, 1016 and 1018 of the substrate 1002 and the height of the covering center conductor line 1004 may be desired.

[0077] In some embodiments, in addition to removing portions of the substrate 1002 to form the remaining portions 1006, 1008, and 1010 of the substrate 1002 having a desired depth, the bridge conductor portions of the center conductor line 1004 can be raised to a desired height above the substrate 1002. For example, the conductor forming component 110 (e.g., using the bridge forming component 112) can form the center conductor line 1004 to include bridge conductor portions (e.g., bridge conductor portions 1020, 1022, and 1024) and base conductor portions (e.g., base conductor portions 1026, 1028, 1030, and 1032), which can alternate and / or be adjacent to the bridge conductor portions along the center conductor line 1004. The conductor forming component 110 can form the base conductor portions (e.g., 1026, 1028, 1030, and 1032) so that they are disposed on the substrate 1002 and contact the substrate 1002 in a desired area (e.g., a central area) of the substrate 1002. The conductor forming member 110 (eg, utilizing the bridge forming member 112 ) may form respective bridge conductor portions 1020 , 1022 , and 1024 of the center conductor line 1004 to be elevated and disposed above respective remaining portions 1006 , 1008 , and 1010 of the substrate 1002 . In some embodiments, the conductor forming component 110 (e.g., using the bridge forming component 112) can form or construct bridge conductor portions (e.g., 1020, 1022 and 1024) to extend upward from associated (e.g., connected) base conductor portions (e.g., 1026, 1028, 1030 and 1032) to a desired height amount at a desired angle (e.g., 45°, 60°, 30° or other desired angle) relative to the associated (e.g., connected) base conductor portion, wherein each of these bridge conductor portions can extend through the substrate 1002 for a desired length (e.g., approximately 40 μm, or greater or less than 40 μm) at the desired height amount, and wherein each of these bridge conductor portions can extend downward at a desired angle at the other end to an adjacent base conductor portion of the center conductor line 1004 associated with (e.g., connected to) it at the other end of such bridge conductor portion.

[0078] In some embodiments, the conductor forming component 110 can form corresponding bridging conductor portions 1020, 1022 and 1024 of the center conductor line 1004 so as to be raised above other portions 1012, 1014, 1016 and 1018 of the substrate 1002 by a desired amount (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, or another desired amount) so that corresponding gaps of a defined distance (e.g., a total distance) can exist between the corresponding bridging conductor portions 1020, 1022 and 1024 of the center conductor line 1004 and the corresponding remaining portions 1006, 1008 and 1010 of the substrate 1002 to facilitate mitigation of energy losses in or associated with the substrate 1002. As a non-limiting example, the conductor forming component 110 can form the corresponding bridging conductor portions 1020, 1022 and 1024 of the center conductor line 1004 so that they are raised 2 μm above the other portions 1012, 1014, 1016 and 1018 of the substrate 1002, and the substrate forming component 108 can remove portions of the substrate 1002 to form remaining portions 1006, 1008 and 1010 of the substrate 1002 having a depth of 2 μm, so that there can be corresponding gaps of a defined distance of 4 μm between the corresponding bridging conductor portions 1020, 1022 and 1024 of the center conductor line 1004 and the corresponding remaining portions 1006, 1008 and 1010 of the substrate 1002.

[0079] According to various embodiments, the total distance between the respective bridging conductor portions 1020, 1022, and 1024 of the center conductor line 1004 and the respective remaining portions 1006, 1008, and 1010 of the substrate 1002 can be in a range from about 1 μm to about 10 μm. In one exemplary embodiment, the total distance can be 4 μm. Compared to conventional techniques for forming CPWs, the disclosed subject matter can have the advantage of desirably and significantly mitigating (e.g., reducing or minimizing) energy losses in or associated with the substrate 1002 by employing a hybrid approach. Moreover, in some embodiments, according to the disclosed subject matter, the conductor forming component 110 can form the CPW to have a desired amount of impedance, such as 50 ohms.

[0080] The system and / or equipment have been described herein (or will be) about the interaction between several parts.It should be understood that such system and parts can include those parts or sub-components specified therein, some of the parts or sub-components specified, and / or additional parts.Sub-components can also be implemented as communicatively coupled to other parts rather than the parts included in the parent part.In addition, one or more parts and / or sub-components can be combined into a single part that provides aggregation function.These parts can also interact with one or more other parts, and for the sake of brevity, these other parts are not specifically described here, but these parts are known to those skilled in the art.

[0081] Fig.11 A flow chart of an exemplary non-limiting method 1100 is shown, which can be used to desirably design a circuit (e.g., a quantum computing circuit) including a CPW that can be enhanced to mitigate energy loss, in accordance with various aspects and embodiments of the disclosed subject matter. In some embodiments, the method 1100 can be performed by, for example, a conductor forming component, a substrate forming component, and / or a processor component. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are or may be omitted.

[0082] At 1102, a dielectric substrate may be formed. The substrate forming component may form a dielectric substrate, which may have a defined size and a defined shape. In some embodiments, the substrate forming component may form the dielectric substrate on a ground plane layer. The ground plane layer may be or may include a desired conductive material. The dielectric substrate may be formed of a dielectric material, which may have a desired high thermal conductivity of less than 1 K, such as described more fully herein. The dielectric substrate and / or the ground plane layer may be part of a quantum computing circuit or a quantum computing device.

[0083] At 1104, a conductor line including a bridging conductor portion disposed above a portion of a dielectric substrate may be formed, wherein a gap of a defined distance may be formed between the bridging conductor portion of the conductor line and a surface of the portion of the dielectric substrate facing the bridging conductor portion. The conductor forming component may form a conductor line (e.g., a center conductor line) to include a bridging conductor portion that may be disposed above the portion of the substrate, wherein a gap of a defined distance may be formed between the bridging conductor portion of the conductor line and a surface of the dielectric substrate facing the bridging conductor portion. The conductor line may be a center conductor line of a CPW, which may be part of a quantum computing circuit or a quantum computing device. The conductor forming component may also form two return conductor lines on the dielectric substrate, wherein there may be a return conductor line on each side of the center conductor line, and wherein the return conductor lines may be separated from the center conductor line by a space of a defined size. In some embodiments, when a ground plane layer is employed, the ground plane layer may be a third return conductor of the CPW.

[0084] In some embodiments, in order to create a gap of a defined distance between a bridging conductor portion and a dielectric substrate, a conductor forming component can form the conductor line to include a plurality of bridging conductor portions, the plurality of bridging conductor portions including a bridge conductor portion having a defined length that can be raised above the dielectric substrate by the defined distance (e.g., 4 μm, or other desired distance in the range of approximately 1 μm to 10 μm), wherein a base conductor portion of the conductor line can be located between and / or adjacent to the bridging conductor portions and can contact the surface of the dielectric substrate.

[0085] In other embodiments, in order to create a gap of a defined distance between the bridging conductor portion and the dielectric substrate, the substrate forming component can remove (e.g., etch away or otherwise remove) a portion of the dielectric substrate below the bridging conductor portion of the conductor line (e.g., the center conductor line) so that the bridging conductor portion of the conductor line can be a defined distance above the surface of the remaining dielectric substrate (e.g., the dielectric substrate remaining after removing the portion of the dielectric substrate), and the base conductor portion of the conductor line can be in contact with other portions of the surface of the dielectric substrate that have not been removed and located between and / or adjacent to the space formed by removing the portion of the dielectric substrate.

[0086] In other embodiments, the disclosed subject matter may employ a hybrid approach that may raise the bridging conductor portion above other portions of the dielectric substrate associated with the base conductor portion of the conductor line, and may also remove portions of the dielectric substrate beneath the bridging conductor portion of the conductor line to achieve a desired gap of a defined distance between the bridging conductor portion and the dielectric substrate.

[0087] Fig.12 A flow chart of another exemplary non-limiting method 1200 for forming a CPW that can be enhanced to include a bridging conductor portion of a conductor line that can be elevated above a substrate to mitigate energy losses in accordance with various aspects and embodiments of the disclosed subject matter is shown. The method 1200 can be performed by, for example, a conductor forming component, a substrate forming component, and / or a processor component. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are or may be omitted.

[0088] At 1202, a dielectric substrate having a defined size and a defined shape may be formed. A substrate forming component may form a dielectric substrate having a defined size and a defined shape. In some embodiments, the substrate forming component may form the dielectric substrate on a ground plane layer, which may be or may include a desired conductive material. The dielectric substrate may be formed of a dielectric material, which may have a desired high thermal conductivity of less than 1 K, such as described more fully herein. The dielectric substrate and / or the ground plane layer may be part of a quantum computing circuit or a quantum computing device.

[0089] At 1204, a conductor line can be formed, the conductor line including a bridge conductor portion elevated above and disposed above a portion of the dielectric substrate, and a base conductor portion located between the bridge conductor portions and in contact with the dielectric substrate, wherein a gap of a defined distance can be formed between the bridge conductor portion of the conductor line and a portion of the dielectric substrate facing the bridge conductor portion, based at least in part on the elevation of the bridge conductor portion above the dielectric substrate. The conductor line can be a center conductor line of a CPW, which can be part of a quantum computing circuit or a quantum computing device. The conductor forming component can form the conductor line to include a bridge conductor portion (e.g., a sequence of bridge conductor portions) that can be elevated above and disposed above corresponding portions of the dielectric substrate. The conductor forming component can elevate the bridge conductor portion above the surface of the dielectric substrate by a defined distance to form a gap of a defined distance (e.g., 4 μm, or other desired distance in the range of about 1 μm to 10 μm) between the bridge conductor portion and the portion of the dielectric substrate.

[0090] At 1206, a first return conductor line may be formed on a dielectric substrate, wherein a space of a defined size (e.g., width) may exist between the conductor line and the first return conductor line. At 1208, a second return conductor line may be formed on the dielectric substrate, wherein a space of a defined size may exist between the conductor line and the second return conductor line. The conductor forming component may form the first return conductor line and the second return conductor line on opposite sides of a conductor line (e.g., a center conductor line) of the CPW, wherein the conductor line may be located between the first return conductor line and the second return conductor line. The conductor forming component may form the first return conductor line and the second return conductor line relative to the conductor line, such that a space of a defined size may exist between the conductor line and the first return conductor line, and a space of a defined size may exist between the conductor line and the second return conductor line.

[0091] Fig.13A flow chart of an exemplary non-limiting method 1300 for forming a CPW that can be enhanced to include a bridging conductor portion of a center conductor line that can be disposed over a remaining portion of a substrate that can remain after removing portions of the substrate in order to mitigate energy losses in or associated with the substrate is shown in accordance with various aspects and embodiments of the disclosed subject matter. The method 1300 can be performed by, for example, a conductor forming component, a substrate forming component, and / or a processor component. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are or may be omitted.

[0092] At 1302, a dielectric substrate of a defined size and a defined shape may be formed. A substrate forming component may form a dielectric substrate of a defined size and a defined shape. In some embodiments, the substrate forming component may form the dielectric substrate on a ground plane layer, which may be or may include a desired conductive material. The dielectric substrate may be formed of a dielectric material, which may have a desired high thermal conductivity of less than 1 K, such as described more fully herein. The dielectric substrate and / or the ground plane layer may be part of a quantum computing circuit or a quantum computing device.

[0093] At 1304, a portion of the dielectric substrate may be removed in or near an area of ​​the dielectric substrate on which a conductor line (e.g., a center conductor line) may be formed, wherein other portions of the dielectric substrate in the area may be located between and / or adjacent to remaining portions of the dielectric substrate remaining after the portions of the dielectric substrate are removed, and wherein a surface of the remaining portion of the dielectric substrate (e.g., a top-facing surface) may be lower than the other portions of the dielectric substrate by a defined distance (e.g., a depth). The substrate forming component may remove (e.g., etch away) a portion of the dielectric substrate in or near (e.g., at least partially surrounding) an area on the dielectric substrate on which a conductor line may be formed, such that there may be remaining portions of the dielectric substrate that may remain after the portions of the dielectric substrate are removed, and such that there may be other portions of the dielectric substrate that may be located between and / or adjacent to the remaining portions of the dielectric substrate (e.g., at least some of the other portions of the dielectric substrate may be located between the remaining portions of the dielectric substrate). The height of the surface of the remaining portion of the dielectric substrate can be lower than the surface of the other portion of the dielectric substrate (e.g., the top-facing surface) by a defined distance (e.g., 4 μm, or other desired distance in the range of about 1 μm to 10 μm). Other sizes (e.g., width and length) of the removed portion of the dielectric substrate (and correspondingly the size of the remaining portion of the dielectric substrate) can be as desired, depending on the defined circuit design standards.

[0094] At 1306, a conductor line (e.g., a center conductor line) can be formed that includes a bridge conductor portion disposed above a remaining portion of the dielectric substrate and a base conductor portion located between and / or adjacent to the bridge conductor portion and in contact with other portions of the dielectric substrate, wherein a gap of a defined distance can be formed between the bridge conductor portion of the conductor line and a remaining portion of the dielectric substrate facing the bridge conductor portion, at least in part based on (e.g., in part due to) the removal of a portion of the dielectric substrate to form the remaining portion. The conductor line can be a center conductor line of a CPW, which can be part of a quantum computing circuit or a quantum computing device. The conductor forming component can form the conductor line to include a bridge conductor portion (e.g., a sequence of bridge conductor portions) that can be disposed above (e.g., suspended on or above) a corresponding remaining portion of the dielectric substrate. The conductor forming member may form the base conductor portion of the conductor line so that the base conductor portion contacts other portions of the dielectric substrate, which other portions may be located between and / or adjacent to the remaining portions of the dielectric substrate (at least some of the other portions of the dielectric substrate may be located between the remaining portions of the dielectric substrate). Since the remaining portions of the dielectric substrate may be a defined distance below other portions of the dielectric substrate on which the base conductor portion of the conductor line is disposed, a gap of a defined distance may exist between the bridging conductor portion of the conductor line and the remaining portions of the dielectric substrate.

[0095] At 1308, a first return conductor line may be formed on a dielectric substrate, wherein a space of a defined size (e.g., width) may exist between the conductor line and the first return conductor line. At 1310, a second return conductor line may be formed on a dielectric substrate, wherein a space of a defined size may exist between the conductor line and the second return conductor line. The conductor forming component may form the first return conductor line and the second return conductor line on opposite sides of a conductor line (e.g., a center conductor line) of the CPW, wherein the conductor line may be located between the first return conductor line and the second return conductor line. The conductor forming component may form the first return conductor line and the second return conductor line relative to the conductor line, such that a space of a defined size may exist between the conductor line and the first return conductor line, and a space of a defined size may exist between the conductor line and the second return conductor line.

[0096] For simplicity of explanation, method and / or computer-implemented method are depicted and described as a series of actions. But it is understood and appreciated that the disclosed subject matter is not limited by the actions and / or order of actions shown, for example, the actions can occur in various orders and / or concurrently, and can occur together with other actions not presented and described herein. In addition, not all the actions shown are necessary for realizing the computer-implemented method according to the disclosed subject matter. In addition, it will be understood and appreciated by those skilled in the art that the computer-implemented method can be represented as a series of interrelated states via state diagrams or events alternatively. In addition, it should also be understood that the computer-implemented method disclosed below and throughout this specification can be stored on a product, so that such a computer-implemented method can be transmitted and transferred to a computer. The term product as used herein is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0097] To provide context for various aspects of the disclosed subject matter, Fig.14 The following discussion is intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Fig.14 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein may be facilitated is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are or may be omitted. Fig.14, a suitable operating environment 1400 for implementing various aspects of the present disclosure may also include a computer 1412. The computer 1412 may also include a processing unit 1414, a system memory 1416, and a system bus 1418. The system bus 1418 couples system components including, but not limited to, the system memory 1416 to the processing unit 1414. The processing unit 1414 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 1414. The system bus 1418 may be any of several bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI). The system memory 1416 may also include volatile memory 1420 and non-volatile memory 1422. The basic input / output system (BIOS), which contains basic routines such as transferring information between elements within the computer 1412 at startup, is stored in the non-volatile memory 1422. As an illustration and not limitation, the non-volatile memory 1422 may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), flash memory, or a non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). The volatile memory 1420 may also include a random access memory (RAM) that acts as an external cache memory. As an illustration and not limitation, RAM can be obtained in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0098] Computer 1412 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Fig.14Disk storage 1424 is shown. Disk storage 1424 may also include, but is not limited to, devices such as a disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 1424 may also include storage media alone or in combination with other storage media, including, but not limited to, optical disk drives such as a compact disk ROM device (CD-ROM), a CD recordable drive (CD-R drive), a CD rewritable drive (CD-RW drive), or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of disk storage 1424 to system bus 1418, a removable or non-removable interface, such as interface 1426, is typically used. Fig.14 Also shown is software that acts as an intermediary between a user and the basic computer resources described in the appropriate operating environment 1400. Such software may also include, for example, an operating system 1428. The operating system 1428 may be stored in the disk storage 1424, and it is used to control and allocate the resources of the computer 1412. The system application 1430 utilizes the management of resources by the operating system 1428 through, for example, program modules 1432 and program data 1434 stored in the system storage 1416 or the disk storage 1424. It should be understood that the present disclosure can be implemented with various operating systems or combinations of operating systems. The user enters commands or information to the computer 1412 through an input device 1436. The input device 1436 includes, but is not limited to, a pointing device such as a mouse, a tracking ball, a stylus, a touch pad, a keyboard, a microphone, a joystick, a game pad, a satellite dish, a scanner, a TV tuner card, a digital camera, a digital video camera, a web camera, etc. These and other input devices are connected to the processing unit 1414 via an interface port 1438 through the system bus 1418. Interface ports 1438 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 1440 use some of the same types of ports as input devices 1436. Thus, for example, a USB port may be used to provide input to computer 1412 and output information to output devices 1440 from computer 1412. Output adapters 1442 are provided to illustrate that there are some output devices 1440, such as monitors, speakers, and printers, among other output devices 1440 that require special adapters. As an illustration and not limitation, output adapters 1442 include graphics cards and sound cards that provide a method of connection between output devices 1440 and system bus 1418. It should be noted that other devices and / or systems of devices provide input and output capabilities, such as remote computers 1444.

[0099] The computer 1412 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1444. The remote computer 1444 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer device or other common network node, etc., and can also generally include many or all of the elements described with respect to the computer 1412. For simplicity, only the memory storage device 1446 is shown with the remote computer 1444. The remote computer 1444 is logically connected to the computer 1412 through a network interface 1448 and then physically connected through a communication connection 1450. The network interface 1448 includes a wired and / or wireless communication network, such as a local area network (LAN), a wide area network (WAN), a cellular network, etc. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like integrated services digital network (ISDN) and its variants, packet switching networks, and digital subscriber lines (DSL). The communication connection 1450 refers to the hardware / software used to connect the network interface 1448 to the system bus 1418. Although the communication connection 1450 is shown as being internal to the computer 1412 for clarity of illustration, it may also be external to the computer 1412. For exemplary purposes only, the hardware / software used to connect to the network interface 1448 may also include internal and external technologies such as modems including conventional telephone grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0100] One or more embodiments may be systems, methods, devices and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of one or more embodiments. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein should not be interpreted as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0101] The computer-readable program instructions described herein can be downloaded to the corresponding computing / processing equipment from the computer-readable storage medium, or via a network, such as the Internet, a local area network, a wide area network and / or a wireless network, downloaded to an external computer or an external storage device. The network can include copper transmission cables, optical transmission optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or the network interface in each computing / processing equipment receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in the corresponding computing / processing equipment. The computer-readable program instructions for performing the operation of the disclosed subject can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcodes, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages, wherein the programming language includes object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and process programming languages ​​(such as "C" programming languages ​​or similar programming languages). Computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider through the Internet). In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can execute computer-readable program instructions to personalize the electronic circuits by utilizing the state information of the computer-readable program instructions, so as to perform aspects of the disclosed subject matter.

[0102] This paper describes various aspects of the disclosed subject matter with reference to the flowchart illustration and / or block diagram of the method, device (system) and computer program product of the embodiment disclosed in the present subject matter.It will be understood that each frame of the flowchart and / or block diagram and the combination of frames in the flowchart and / or block diagram can be realized by computer-readable program instructions.These computer-readable program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a method for realizing the function / action specified in one or more frames of the flowchart and / or block diagram.These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide a computer, a programmable data processing device and / or other equipment to work in a particular manner, so that the computer-readable storage medium having instructions stored therein includes a product, and the product includes instructions for realizing various aspects of the function / action specified in one or more frames of the flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational actions to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0103] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the various embodiments of the disclosed subject matter.In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing the specified logical function.In some alternative embodiments, the function noted in the frame may not occur in the order noted in the figure.For example, depending on the function involved, the two frames shown in succession can be performed substantially simultaneously, or these frames can sometimes be performed in reverse order.It will also be noted that the combination of the frames in each frame of the block diagram and / or the flow chart illustration and the block diagram and / or the flow chart illustration can be realized by a dedicated hardware-based system that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0104] Although the subject matter is described above in the general context of computer executable instructions of a computer program product running on one and / or multiple computers, it will be appreciated by those skilled in the art that the present disclosure may also be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. In addition, it will be appreciated by those skilled in the art that the computer-implemented methods disclosed herein may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, large computers, and computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The various aspects shown may also be practiced in a distributed computing environment in which tasks are performed by a remote processing device linked by a communication network. However, some aspects of the present disclosure, if not all aspects, may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in local and remote memory storage devices.

[0105] As used in this application, the terms "component", "system", "platform", "interface", etc. may refer to and / or may include computer-related entities or entities related to an operating machine having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and / or a computer running on a processor. As an illustration, both an application program and a server running on a server may be a component. One or more components may reside in a process and / or a thread of execution, and a component may be located on a computer and / or distributed between two or more computers. In another example, the corresponding component may be executed from various computer-readable media having various data structures stored thereon. These components may communicate via local and / or remote processes, for example, according to a signal having one or more data packets (e.g., data from a component, which interacts with another component in a local system, a distributed system, and / or interacts with other systems via a network such as the Internet). As another example, a component may be a device having a specific functionality provided by a mechanical component operated by an electrical or electronic circuit that is operated by a software or firmware application executed by a processor. In this case, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides a specific functionality by electronic components rather than mechanical components, where the electronic components may include a processor or other method to execute software or firmware that at least partially imparts the functionality to the electronic components. In one aspect, the component may emulate the electronic component via a virtual machine, such as within a cloud computing system.

[0106] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X uses A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing instances. In addition, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and the drawings should generally be interpreted as meaning "one or more". As used herein, the terms "example" and / or "exemplary" are used to indicate use as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to these examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as being preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0107] As used in this specification, the term "processor" may refer to substantially any computational processing unit or device, including but not limited to a single-core processor; a single processor with software multithreaded execution capability; a multi-core processor; a multi-core processor with software multithreaded execution capability; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. In addition, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the processor may employ a nanoscale architecture, such as, but not limited to, transistors, switches, and gates based on molecules and quantum dots, in order to optimize space usage or enhance the performance of user devices. The processor may also be implemented as a combination of computational processing units. In the present disclosure, terms such as "store", "storage", "data store", "data storage", "data storage", "database", and substantially any other information storage component related to the operation and functionality of the component are used to refer to a "memory component", an entity contained in a "memory", or a component that includes a memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, for example, which may act as an external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). In addition, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0108] The above description includes only examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for the purpose of describing the present disclosure, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. In addition, to the extent that the terms "includes," "has," "possess," and the like are used in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a manner similar to that in which the term "comprising" is interpreted when used as a transitional word in the claims. Descriptions of various embodiments have been presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: substrate; as well as Coplanar waveguides, including: First return wire, A second return conductor, and a center conductor line extending continuously in a direction parallel to the first and second return conductors, located between and separated from the first and second return conductors, wherein the center conductor line includes a plurality of base conductor portions disposed directly on the substrate, and a bridge portion disposed over a portion of the substrate, wherein a gap of a defined distance is formed between the bridge portion of the center conductor line and a surface of the portion of the substrate facing the bridge portion, the gap reducing an amount of energy loss associated with the substrate.

2. The device according to claim 1, wherein the bridge portion is a first bridge portion, and wherein the center conductor line includes a bridge portion group and a base conductor portion, the bridge portion group includes the first bridge portion and the second bridge portion, and the base conductor portion is arranged on the substrate and is located between the first bridge portion and the second bridge portion.

3. The device of claim 2, wherein the first bridge portion and the second bridge portion are elevated above the base conductor portion and the surface of the substrate to form a plurality of gaps including the gap between the substrate and the first bridge portion and the second bridge portion.

4. The device according to any one of claims 2 to 3, wherein the portion of the substrate is a first portion of the substrate, wherein the gap is a first gap, and wherein a first section of the substrate is removed to form the first gap between the first portion of the substrate and the first bridging portion disposed over the first portion of the substrate, and a second section of the substrate is removed to form a second gap between the second portion of the substrate and the second bridging portion disposed over the second portion of the substrate.

5. A device according to any one of preceding claims 2 to 3, wherein a conductive layer is disposed on the substrate, wherein the conductive layer includes a first portion of the conductive layer, a second portion of the conductive layer, and the center conductor line is located between the first portion of the conductive layer and the second portion of the conductive layer, wherein a first space is formed between the center conductor line and the first portion of the conductive layer, and a second space is formed between the center conductor line and the second portion of the conductive layer.

6. The device of claim 1 , wherein the defined distance formed between the bridging portion of the center conductor line and the surface of the portion of the substrate is a sufficient distance to reduce an amount of energy loss associated with the substrate without exceeding a defined distance threshold amount based on defined circuit design criteria.

7. A device according to any one of the preceding claims 2 to 3, wherein the central conductor line is formed from a superconducting material.

8. A device according to any one of the preceding claims 2 to 3, wherein the substrate comprises a dielectric material and has a thermal conductivity level that meets a defined threshold conductivity level.

9. A device according to any one of the preceding claims 2 to 3, wherein the substrate and the coplanar waveguide are part of a quantum computing circuit comprising qubits.

10. A method comprising: forming a substrate for quantum devices; as well as A coplanar waveguide is formed, the coplanar waveguide comprising: First return wire, A second return conductor, and a center conductor line extending continuously in a direction parallel to the first and second return conductors, located between and separated from the first and second return conductors, wherein the center conductor line includes a plurality of base conductor portions disposed directly on the substrate, and a bridge conductor portion disposed over a portion of the substrate, wherein a gap of a defined distance is formed between the bridge conductor portion of the center conductor line and a surface of the portion of the substrate facing the bridge conductor portion, the gap reducing an amount of energy loss associated with the substrate.

11. The method of claim 10, wherein the bridging conductor portion is a first bridging conductor portion, and wherein forming the coplanar waveguide comprises forming the center conductor line including a bridging conductor portion group and a base conductor portion, the bridging conductor portion group including the first bridging conductor portion and the second bridging conductor portion, the base conductor portion being disposed on the substrate and located between the first bridging portion and the second bridging portion.

12. The method of claim 11, wherein the first and second bridge conductor portions are formed at elevated levels relative to the base conductor portion and the surface of the substrate to form a plurality of gaps including the gap between the substrate and the first and second bridge conductor portions.

13. The method according to any one of claims 11 to 12, wherein the portion of the substrate is a first portion of the substrate, wherein the gap is a first gap, and wherein the method further comprises: removing a first portion of the substrate to form the first gap between the first portion of the substrate and the first bridging conductor portion disposed above the first portion of the substrate; as well as The second portion of the substrate is removed to form a second gap between the second portion of the substrate and the second bridge conductor portion disposed above the second portion of the substrate.

14. The method according to any one of claims 10 to 12, wherein a conductive layer is disposed on the substrate, and wherein the conductive layer includes a first portion of the conductive layer, a second portion of the conductive layer, and the conductor line located between the first portion of the conductive layer and the second portion of the conductive layer, wherein a first space is formed between the conductor line and the first portion of the conductive layer, and a second space is formed between the conductor line and the second portion of the conductive layer.

15. A method according to any one of claims 10 to 12, wherein the centre conductor line is formed of a superconducting material, and wherein the substrate comprises a dielectric material and has a thermal conductivity level that meets a defined minimum threshold conductivity level.

16. The method of any one of claims 10 to 12, wherein the substrate and the coplanar waveguide are part of a quantum computing circuit comprising qubits.

17. A computer program product for facilitating forming a quantum computing circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therein, the program instructions executable by a processor to cause the processor to: forming a substrate comprising a dielectric material to enable creation of circuit components of the quantum computing circuit; and A coplanar waveguide is formed, the coplanar waveguide comprising: First return wire, A second return conductor, and A center conductor line extending continuously in a direction parallel to the first return conductor and the second return conductor, located between and separated from the first return conductor and the second return conductor, wherein the center conductor line includes a plurality of base conductor portions disposed directly on the substrate, and a bridge conductor portion disposed over a portion of the substrate, wherein a space of a defined distance is formed between the bridge conductor portion of the center conductor line and a surface of the portion of the substrate facing the bridge conductor portion, the space reducing an amount of energy loss associated with the substrate.

18. The computer program product of claim 17, wherein the bridging conductor portion is a first bridging conductor portion, wherein the portion of the substrate is a first portion of the substrate, wherein the space is a first space, and wherein the forming the coplanar waveguide comprises: creating a center conductor line including a bridge conductor portion group and a base conductor portion, the bridge conductor portion group including the first bridge conductor portion and the second bridge conductor portion, the base conductor portion being disposed on the substrate and located between the first bridge conductor portion and the second bridge conductor portion; wherein the first bridge conductor portion and the second bridge conductor portion are elevated above the surface of the base conductor portion and the substrate to form a plurality of spaces including the first space between the substrate and the first bridge conductor portion and the second bridge conductor portion, or A first portion of the substrate is removed to form the first space between the first portion of the substrate and the first bridge conductor portion located above the first portion of the substrate, and a second portion of the substrate is removed to form a second space between the second portion of the substrate and the second bridge conductor portion located above the second portion of the substrate.

19. A system comprising: a memory storing computer executable components; as well as a processor operatively coupled to the memory, the processor executing computer executable components, the computer executable components comprising: a substrate forming component that forms a dielectric substrate as part of a quantum computing circuit; and A conductor forming part, which forms a coplanar waveguide, the coplanar waveguide comprising: First return wire, A second return conductor, and a center conductor line extending continuously in a direction parallel to the first return conductor and the second return conductor, located between and separated from the first return conductor and the second return conductor, wherein the center conductor line includes a plurality of base conductor portions disposed directly on the dielectric substrate, and a bridge conductor portion disposed over a portion of the dielectric substrate, wherein a space of a defined distance is formed between the bridge conductor portion of the center conductor line and a surface of the portion of the dielectric substrate facing the bridge conductor portion, the space reducing an amount of energy loss associated with the dielectric substrate.

20. The system of claim 19, wherein the bridge conductor portion is a first bridge conductor portion, and wherein the conductor forming member forms the coplanar waveguide to include a center conductor line forming a set of bridge conductor portions and a base conductor portion, wherein the set of bridge conductor portions includes the first bridge conductor portion and a second bridge conductor portion, wherein the base conductor portion is arranged on the dielectric substrate and is located between the first bridge conductor portion and the second bridge conductor portion, and The first bridge conductor portion and the second bridge conductor portion are at an elevated level compared to the base conductor portion and the surface of the dielectric substrate to form a plurality of spaces including the space between the dielectric substrate and the first bridge conductor portion and the second bridge conductor portion.

21. The system of claim 20, wherein the bridging conductor portion is a first bridging conductor portion, wherein the portion of the dielectric substrate is a first portion of the dielectric substrate, wherein the space is a first space, wherein the substrate forming member removes a first section of the dielectric substrate to form the first portion of the dielectric substrate, and forms the first space between the first portion of the dielectric substrate and the first bridge conductor portion located above the first portion of the dielectric substrate, and The substrate forming member removes a second section of the dielectric substrate to form a second portion of the dielectric substrate, and forms a second space between the second portion of the dielectric substrate and the second bridge conductor portion located above the second portion of the dielectric substrate.

22. A computer program product for facilitating creation of a quantum computing circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therein, the program instructions being executable by a processor to cause the processor to: forming a dielectric substrate comprising a dielectric material to enable creation of circuit components of the quantum computing circuit; and A coplanar waveguide is formed, the coplanar waveguide comprising: First return wire, A second return conductor, and a center conductor line extending continuously in a direction parallel to the first return conductor and the second return conductor, located between and separated from the first return conductor and the second return conductor, wherein the center conductor line includes a plurality of base conductor portions disposed directly on the substrate, and a bridge portion disposed over a portion of the dielectric substrate, wherein a gap of a defined distance is formed between the bridge portion of the center conductor line and a surface of the portion of the dielectric substrate facing the bridge portion, the gap reducing an amount of energy loss associated with the dielectric substrate.

23. The computer program product of claim 22, wherein the bridge portion is a first bridge portion, wherein the portion of the dielectric substrate is a first portion of the dielectric substrate, wherein the gap is a first gap, and wherein the forming of the coplanar waveguide comprises: forming the center conductor line including a bridge portion group and a base conductor portion, the bridge portion group including the first bridge portion and the second bridge portion, and the base conductor portion being disposed on a dielectric substrate and located between the first bridge portion and the second bridge portion, wherein the first bridge portion and the second bridge portion are at elevated levels relative to the base conductor portion and the surface of the dielectric substrate to form a plurality of gaps including the first gap between the dielectric substrate and the first bridge portion and the second bridge portion, or wherein a first section of the dielectric substrate is etched away to form the first gap between the first portion of the dielectric substrate and the first bridge portion disposed over the first portion of the dielectric substrate, and a second section of the dielectric substrate is etched away to form a second gap between the second portion of the dielectric substrate and the second bridge portion disposed over the second portion of the dielectric substrate, and wherein the dielectric substrate is formed on a ground plane layer.

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