Electronic component and method of manufacturing the same

Abstract

[Problem] The object of the present application is to satisfy the characteristics required for both elements in an electronic component in which an element requiring high processing precision like a capacitor and an element requiring sufficient conductor thickness like an inductor are integrated. [Solution] An electronic component (1) has conductor layers (M1 to M4) and insulating resin layers (11 to 14) alternately laminated on a substrate (2). The insulating resin layer (11) located at the lowermost layer is thinner than the insulating resin layers (12 to 14), and the insulating resin layers (12 to 14) have a lower coefficient of thermal expansion than the insulating resin layer (11). Thus, an element requiring high processing precision like a capacitor can be embedded in the thin insulating resin layer (11) located at the lowermost layer, and an element requiring sufficient conductor thickness like an inductor can be embedded in the thick insulating resin layers (12 to 14). Furthermore, since the insulating resin layers (12 to 14) have a low coefficient of thermal expansion, warping and peeling can also be suppressed.

Description

Technical Field

[0001] This invention relates to electronic components and methods for manufacturing the same, and particularly to electronic components having a structure in which multiple conductor layers and multiple insulating layers are alternately stacked on a substrate, and methods for manufacturing the same. Background Technology

[0002] Patent Document 1 discloses an LC filter having a structure in which a capacitor and an inductor are formed on a substrate. In the LC filter described in Patent Document 1, the lower electrode of the capacitor and the coil pattern constituting the inductor are arranged on the same conductor layer.

[0003] [Existing Technical Documents]

[0004] Patent Document 1: Japanese Patent Application Publication No. 2008-34626 Summary of the Invention

[0005] [The technical problem that the invention aims to solve]

[0006] However, when the lower electrode of the capacitor and the coil pattern are arranged on the same conductor layer, if the conductor thickness of the coil pattern is increased to improve the Q value of the coil, the conductor thickness of the lower electrode of the capacitor will inevitably increase as well. Therefore, it is difficult to form the upper electrode with high precision on the lower electrode, resulting in a problem of increased capacitor deviation.

[0007] Therefore, the object of the present invention is to satisfy the required characteristics of both components in an electronic component that integrates components requiring high processing precision, such as capacitors, and components requiring sufficient conductor thickness, such as inductors. Furthermore, the object of the present invention is to provide a method for manufacturing such an electronic component.

[0008] [Methods used to solve technical problems]

[0009] An electronic component according to one aspect of the present invention is characterized by comprising: a substrate and a plurality of conductor layers and a plurality of insulating resin layers alternately stacked on the substrate, the plurality of insulating resin layers comprising a first insulating resin layer located at the bottom and a plurality of second insulating resin layers located on the first insulating resin layer, the plurality of conductor layers comprising a first conductor layer embedded in the first insulating resin layer and a plurality of second conductor layers respectively embedded in the plurality of second insulating resin layers, the first conductor layer comprising a capacitor comprising a lower electrode and an upper electrode, the upper electrode being stacked on the lower electrode via a dielectric film made of an inorganic insulating material, the plurality of second conductor layers comprising a coil pattern, the thickness of the first insulating resin layer being thinner than that of the second insulating resin layer, and the coefficient of thermal expansion of the second insulating resin layer being smaller than that of the first insulating resin layer.

[0010] According to the present invention, since the capacitor, which requires high processing precision, is embedded in the thin first insulating resin layer at the bottom, and the inductor, which requires sufficient conductor thickness, is embedded in the thicker second insulating resin layer, the required characteristics of both components can be satisfied. Furthermore, since the second insulating resin layer has a lower coefficient of thermal expansion, warping and peeling can be suppressed. Here, the first insulating resin layer can also be made of a polyimide resin. Alternatively, the second insulating resin layer can be made of a material in which filler has been added to an epoxy resin.

[0011] In this invention, each of the plurality of second conductor layers may be thicker than the combined thickness of the lower electrode and the upper electrode. This can improve the Q value of the coil.

[0012] In this invention, the first through-hole conductor may also have a rectangular planar shape, be disposed through the first insulating resin layer, and connect the first conductor layer to the second conductor layer; the second through-hole conductor may have a circular planar shape, be disposed through the second insulating resin layer, and connect different second conductor layers to each other. This ensures sufficient area of ​​the first through-hole conductor and prevents peeling near the second through-hole conductor.

[0013] In this invention, the first insulating resin layer may be partially removed, and the insulating resin layer in contact with the first insulating resin layer among a plurality of second insulating resin layers may be embedded in the portion where the first insulating resin layer has been removed. This further increases the volume of the second insulating resin layer, which has a low coefficient of thermal expansion, thus making it more difficult for the electronic component to warp overall.

[0014] The method for manufacturing an electronic component according to the present invention is characterized by comprising: a first step of forming a first conductor layer on a substrate, the first conductor layer including a capacitor comprising a lower electrode and an upper electrode, the upper electrode being laminated on the lower electrode via a dielectric film made of an inorganic insulating material; a second step of forming a first insulating resin layer covering the first conductor layer; and a third step of alternately forming a second conductor layer and a second insulating resin layer on the first insulating resin layer, the second conductor layer including a coil pattern, the second insulating resin layer being thicker than the first insulating resin layer, and the second insulating resin layer having a smaller coefficient of thermal expansion than the first insulating resin layer.

[0015] According to the present invention, a capacitor requiring high processing precision can be formed in the first conductor layer, and an inductor requiring sufficient conductor thickness can be formed in the second conductor layer. Furthermore, since the second insulating resin layer has a low coefficient of thermal expansion, warping and peeling can also be suppressed.

[0016] In this invention, the first insulating resin layer can be formed by coating in the second step, and the second insulating resin layer can be formed by lamination in the third step. This allows for the easy formation of first and second insulating resin layers of different thicknesses.

[0017] In this invention, the second conductor layer may also have a first through-hole conductor and a second through-hole conductor; the first through-hole conductor is disposed in a manner that penetrates the first insulating resin layer, and the first through-hole conductor connects the lowest conductor layer among a plurality of second conductor layers to the first conductor layer; the second through-hole conductor is disposed in a manner that penetrates the second insulating resin layer, and the second through-hole conductor connects the plurality of second conductor layers to each other; the bottom of the first through-hole conductor is flat, the surfaces of the plurality of second conductor layers have recesses at the portions connected to the second through-hole conductor, and the bottom of the second through-hole conductor has a convex shape that is recessed into the recesses. Therefore, since the bottom of the first through-hole conductor is flat, the capacitor deviation caused by the unevenness of the lower and upper electrodes is suppressed. On the other hand, since the bottom of the second through-hole conductor has a convex shape that is recessed into the recesses, the contact area between the second conductor layer and the third conductor layer is increased, thereby improving their sealing performance.

[0018] In this invention, the planar shape of the first through-hole conductor can be rectangular, and the planar shape of the second through-hole conductor can be circular. This ensures sufficient area of ​​the first through-hole conductor and prevents peeling near the second through-hole conductor.

[0019] In this invention, the multiple second conductor layers may be thicker than the combined thickness of the lower and upper electrodes. This can improve the Q value of the coil.

[0020] In one aspect of the manufacturing method of the electronic component of the present invention, the method may further include a fourth step and a fifth step; in the fourth step, an opening is formed in the first insulating resin layer to expose the first conductor layer; in the fifth step, an opening is formed in the second insulating resin layer to expose the second conductor layer; the fourth step is performed by photolithography, and the fifth step is performed by laser processing. Therefore, higher processing accuracy can be obtained in the fourth step, and the opening in the first insulating resin layer can be processed into any planar shape. Furthermore, the fifth step can be implemented inexpensively, and a non-photosensitive material can be used as the material for the second insulating resin layer.

[0021] Another aspect of the electronic component of the present invention is characterized by comprising: a substrate; a first conductor layer formed on the substrate, which includes a capacitor comprising a lower electrode and an upper electrode, the upper electrode being laminated on the lower electrode via a dielectric film made of an inorganic insulating material; a first insulating resin layer covering the first conductor layer; a second conductor layer formed on the first insulating resin layer; a second insulating resin layer covering the second conductor layer; and a third conductor layer formed on the second insulating resin layer; wherein the second and third conductor layers include coil patterns, the first insulating resin layer has a first opening exposing the first conductor layer, the second insulating resin layer has a second opening exposing the second conductor layer, the second conductor layer has a first through-hole conductor connected to the first conductor layer via the first opening, the third conductor layer has a second through-hole conductor connected to the second conductor layer via the second opening, the bottom of the first through-hole conductor is flat, the surface of the second conductor layer has a recess at the portion connected to the second through-hole conductor, and the bottom of the second through-hole conductor has a convex shape such that it is recessed into the recess.

[0022] According to the present invention, components requiring high processing precision, such as capacitors, are embedded in the bottommost first insulating resin layer, while components requiring sufficient conductor thickness, such as inductors, are embedded in the second and third insulating resin layers. Therefore, the required characteristics of both components can be satisfied. Furthermore, since the bottom of the first through-hole conductor is flat, capacitor deviation caused by unevenness in the lower and upper electrodes is suppressed. On the other hand, since the bottom of the second through-hole conductor has a convex shape with a recessed portion, the contact area between the second and third conductor layers is increased, improving their sealing.

[0023] Another aspect of the present invention relates to a method for manufacturing an electronic component, characterized by comprising: a first step of forming a first conductor layer on a substrate, the first conductor layer including a capacitor, the capacitor being composed of a lower electrode and an upper electrode, the upper electrode being stacked on the lower electrode via a dielectric film made of an inorganic insulating material; a second step of forming a first insulating resin layer covering the first conductor layer; a third step of forming a first opening in the first insulating resin layer to expose the first conductor layer by photolithography; a fourth step of forming a second conductor layer including a coil pattern on the first insulating resin layer in a manner connected to the first conductor layer via the first opening; a fifth step of forming a second insulating resin layer covering the second conductor layer; a sixth step of forming a second opening in the second insulating resin layer to expose the second conductor layer by laser processing; a seventh step of forming a recess on the surface of the second conductor layer exposed from the second opening; and an eighth step of forming a third conductor layer including a coil pattern on the second insulating resin layer in a manner connected to the second conductor layer via the second opening.

[0024] According to the present invention, a capacitor requiring high processing precision can be formed in the first conductor layer, and an inductor requiring sufficient conductor thickness can be formed in the second conductor layer. Furthermore, after forming the second opening in the second insulating resin layer by laser processing, a recess is formed on the surface of the second conductor layer exposed from the second opening, thus increasing the contact area between the second and third conductor layers and improving their adhesion. In addition, the second opening can be formed inexpensively, and a non-photosensitive material can be used as the material for the second insulating resin layer. In contrast, forming the first opening by photolithography allows for high processing precision and enables the first opening to be processed into any planar shape.

[0025] In this invention, the first insulating resin layer can be formed by coating in the second step, and the second insulating resin layer can be formed by lamination in the fifth step. This allows for the easy formation of first and second insulating resin layers of different thicknesses.

[0026] [Invention Effects]

[0027] As described above, according to the present invention, in an electronic component that integrates components requiring high processing precision, such as capacitors, and components requiring sufficient conductor thickness, such as inductors, the characteristics required by both components can be satisfied. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view illustrating the structure of electronic component 1 according to one embodiment of the present invention.

[0029] Figure 2 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0030] Figure 3 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0031] Figure 4 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0032] Figure 5 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0033] Figure 6 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0034] Figure 7 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0035] Figure 8 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0036] Figure 9 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0037] Figure 10 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0038] Figure 11 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0039] Figure 12 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0040] Figure 13 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0041] Figure 14 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0042] Figure 15 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0043] Figure 16 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0044] Figure 17 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0045] Figure 18 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0046] Figure 19 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0047] Figure 20 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0048] Figure 21 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0049] Figure 22 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0050] Figure 23 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0051] Figure 24 This is a process diagram used to illustrate the manufacturing method of electronic component 1.

[0052] Figure 25 This is a cross-sectional view used to illustrate the structure of the electronic component 1A in the first modified example.

[0053] Figure 26 This is a cross-sectional view used to illustrate the structure of electronic component 1B in the second modified example. Detailed Implementation

[0054] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 This is a cross-sectional view illustrating the structure of electronic component 1 according to one embodiment of the present invention.

[0056] In this embodiment, electronic component 1 is an LC filter, such as... Figure 1 As shown, the substrate includes a substrate 2 and conductor layers M1 to M4 and insulating resin layers 11 to 14 alternately stacked on the upper surface of the substrate 2. The material of the substrate 2 is not particularly limited; it can be any material that is chemically and thermally stable, generates little stress, and can maintain surface smoothness. Materials such as single-crystal silicon, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO3 single crystal, surface-oxidized silicon, glass, quartz, and ferrite can be used. The surface of the substrate 2 is covered by a planarization layer 3. The planarization layer 3 can be alumina or silicon oxide.

[0057] Conductor layer M1 is the bottommost conductor layer and includes conductor patterns 21 and 22. Conductor patterns 21 and 22 are both composed of a thin seed layer S in contact with the planarization layer 3 and a plating layer P, with a thickness greater than that of the seed layer S, disposed on the seed layer S. The same applies to conductor patterns on other conductor layers; they are composed of a stack of seed layers S and plating layer P. Here, conductor pattern 21 forms the lower electrode of the capacitor, and its upper surface and sides are covered by a dielectric film (capacitor insulating film) 4. At the outer periphery of the electronic component 1, the dielectric film 4 is removed, thereby alleviating stress.

[0058] Conductor pattern 23 is formed on the upper surface of conductor pattern 21 via dielectric film 4. Conductor pattern 23 belongs to conductor layer MM located between conductor layer M1 and conductor layer M2, constituting the upper electrode of the capacitor. Thus, a capacitor is formed, wherein conductor pattern 21 serves as the lower electrode and conductor pattern 23 serves as the upper electrode. Conductor layer M1 and conductor layer MM are covered by insulating resin layer 11 through passivation film 5. In this embodiment, both dielectric film 4 and passivation film 5 are made of inorganic insulating material. The inorganic insulating material constituting dielectric film 4 and inorganic insulating material constituting passivation film 5 can be the same material or different materials. At the outer periphery of electronic component 1, passivation film 5 is removed, thereby relieving stress.

[0059] Conductor layer M2 is a second conductor layer disposed on the surface of insulating resin layer 11, and includes conductor patterns 24 and 25. Conductor pattern 24 is connected to conductor patterns 23 and 22 via through-hole conductors 24a and 24b, respectively. Conductor pattern 25 is connected to conductor pattern 21 via through-hole conductor 25a. Conductor layer M2 is covered by insulating resin layer 12.

[0060] Conductor layer M3 is a third conductor layer disposed on the surface of insulating resin layer 12, and includes conductor patterns 26 and 27. Conductor pattern 26 is connected to conductor pattern 24 via through-hole conductor 26a. Conductor layer M3 is covered by insulating resin layer 13.

[0061] Conductor layer M4 is a fourth conductor layer disposed on the surface of insulating resin layer 13, and includes conductor patterns 28 and 29. Conductor pattern 28 is connected to conductor pattern 26 via through-hole conductor 28a. Conductor layer M4 is covered by insulating resin layer 14.

[0062] Terminal electrodes E1 and E2 are provided on the upper surface of the insulating resin layer 14. Terminal electrodes E1 and E2 are connected to conductor patterns 28 and 29 via through-hole conductors E1a and E2a, respectively. Conductor patterns 22, 24-29 are, for example, part of a coil pattern, thereby integrating capacitors and inductors on the substrate 2.

[0063] In this embodiment, the materials constituting the insulating resin layer 11 are different from those constituting the insulating resin layers 12-14. Specifically, the insulating resin layer 11 is made of a photosensitive material, such as a polyimide resin, which is easy to form into a film using a coating method (e.g., spin coating). In contrast, the insulating resin layers 12-14 are made of materials, such as epoxy resins with added fillers, whose coefficient of thermal expansion is easy to adjust and which can be formed by lamination.

[0064] like Figure 1As shown, when the thicknesses of insulating resin layers 11 to 14 are respectively set to H11 to H14, in this embodiment, H11 < (H12, H13, H14). That is, the thickness of insulating resin layer 11 is thinner than the thickness of any one of insulating resin layers 12 to 14. This means that the total thickness of conductor layers M1 and MM embedded in insulating resin layer 11 is thinner than the thickness of conductor layers M2 to M4 embedded in insulating resin layers 12 to 14. As an example, it can be set as follows: the thickness of conductor layers M2 to M4 is 20 μm, and the thickness of conductor layers M1 and MM is 5 μm. In this way, the conductor thickness of conductor patterns 21 to 23 formed in conductor layers M1 and MM is thin, so the lower electrode and upper electrode constituting the capacitor can be formed with high precision. On the other hand, for conductor patterns 24 to 29 formed in conductor layers M2 to M4, since the conductor thickness can be sufficiently ensured, the Q value of the coil can be improved.

[0065] Furthermore, in this embodiment, the coefficient of thermal expansion of the insulating resin layers 12-14 is smaller than that of the insulating resin layer 11. This prevents peeling at the interface between the thick insulating resin layers 12-14 and the conductor patterns 24-29, and also reduces the likelihood of warping of the electronic component 1 as a whole. The coefficient of thermal expansion of the insulating resin layers 12-14 can be adjusted by the amount and material of the filler added to the insulating resin layers 12-14. Materials with a low coefficient of thermal expansion, such as silicon dioxide, can be used as fillers. While the coefficient of thermal expansion of the insulating resin layer 11 is larger than that of the insulating resin layers 12-14, its thinner thickness prevents strong stress and makes peeling less likely. The coefficient of thermal expansion of the substrate 2 is preferably smaller than that of the insulating resin layers 12-14. Thus, by sandwiching the insulating resin layer 11 with a large coefficient of thermal expansion between the substrate 2 (with a small coefficient of thermal expansion) and the insulating resin layers 12-14, warping of the electronic component 1 as a whole can be suppressed.

[0066] Furthermore, the surfaces of conductor layers M1 and MM are flat, and the bottoms of the through-hole conductors 24a, 24b, and 25a connecting conductor layers M2 and M1 and MM are also flat. This suppresses capacitor deviation caused by the unevenness of the lower and upper electrodes. In contrast, the surfaces of conductor layers M2 to M4 have recesses, and the bottoms of the through-hole conductors 26a, 28a, E1a, and E2a have convex shapes that are recessed into the recesses of conductor layers M2 to M4. As a result, the contact area between the through-hole conductors 26a, 28a, E1a, and E2a and the conductor patterns 24, 26, 28, and 29 connected to them is increased, thus improving the sealing performance.

[0067] In this embodiment, the planar shape of the flat-bottomed through-hole conductors 24a, 24b, and 25a can be set to rectangular, and the planar shape of the through-hole conductors 26a, 28a, E1a, and E2a with convex bottoms can be set to circular. This increases the connection area of ​​the through-hole conductors 24a, 24b, and 25a and prevents peeling around the through-hole conductors 26a, 28a, E1a, and E2a.

[0068] Furthermore, among the through-hole conductors 24a, 24b, and 25a, the through-hole conductor 24a, which is connected to the upper electrode, i.e., conductor pattern 23, is configured to penetrate both the insulating resin layer 11 and the passivation film 5. In contrast, the through-hole conductors 24b and 25a, which are connected to the lower electrode or coil patterns, i.e., conductor patterns 21 and 22, are configured to penetrate both the insulating resin layer 11, the passivation film 5, and the dielectric film 4. That is, the through-hole conductor 24a penetrates one layer of inorganic insulating film, while the through-hole conductors 24b and 25a penetrate two layers of inorganic insulating film. This is because, apart from the area where the conductor pattern 23, which serves as the upper electrode, is formed, the upper surfaces of the conductor patterns 21 and 22 are covered by two layers of inorganic insulating film composed of the dielectric film 4 and the passivation film 5. In this way, by covering the upper surfaces of the conductor patterns 21 and 22 with two layers of inorganic insulating film composed of the dielectric film 4 and the passivation film 5, the conductor patterns 21 and 22 can be protected more effectively.

[0069] Next, the manufacturing method of the electronic component 1 in this embodiment will be described.

[0070] Figures 2 to 24 This is a process diagram illustrating the manufacturing method of the electronic component 1 according to this embodiment. In the manufacturing process of the electronic component 1, multiple electronic components 1 are obtained by using an assembly substrate, but the manufacturing process described below focuses on the manufacturing process of one electronic component 1.

[0071] First, such as Figure 2 As shown, a planarization layer 3 is formed on a substrate (assembly substrate) 2 using a sputtering method or the like, and its surface is smoothed by grinding or CMP mirror finishing. Then, a seed layer S is formed on the surface of the planarization layer 3 using a sputtering method or the like. Next, as... Figure 3 As shown, after spin-coating the resist layer R1 onto the seed layer S, the resist layer R1 is patterned so that the area of ​​the seed layer S to be formed as the conductor layer M1 is exposed. In this state, electroplating is performed using the seed layer S as a power source, such as... Figure 4 As shown, a plating layer P is formed on the seed layer S. The stack of the seed layer S and the plating layer P constitutes the conductor layer M1. Figure 4 In the cross-section shown, conductor patterns 21 and 22 and sacrificial patterns 31 and 32 are included in conductor layer M1. Then, as... Figure 5As shown, remove the resist layer R1, as... Figure 6 As shown, removing the exposed seed layer S on the surface completes the conductor layer M1. The seed layer S can be removed by etching or ion polishing.

[0072] Next, as Figure 7 As shown, a dielectric film 4 is formed on the entire surface, including the upper and side surfaces of the conductor layer M1. The dielectric film 4 can be made of conventional dielectric materials such as silicon nitride (SiNx) or silicon oxide (SiOx), or it can be made of inorganic insulating materials such as known ferroelectric materials. Methods for forming the dielectric film 4 include sputtering, plasma CVD, MOCVD, sol-gel methods, and electron beam evaporation.

[0073] Next, as Figure 8 As shown, a conductor pattern 23 is formed on the upper surface of the conductor pattern 21 via a dielectric film 4 using the same method as that used to form the conductor layer M1. The conductor pattern 23 is also composed of a stack of a seed layer S and a plating layer P. Thus, the conductor layer M1 is completed, forming a capacitor with the conductor pattern 21 as the lower electrode and the conductor pattern 23 as the upper electrode. Next, as... Figure 9 As shown, a passivation film 5 is formed on the entire surface, including the upper and side surfaces of the conductor layers M1 and MM. The passivation film 5 can be made of the same inorganic insulating material as the dielectric film 4.

[0074] Next, as Figure 10 As shown, a resist layer R2 is formed, which does not cover the sacrificial patterns 31 and 32, but covers the conductor patterns 21 and 22. The edge of the resist layer R2 is positioned slightly inside the portion that ultimately becomes the electronic component 1. In this state, the passivation film 5 and the dielectric film 4 are etched, as shown... Figure 11 As shown, the passivation film 5 and dielectric film 4 that ultimately become the outer periphery of the electronic component 1 are removed. In etching the passivation film 5 and dielectric film 4, a highly anisotropic etching method such as ion polishing is preferably used. This removes the portion parallel to the substrate 2, i.e., the surface of the planarization layer 3 and the upper surface covering the sacrificial patterns 31 and 32. On the other hand, the passivation film 5 and dielectric film 4 covering the portion perpendicular to the substrate 2, i.e., the sides covering the sacrificial patterns 31 and 32, remain unremoved.

[0075] Next, as Figure 12As shown, an insulating resin layer 11 is formed covering the conductor layers M1 and MM. The insulating resin layer 11 can be formed by a coating method (e.g., spin coating). This is because the combined film thickness of the conductor layers M1 and MM is, for example, about 10 μm, therefore, the cost is lower compared to forming the insulating resin layer 11 by lamination. As the material for the insulating resin layer 11, a photosensitive polyimide resin can be used. Next, as... Figure 13 As shown, openings 41 to 45 are formed in the insulating resin layer 11 by patterning the insulating resin layer 11. The openings 41 to 45 can be formed by photolithography using a photomask (not shown). As a result, the passivation film 5 covering the upper surface of the conductor patterns 21 to 23 is exposed through the openings 41 to 43, and the sacrificial patterns 31 and 32 are exposed through the openings 44 and 45, respectively.

[0076] Next, as Figure 14 As shown, after forming a resist layer R3 on the insulating resin layer 11, openings 51 to 53 are formed in the resist layer R3. Openings 51 to 53 are respectively positioned overlapping with openings 41 to 43. Thus, the passivation film 5 covering the upper surfaces of the conductor patterns 21 to 23 is exposed through the openings 51 to 53. In this state, the passivation film 5 and dielectric film 4 exposed at openings 51 and 52 are removed by ion polishing or the like, and the passivation film 5 exposed at opening 53 is also removed. Thus, the upper surfaces of the conductor patterns 21 to 23 are exposed at the positions overlapping with openings 51 to 53.

[0077] Then, after removing the resist layer R3, as... Figure 15 As shown, conductor layer M2 is formed on insulating resin layer 11 using the same method as that used to form conductor layer M1. Figure 15 In the cross-section shown, conductor patterns 24 and 25, and sacrificial patterns 33 and 34 are contained within conductor layer M2. Each conductor pattern and sacrificial pattern constituting conductor layer M2 is also composed of a stack of seed layer S and plating layer P. Here, conductor pattern 24 is connected to conductor patterns 22 and 23 via an opening in insulating resin layer 11, and conductor pattern 25 is connected to conductor pattern 21 via an opening in insulating resin layer 11. The portions of conductor patterns 24 and 25 located within the openings in insulating resin layer 11 constitute through-hole conductors 24a, 24b, and 25a. Furthermore, sacrificial patterns 33 and 34 are connected to sacrificial patterns 31 and 32 respectively via openings in insulating resin layer 11.

[0078] Next, as Figure 16As shown, an insulating resin layer 12 is formed covering the conductor layer M2. The insulating resin layer 12 can be formed by lamination. This is because the thickness of the conductor layer M2 is, for example, about 20 μm, so it can be formed at a lower cost compared to forming the insulating resin layer 12 by coating. As the material for the insulating resin layer 12, a non-photosensitive epoxy resin can be used. A filler for adjusting the coefficient of thermal expansion is added to the insulating resin layer 12, thereby giving it a lower coefficient of thermal expansion than the insulating resin layer 11.

[0079] Next, as Figure 17 As shown, openings 54 to 56 are formed in the insulating resin layer 12. The formation of openings 54 to 56 can be performed by laser processing. Thus, the conductor pattern 24 is exposed through opening 54, and the sacrificial patterns 33 and 34 are exposed through openings 55 and 56, respectively. Then, a decontamination treatment using permanganate or the like is performed to remove residue from the openings 54 to 56. At this time, the surface of the conductor pattern 24 exposed in the opening 54 is also etched to form a recess 24R. The same recesses are also formed on the surfaces of the sacrificial patterns 33 and 34. The shape of the recess 24R can be adjusted according to the decontamination treatment time, the type of solution used, etc. Furthermore, in addition to the decontamination treatment, an etching process can be added to form the recess 24R on the conductor pattern 24.

[0080] Next, as Figure 18 As shown, the conductor layer M3 is formed on the insulating resin layer 12 using the same method as that used to form the conductor layer M1. Figure 18 In the cross-section shown, conductor patterns 26 and 27 and sacrificial patterns 35 and 36 are included in conductor layer M3. Each conductor pattern and sacrificial pattern constituting conductor layer M3 is also composed of a stack of seed layer S and plating layer P. Here, conductor pattern 26 is connected to conductor pattern 24 via an opening provided in insulating resin layer 12. The portion of conductor pattern 26 located within the opening in insulating resin layer 12 constitutes a through-hole conductor 26a, the bottom of which has a convex shape recessed into recess 24R. Furthermore, sacrificial patterns 35 and 36 are respectively connected to sacrificial patterns 33 and 34 via openings provided in insulating resin layer 12.

[0081] Then, by repeating the same process, such as Figure 19 As shown, an insulating resin layer 13, a conductor layer M4, and an insulating resin layer 14 are formed sequentially. Insulating resin layers 13 and 14 can also be formed by lamination. Figure 19In the cross-section shown, conductor patterns 28 and 29 and sacrificial patterns 37 and 38 are included in conductor layer M4. Here, conductor pattern 28 is connected to conductor pattern 26 through an opening provided in insulating resin layer 13, and sacrificial patterns 37 and 38 are connected to sacrificial patterns 35 and 36 respectively through openings provided in insulating resin layer 13. The portion of conductor pattern 28 located within the opening in insulating resin layer 13 constitutes a through-hole conductor 28a, and its bottom has a convex shape such that it is recessed into the recess provided in conductor pattern 26.

[0082] Next, as Figure 20 As shown, openings 61 and 62 are formed by laser processing of the insulating resin layer 14. This exposes the upper surfaces of the conductor patterns 28 and 29 through the openings 61 and 62, respectively. Afterwards, a decontamination process is performed to remove residue from the openings 61 and 62, and recesses 28R and 29R are formed on the surfaces of the conductor patterns 28 and 29. Then, as... Figure 21 As shown, terminal electrodes E1 and E2 are formed on the insulating resin layer 14. Terminal electrode E1 is connected to conductor pattern 28 through an opening in the insulating resin layer 14, and terminal electrode E2 is connected to conductor pattern 29 through an opening in the insulating resin layer 14. The portions of terminal electrodes E1 and E2 located within the openings in the insulating resin layer 14 respectively constitute through-hole conductors E1a and E2a, and their bottoms have a convex shape by incorporating recesses 28R and 29R.

[0083] Next, as Figure 22 As shown, openings 63 and 64 are formed by patterning the insulating resin layer 14. Thus, the upper surfaces of the sacrificial patterns 37 and 38 are exposed through openings 63 and 64, respectively. Then, as... Figure 23 As shown, after forming a resist layer R4 on the entire surface of the insulating resin layer 14 containing terminal electrodes E1 and E2, openings 73 and 74 are formed in the resist layer R4 to expose the sacrificial patterns 37 and 38. In this state, etching using an acid or the like is performed... Figure 24 As shown, sacrificial patterns 31 to 38 are removed. Thus, space A is formed in the region where sacrificial patterns 31 to 38 have been removed.

[0084] Then, after removing the resist layer R4, the substrate 2 is cut along space A, thereby monolithically forming the electronic component 1. Thus, the electronic component 1 of this embodiment is completed.

[0085] As explained above, in the electronic component 1 of this embodiment, the material and thickness of the bottom insulating resin layer 11 are different from those of the insulating resin layers 12-14 located above it. Specifically, the insulating resin layer 11 is thinner than the insulating resin layers 12-14, and the coefficient of thermal expansion of the insulating resin layers 12-14 is smaller than that of the insulating resin layer 11. Therefore, capacitors requiring high processing precision can be embedded in the thin insulating resin layer 11, while inductors requiring sufficient conductor thickness can be embedded in the thick insulating resin layers 12-14. Furthermore, since the insulating resin layers 12-14 have a lower coefficient of thermal expansion, warping and peeling can be suppressed.

[0086] Furthermore, in the electronic component 1 of this embodiment, since the surfaces of conductor layers M1 and MM are flat, capacitor deviation caused by the unevenness of the lower and upper electrodes can be suppressed. On the other hand, the surfaces of conductor layers M2 to M4 have recesses, and the bottoms of through-hole conductors 26a, 28a, E1a, and E2a have convex shapes that are recessed into the recesses of conductor layers M2 to M4. As a result, the contact area of ​​through-hole conductors 26a, 28a, E1a, and E2a and the conductor patterns 24, 26, 28, and 29 connected to them is increased, thus improving the tightness of the fit.

[0087] Furthermore, among the through-hole conductors 24a, 24b, and 25a, the through-hole conductor 24a connected to the upper electrode, i.e., conductor pattern 23, is configured to penetrate the insulating resin layer 11 and the passivation film 5. In contrast, the through-hole conductors 25a and 24b connected to the lower electrode or coil patterns, i.e., conductor patterns 21 and 22, are configured to penetrate the insulating resin layer 11, the passivation film 5, and the dielectric film 4. This allows for more effective protection of the conductor patterns 21 and 22.

[0088] Figure 25 This is a cross-sectional view used to illustrate the structure of the electronic component 1A in the first modified example.

[0089] In the electronic component 1A of the first modification, the difference from the electronic component 1 of the above embodiment is that the insulating resin layer 11 is partially removed in the area that does not overlap with the coil pattern, and an insulating resin layer 12 is embedded in the portion where the insulating resin layer 11 has been removed. The embedded insulating resin layer 12 is in contact with the planarization layer 3 or the passivation film 5, and its thickness locally increases in this portion. Other basic structures are the same as those of the electronic component 1 of the above embodiment; therefore, the same reference numerals are used for the same elements, and repeated descriptions are omitted. According to the electronic component 1A of the first modification, since the volume of the insulating resin layer 12, which has a small coefficient of thermal expansion, is further increased, it is more difficult for the overall warping of the electronic component 1 to occur.

[0090] Figure 26 This is a cross-sectional view used to illustrate the structure of electronic component 1B in the second modified example.

[0091] In the second variation of electronic component 1B, the difference from the first variation of electronic component 1A is that the dielectric film 4 and the passivation film 5 are removed in the removed portion of the insulating resin layer 11. The embedded insulating resin layer 12 is in contact with the planarization layer 3 or the conductor pattern 21. Other basic structures are the same as those in the first variation of electronic component 1A; therefore, the same reference numerals are used for the same elements, and repeated descriptions are omitted. According to the second variation of electronic component 1B, since the volume of the insulating resin layer 12 with a small coefficient of thermal expansion is further increased, it is more difficult for the overall warping of electronic component 1 to occur. Furthermore, by partially removing the dielectric film 4 and the passivation film 5, the stress generated by the dielectric film 4 and the passivation film 5 can also be mitigated.

[0092] The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments. Various modifications can be made without departing from the spirit of the present invention, and these modifications are also included within the scope of the present invention.

[0093] For example, in the above embodiments, the application of the present invention to an LC filter was described as an example, but the electronic components that are the subject of the present invention are not limited to LC filters, and can also be applied to other types of electronic components.

[0094] [Symbol Explanation]

[0095] 1, 1A, 1B Electronic Components

[0096] 2 substrates

[0097] 3 Planarization layer

[0098] 4. Dielectric film

[0099] 5. Passivation film

[0100] 11-14 Insulating resin layers

[0101] Conductor patterns 21-29

[0102] 24a, 24b, 25a, 26a, 28a, E1a, E2a through-hole conductors

[0103] 24R, 28R, 29R recess

[0104] Sacrifice patterns 31-38

[0105] 41–45, 51–56, 61–64, 73, 74 openings

[0106] Space A

[0107] E1 and E2 terminal electrodes

[0108] M1~M4, MM conductor layer

[0109] P coating

[0110] R1~R4 resist layers

[0111] S-seed layer.

Claims

1. An electronic component, characterized by comprising: a substrate; and a plurality of conductor layers and a plurality of insulating resin layers alternately laminated on the substrate, the plurality of insulating resin layers including a first insulating resin layer located at a lowermost layer and a plurality of second insulating resin layers located on the first insulating resin layer, the plurality of conductor layers including a first conductor layer embedded in the first insulating resin layer and a plurality of second conductor layers embedded in the plurality of second insulating resin layers, respectively, the first conductor layer including a capacitor composed of a lower electrode and an upper electrode laminated on the lower electrode via a dielectric film composed of an inorganic insulating material, the plurality of second conductor layers including a coil pattern, the first insulating resin layer being thinner than the second insulating resin layer in thickness, and the second insulating resin layer having a lower coefficient of thermal expansion than the first insulating resin layer.

2. The electronic component according to claim 1, characterized in that the first insulating resin layer is composed of a polyimide-based resin.

3. The electronic component according to claim 1, characterized in that the second insulating resin layer is composed of a material in which a filler is added to an epoxy-based resin.

4. The electronic component according to claim 1, characterized in that each of the plurality of second conductor layers is thicker than a total thickness of the lower electrode and the upper electrode.

5. The electronic component according to claim 1, characterized in that a first via conductor, which is provided so as to penetrate the first insulating resin layer and connects the first conductor layer and the second conductor layer, has a rectangular planar shape, and a second via conductor, which is provided so as to penetrate the second insulating resin layer and connects different second conductor layers to each other, has a circular planar shape.

6. The electronic component according to claim 1, characterized in that the first insulating resin layer is partially removed, and an insulating resin layer of the plurality of second insulating resin layers, which is in contact with the first insulating resin layer, is embedded in a portion in which the first insulating resin layer is removed.

7. The electronic component according to any one of claims 1 to 4 and 6, characterized in that the second conductor layer has a first via conductor, which is provided so as to penetrate the first insulating resin layer and connects a conductor layer located at a lowermost layer of the plurality of second conductor layers and the first conductor layer, and a second via conductor, which is provided so as to penetrate the second insulating resin layer and connects the plurality of second conductor layers to each other, a bottom portion of the first via conductor is flat, a surface of the plurality of second conductor layers has a recessed portion at a portion connected to the second via conductor, and a bottom portion of the second via conductor has a convex portion shape in a manner of sinking into the recessed portion.

8. The electronic component according to claim 7, characterized in that the first via conductor has a rectangular planar shape, and the second via conductor has a circular planar shape.

9. The electronic component according to claim 7, characterized in that ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The plurality of second conductor layers are thicker than a total thickness of the lower electrode and the upper electrode.

10. A method for manufacturing an electronic component, characterized by comprising: a first step of forming a first conductor layer on a substrate, the first conductor layer including a capacitor composed of a lower electrode and an upper electrode, the upper electrode being stacked on the lower electrode via a dielectric film composed of an inorganic insulating material; a second step of forming a first insulating resin layer covering the first conductor layer; and a third step of alternately forming a second conductor layer including a coil pattern and a second insulating resin layer on the first insulating resin layer, the second insulating resin layer being thicker than the first insulating resin layer and having a thermal expansion coefficient smaller than that of the first insulating resin layer.

11. The method for manufacturing an electronic component according to claim 10, characterized in that: in the second step, the first insulating resin layer is formed by a coating method, in the third step, the second insulating resin layer is formed by a lamination method.

12. The method for manufacturing an electronic component according to claim 10 or 11, characterized by further comprising: a fourth step of exposing the first conductor layer by forming an opening portion in the first insulating resin layer; and a fifth step of exposing the second conductor layer by forming an opening portion in the second insulating resin layer, the fourth step is performed by a photolithography method, the fifth step is performed by a laser processing method. ​ ​ ​

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