Implementation of multi-type trigger system in waveform acquisition and recording based on FPGA

Abstract

The present invention discloses a multi-type trigger system for waveform acquisition and recording based on an FPGA. The system comprises a storage recorder, a digital trigger module, and a trigger output module. The storage recorder is used to acquire analog signals and convert them into digital signals for input into the digital trigger module. The digital trigger module comprises a level filter detection module, a trigger event processing module, and a channel selection module, which is used to select whether to turn any of eight trigger channels on or off and select any preset trigger type. The trigger output module is used to perform an OR or AND logical combination of the trigger outputs of the channels set to on among the eight channels, and then generate a final trigger output. The system can set different trigger modes for various signals to be acquired, thereby extracting different characteristics of the signals, thereby more accurately capturing, storing, and recording the signals.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-type triggering, and in particular to a multi-type triggering system for waveform acquisition and recording based on FPGA. Background Art

[0002] Test and measurement instruments play a crucial role in industrial production, and electronic measuring instruments are increasingly widely used. Digital oscilloscopes are currently the most widely used electronic measuring instruments, serving as the "third eye" for electronic test engineers. However, with the rapid development of information technology, the variety of industrial parameters that need to be measured is increasing, and the signals being measured are becoming increasingly complex and diverse. Oscilloscopes are unable to meet these demands, leading to the emergence of storage recorders.

[0003] Storage recorders utilize multiple acquisition channels to collect, calculate, and store various signals through plug-in and plug-out acquisition submodules. These recorders are suitable for industrial applications requiring simultaneous acquisition of multiple signals and long-term recording and storage, such as aircraft status monitoring, fault analysis, and environmental monitoring. Storage recorders need to record waveform data with various characteristics or abnormal waveform data, making a trigger system with extensive triggering capabilities particularly important. The trigger system's intuitive function is to display or store waveforms based on user-defined conditions on the instrument panel. Essentially, it captures and extracts waveforms of interest. Therefore, the trigger system's accuracy, flexibility, and scalability determine the storage recorder's ability to store and record a variety of signals with diverse characteristics.

[0004] However, the existing trigger system cannot set different trigger modes for various signals that need to be collected, and thus cannot extract different features of the signals. Therefore, it is impossible to capture and store the signals more accurately. Therefore, a trigger system suitable for storage recorders is urgently needed. Summary of the Invention

[0005] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0006] Therefore, the purpose of the present invention is to propose a multi-type trigger system for waveform acquisition and recording based on FPGA.

[0007] To achieve the above-mentioned purpose, an embodiment of the present invention proposes a multi-type trigger system for waveform acquisition and recording based on FPGA, including: a storage recorder, a digital trigger module and a trigger output module, wherein the storage recorder is used to acquire analog signals and convert the analog signals into digital signals to enter the digital trigger module; the digital trigger module includes a level filter detection module, a trigger event processing module and a channel selection module, which is used to open or close any one of the eight trigger channels and select any preset trigger type; the trigger output module is used to perform a logical combination of or or and on the trigger outputs of the channels set to on among the eight channels to perform the final trigger output.

[0008] The embodiment of the present invention implements a multi-type trigger system for waveform acquisition and recording based on FPGA, which is applied to the trigger system of a storage recorder. The system can capture multiple features of the input waveform and allow the user to select one or more trigger sources for triggering, thereby enriching the trigger function of the oscilloscope and improving the waveform capture capability of the storage recorder. In terms of code writing, common functions are extracted from the functions of various triggers, thereby greatly reducing the complexity of the state machines of various triggers, reducing the number of state machine state transitions, and improving the reusability of the code.

[0009] In addition, the multi-type trigger system for waveform acquisition and recording based on FPGA according to the above embodiment of the present invention may also have the following additional technical features:

[0010] Furthermore, in one embodiment of the present invention, the level filtering detection module is used to perform level detection on the digital signal and output a pulse, wherein a threshold Vth is set. When the waveform crosses the threshold upward, a pulse cmp_up_pulse is output; when the waveform crosses the threshold downward, another pulse cmp_up_pulse is output. At the same time, a delay filter is used for filtering. When it is detected that the signal crosses the threshold, a delay judgment is started, and the delay value is time_dly. If the voltage threshold after a delay period is lower or higher than the set threshold, the signal is considered to be relatively stable and meets the conditions for pulse output.

[0011] Furthermore, in one embodiment of the present invention, the trigger event processing module is used to process the trigger output module, wherein the trigger event number events and the module enable signal events_en are set, and a counter is used to count the number of trigger input signal trigger_in triggers. If it is lower than the set number of trigger events, no trigger is generated. If the set number of trigger events is reached, a trigger output signal trigger_out is generated.

[0012] Furthermore, in one embodiment of the present invention, the trigger event processing module is only effective when each channel selects the or trigger logic combination mode, and is invalid when the and mode is selected.

[0013] Furthermore, in one embodiment of the present invention, the preset trigger types include level triggering, window triggering, voltage drop triggering, periodic triggering, and pulse triggering.

[0014] Furthermore, in one embodiment of the present invention, when the level trigger is selected, a level threshold and a delay parameter of a delay filter are set, the digital signal is input and passes through the level filter detection module to output two pulse signals, and the control word that crosses the threshold upward or downward determines which of the two signals serves as the trigger input for level detection, and the first signal is named the start_pulse signal, and the other signal is named the stop_pulse signal;

[0015] The state machine of the level detection is in the idle state. After encountering the start_pulse pulse, the state machine enters the HOLD state. During the HOLD state, the signal trigger_out_r0 is always in the high level state. When encountering the stop_pulse pulse, the level detection trigger state machine exits the HOLD state and returns to the IDLE state, and sets the signal trigger_out_r0 to 0.

[0016] When the or mode is selected, the rising edge of the signal trigger_out_r0 is detected, and the output signal trigger_out_or is sent to the trigger event processing module. After detection by the trigger event processing module, the trigger signal of the final level trigger module is output. When the and mode is selected, the output signal trigger_out_and is equal to trigger_out_r0, and trigger_out_and is also input into the trigger event processing module, but no processing is done.

[0017] Furthermore, in one embodiment of the present invention, when the window trigger is selected, the input digital signal first passes through the level filter detection module. After the digital signal passes through the level filter detection module that detects the high level, two pulse signals are output, namely, an output pulse signal th_cmp_up_pulse that crosses the high level threshold upward and an output pulse signal th_cmp_down_pulse that crosses the low level threshold downward. When the user selects internal window trigger, th_cmp_down_pulse and tl_cmp_up_pulse serve as start_pulse signals, and th_cmp_up_pulse and tl_cmp_down_pulse serve as stop_pulse signals; when the user selects external window trigger signal, the signal sources of start_pulse and stop_pulse are opposite;

[0018] The state machine is initially in the IDLE state. When the start_pulse signal is detected, it means that the input signal enters the set level range. At this time, the state of the state machine enters the HOLD state, and the signal trigger_out_r0 is always set to 1 in the HOLD state. When the state machine is in the HOLD state, when the stop_pulse signal is detected, it returns to the IDLE state and sets trigger_out_r0 to 0.

[0019] When the same level is triggered, trigger_out_r0 is processed by the trigger event processing module.

[0020] Furthermore, in one embodiment of the present invention, when the voltage drop trigger is selected, the stability of the low-frequency power supply voltage is detected. When the power supply voltage is lower than a certain level, a trigger is generated. When the voltage peak value continues to be lower than the set level for 1 / 2 cycle, the voltage drop trigger condition is met. The voltage drop trigger has two thresholds for triggering. The thresholds are set by the RMS effective value and the level threshold Vth to obtain the high and low level thresholds, and the outputs th_cmp_up_pulse and th_cmp_down_pulse compared with the high level threshold are output, and the outputs tl_cmp_up_pulse and tl_cmp_down_pulse compared with the low level threshold are output;

[0021] The state machine triggered by voltage drop is in IDLE state when it is not lower than the low level threshold;

[0022] When the digital signal crosses the low level threshold, it cannot be determined that the level has reached the lowest value, so triggering is not selected here;

[0023] When the digital signal crosses the low-level threshold upward, the state of the state machine changes and enters the CNT state. A counter cnt is used to count the input waveform to count the time the waveform is lower than the set level state. When the counter is lower than 1 / 2 cycle half_period_Max and the signal crosses the high-level threshold upward or crosses the low-level threshold downward, it means that the trigger condition is not met. At this time, the state machine returns to the IDLE state and re-detects; when the counter cnt is equal to half_period_Max, it enters the HOLD state, and the signal trigger_out_r0 is in a high-level state. When a pulse signal crossing the high-level threshold upward or crossing the low-level threshold downward is detected, the state machine returns from the HOLD state to the IDLE state machine, and clears cnt and trigger_out_r0 at the same time;

[0024] When the same level is triggered, trigger_out_r0 is processed by the trigger event processing module.

[0025] Furthermore, in one embodiment of the present invention, when the periodic trigger is selected, the periodic trigger condition is met when the time between two rising edges or falling edges of the signal is within the set period range or outside the period range, wherein, when the out-of-period trigger is selected, a trigger is generated if the signal period is less than the set period lower limit or greater than the set period upper limit; when the in-period trigger is selected, a trigger is generated if the signal period is within the set period lower limit or less than the period upper limit.

[0026] Furthermore, in one embodiment of the present invention, when the pulse width trigger is selected, if the pulse width is shorter than the set pulse width, the pulse trigger condition is met.

[0027] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic diagram of the structure of a multi-type trigger system for waveform acquisition and recording based on FPGA according to an embodiment of the present invention;

[0030] Figure 2 Schematic diagram of level comparison and output of two signals according to an embodiment of the present invention;

[0031] Figure 3 is a schematic diagram of delay filtering according to an embodiment of the present invention;

[0032] Figure 4 1 is a schematic diagram of a signal of a level filtering detection module according to an embodiment of the present invention;

[0033] Figure 5 This is a signal diagram of a trigger event processing module according to an embodiment of the present invention;

[0034] Figure 6 1 is a schematic diagram of a waveform detection process according to an embodiment of the present invention;

[0035] Figure 7 1 is a schematic diagram of a level-triggered and window-triggered state machine according to an embodiment of the present invention;

[0036] Figure 8 Schematic diagram of a voltage drop trigger state machine according to an embodiment of the present invention;

[0037] Figure 9 Schematic diagram of an out-of-cycle trigger state machine according to an embodiment of the present invention;

[0038] Figure 10 Schematic diagram of a trigger state machine within a cycle according to an embodiment of the present invention;

[0039] Figure 11 1 is a schematic diagram of a pulse trigger state machine according to an embodiment of the present invention;

[0040] Figure 12 1 is a schematic diagram of level triggering according to a specific embodiment of the present invention;

[0041] Figure 13 This is a schematic diagram of in-window triggering according to a specific embodiment of the present invention;

[0042] Figure 14 This is a schematic diagram of out-of-window triggering according to a specific embodiment of the present invention;

[0043] Figure 15 This is a schematic diagram of a voltage drop trigger according to a specific embodiment of the present invention;

[0044] Figure 16 This is a schematic diagram of an extra-periodic trigger according to a specific embodiment of the present invention;

[0045] Figure 17 It is a schematic diagram of pulse width triggering according to a specific embodiment of the present invention;

[0046] Figure 18 This is a schematic diagram of the output of the multi-channel trigger and / or mode according to a specific embodiment of the present invention (taking dual channels as an example). DETAILED DESCRIPTION

[0047] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0048] The following describes a multi-type trigger system for waveform acquisition and recording based on FPGA according to an embodiment of the present invention with reference to the accompanying drawings.

[0049] Figure 1 The present invention is a schematic diagram of a multi-type trigger system for waveform acquisition and recording based on FPGA according to an embodiment of the present invention.

[0050] like Figure 1 As shown, the system 10 includes: a storage recorder 100 , a digital trigger module 200 and a trigger output module 300 .

[0051] The storage recorder 100 is used to collect analog signals and convert them into digital signals for input into the digital trigger module. The digital trigger module 200 includes a level filter detection module 201, a trigger event processing module 202, and a channel selection module 203. These modules are used to enable or disable any of the eight trigger channels and select any preset trigger type. The trigger output module 300 is used to perform an OR or AND logical combination of the trigger outputs of the eight channels set to ON, generating the final trigger output.

[0052] Furthermore, the storage recorder 100 in the embodiment of the present invention uses its ADC module to collect analog signals, converts the analog signals into digital signals, and then enters the digital trigger system.

[0053] Furthermore, there are a total of 8 trigger channels in the digital trigger module 200 in the embodiment of the present invention, and the switches of the 8 channels are turned on / off by the channel selection module; each channel can select multiple trigger types. It should be noted that the logic code of each trigger type is implemented, and each trigger type has multiple different configurations. The trigger types include level trigger, window trigger, voltage drop trigger, periodic trigger, and pulse trigger.

[0054] Furthermore, a level trigger is triggered when a signal crosses a set level threshold. Items that require settings include: level threshold, rising or falling threshold crossing, trigger event settings, and trigger filter settings. A window trigger is triggered when a signal enters or leaves a certain range. Items that require settings include: triggering within or outside the window, window trigger upper limit, window trigger lower limit, and trigger event settings. A voltage drop trigger is triggered when a signal remains below a set level for more than 1 / 2 cycle. Items that require settings include: voltage drop level threshold, input signal frequency setting, effective value setting, and trigger event settings. A period trigger is divided into period trigger and period trigger. A trigger is generated when the input signal is within or outside the set period range. Items that require settings include: level threshold, rising or falling threshold crossing selection, cycle lower limit threshold, cycle upper limit threshold, trigger event count setting, and trigger filter settings. A pulse width trigger is triggered when the pulse width is greater than or less than a certain width threshold. Items that require settings include: level threshold setting, rising or falling threshold crossing selection, trigger event count setting, and pulse width threshold setting.

[0055] Furthermore, the level filter detection module 201 and the trigger event processing module 202 can be extracted from the above-mentioned trigger modes to enhance the reusability of the code, wherein:

[0056] The level filter detection module 201 is used to perform the most basic level detection on the input signal and output a pulse. Figure 2 As shown, set the threshold Vth. When the waveform passes through the threshold upward, output a pulse cmp_up_pulse. When the waveform passes through the threshold downward, output another pulse cmp_up_pulse. At the same time, because the input signal may contain certain interference signals, it is necessary to perform certain filtering processing. Figure 3 As shown, the embodiment of the present invention adopts a time delay filter to perform filtering. Figure 4 As shown, when it is detected that the signal crosses the threshold, the delay judgment begins, and the delay value is time_dly. If the voltage threshold after a period of delay is lower or higher than the set threshold, it is considered that the signal is relatively stable and meets the conditions for pulse output.

[0057] The trigger event processing module 202 is a module for processing trigger output. Figure 5As shown, the trigger event count (events) and module enable signal (events_en) are set. A counter is used to count the number of trigger events on the trigger input signal (trigger_in). If the number of trigger events is less than the set number, no trigger is generated. If the number of trigger events reaches the set number, a trigger output signal (trigger_out) is generated. Trigger event processing module 202 is only effective when each channel selects the OR trigger logic combination mode; it is invalid when the AND mode is selected.

[0058] It should be noted that if Figure 6 As shown in the figure, for different trigger modes, the trigger signal is output after detection and processing by three modules. The first two modules are multiplexed modules, while the second module is a state machine specific to each trigger mode. The choice of which state machine to trigger the signal depends on the trigger mode selected and the configuration parameters.

[0059] Specifically, if Figure 7 As shown in the figure, when level triggering is selected, the level threshold and delay filter parameters are set. The input signal passes through the level filter detection module, outputting two pulse signals. The control word, which determines whether the signal crosses the threshold upward or downward, determines which of the two signals serves as the trigger input for level detection. This signal is named the start_pulse signal, and the other is named the stop_pulse signal. The level detection state machine is in the idle state. After encountering the start_pulse pulse, the state machine enters the hold state. During this hold state, the trigger_out_r0 signal remains high. Upon encountering the stop_pulse pulse, the level detection trigger state machine exits the hold state, returns to the idle state, and sets the trigger_out_r0 signal to 0. The control word, which selects either the or or and combinational logic, determines which signal enters the trigger event detection module. When the or mode is selected, the trigger_out_r0 signal is detected for a rising edge and outputs the trigger_out_or signal to the trigger event processing module. After detection by the trigger event processing module, the final trigger signal for the level trigger module is output. When the and mode is selected, the output signal trigger_out_and is equal to trigger_out_r0. In order to maintain consistency in the code, trigger_out_and is also input into the trigger event processing module, but no processing is performed.

[0060] Specifically, if Figure 7As shown, when window triggering is selected, the input signal first passes through the level filter detection module. Window triggering involves two level thresholds: a high level threshold and a low level threshold. After the input signal passes through the level filter detection module for detecting the high level, it outputs two pulse signals: an output pulse signal th_cmp_up_pulse that crosses the high level threshold upward, and an output pulse signal th_cmp_down_pulse that crosses the low level threshold downward. After the input signal passes through the level filter detection module for detecting the low level, it outputs two pulse signals: an output pulse signal tl_cmp_up_pulse that crosses the low level threshold upward, and an output pulse signal tl_cmp_down_pulse that crosses the low level threshold downward. The four signals, th_cmp_up_pulse, th_cmp_down_pulse, tl_cmp_up_pulse, and tl_cmp_down_pulse, function differently depending on whether the user selects internal or external triggering. When internal triggering is selected, th_cmp_down_pulse and tl_cmp_up_pulse serve as the start_pulse signals, while th_cmp_up_pulse and tl_cmp_down_pulse serve as the stop_pulse signals. When external triggering is selected, the start_pulse and stop_pulse signal sources are reversed. The state machine is initially in the IDLE state. Upon detecting the start_pulse signal, indicating that the input signal has entered the set level range (inside or outside the window), the state machine enters the HOLD state, and the trigger_out_r0 signal remains set to 1 in the HOLD state. If the stop_pulse signal is detected while the state machine is in the HOLD state, the state machine returns to the IDLE state, and trigger_out_r0 is set to 0. Subsequent processing of trigger_out_r0 needs to go through the trigger event processing module, which is the same trigger event processing module used when triggering at the same level.

[0061] Specifically, if Figure 8 As shown, the voltage drop trigger is primarily used to detect the stability of low-frequency power supply voltages. It triggers when the power supply voltage drops below a certain level. When the voltage drop trigger is selected, the voltage drop trigger condition is met when the voltage peak remains below the set level for 1 / 2 cycle. The voltage drop trigger has two thresholds for triggering, set by the RMS value and the level threshold Vth. The high and low thresholds are:

[0062] Vth_high=RMS+Vth;

[0063] Vth_low=RMS–Vth;

[0064] Based on the delay filter parameter settings and the high and low thresholds, four pulses similar to those used for window triggering are output: th_cmp_up_pulse and th_cmp_down_pulse, which are compared with the high threshold, and tl_cmp_up_pulse and tl_cmp_down_pulse, which are compared with the low threshold. The state machine for voltage drop triggering is in the IDLE state unless the input signal falls below the low threshold. When the input signal crosses the low threshold, it cannot be guaranteed that the voltage has reached its minimum, so triggering is not performed at this point. When the input signal crosses the low threshold, the state machine changes state to the CNT state. In the CNT state, a counter, cnt, is used to count the time the input waveform remains below the set voltage level. When the counter is less than half_period_Max and the signal crosses the high threshold or the low threshold, the trigger condition is not met. The state machine then returns to the IDLE state and retests. When the counter cnt reaches half_period_Max, it enters the HOLD state. In the HOLD state, the trigger_out_r0 signal is high. When a pulse signal crossing the high threshold or the low threshold is detected, the state machine returns from the HOLD state to the IDLE state, simultaneously clearing cnt and trigger_out_r0. The control word, which selects either or, depending on the combinational logic, determines which signal enters the trigger event detection module. Subsequent processing of trigger_out_r0 requires the trigger event processing module, the same as that used for level triggering.

[0065] Specifically, if Figure 9 As shown, when periodic triggering is selected, the periodic trigger condition is met when the time between the rising or falling edges of the signal is within or outside the set period range. Periodic triggering requires only a single level threshold for level filtering detection. After the input signal passes through the level filtering module, it outputs a pulse signal (cmp_up_pulse) that crosses the level threshold upward, and a pulse signal (cmp_down_pulse) that crosses the level threshold downward. If the user sets the pulse that crosses the threshold upward as the start_pulse, the pulse that crosses the threshold downward becomes the stop_pulse, and vice versa. Triggering outside the period and triggering within the period are two separate state machines.

[0066] When an out-of-cycle trigger is selected, a trigger is generated if the signal period is less than the set lower limit or greater than the set upper limit. When the out-of-cycle trigger state machine is in the IDLE state and detects a high start_pulse, the state machine transitions to the CNT state. In the CNT state, the signal time is counted and compared against the set upper and lower limit periods. In the CNT state, a lower limit of less than five times the sampling period is considered invalid; in this case, the lower limit is ignored. A lower limit of five times or more is considered valid. When the lower limit is less than five times the sampling period, if the counter cnt is less than the set upper limit and a start_pulse is detected, the state machine returns to the IDLE state and no trigger is generated. If the counter is equal to the set upper limit and no start_pulse is detected, the state machine transitions to the HOLD_H state. When the lower limit of the period is set to 5 times or greater than the sampling period, if the counter cnt is less than the lower limit and detects the start_pulse, the state machine transitions to the HOLD_L state. If cnt is greater than the lower limit but less than the upper limit and detects the start_pulse, the state machine returns to the IDLE state and no trigger is generated. If cnt is equal to the upper limit and no start_pulse is detected, the state machine transitions to the HOLD_H state. In the HOLD_L state, the counter cnt continues counting the input signal and continuously pulls the trigger_out_r0 signal high. When the counter reaches the lower limit of the period, the state machine returns to the IDLE state. In the HOLD_H state, the counter cnt stops counting and the trigger_out_r0 signal is continuously pulled high. When the start_pulse signal is detected, the state machine returns to the IDLE state. The control word selected by the combinational logic, either or, determines which signal enters the trigger event detection module. When the OR mode is selected, the rising edge of the trigger_out_r0 signal is detected, and the output signal trigger_out_or is connected to the trigger event processing module. After detection by the trigger event processing module, the final trigger signal of the level trigger module is output. When the AND mode is selected, the output signal trigger_out_and is equal to trigger_out_r0, and trigger_out_and is connected to the trigger event processing module. After the above processing, the final output is trigger_out.

[0067] like Figure 10As shown in the figure, when intra-cycle triggering is selected, a trigger is generated if the signal period is within the set period lower limit or less than the period upper limit. When the state machine for intra-cycle triggering is in the IDLE state, if the start_pulse signal is detected as high, the state machine jumps to the CNT state. In the CNT state, if the user-set period lower limit is less than 5 times, if the counter cnt is less than the period upper limit and the start_pulse signal is detected, the state machine jumps to the HOLD state. If the counter cnt reaches the period upper limit and no start_pulse signal is detected, the state machine jumps to the IDLE state. If the user-set period lower limit is 5 times or more, if the counter cnt is less than the period lower limit and the start_pulse signal is detected, the state machine returns to the IDLE state. If cnt is greater than the period lower limit but less than the period upper limit and the start_pulse signal is detected, the state machine jumps to the HOLD state. If the counter cnt is equal to the period upper limit and no start_pulse signal is detected, the state machine returns to the IDLE state. In the HOLD state, the counter cnt continues counting, while the signal trigger_out_r0 is pulled high. When the counter cnt reaches the upper limit of the cycle, the state machine returns to the IDLE state. The signal trigger_out_r0 is also processed and connected to the trigger event processing module, and finally the out-of-cycle trigger signal trigger_out is output.

[0068] Specifically, if Figure 11As shown in the figure, when pulse width triggering is selected, if the pulse width is shorter than the set pulse width, the pulse trigger condition is met. Pulse triggering requires only one level threshold for level filtering detection. After the input signal passes through the level filtering module, it still outputs a pulse signal, cmp_up_pulse, that crosses the level threshold upward, and a pulse signal, cmp_down_pulse, that crosses the level threshold downward. The start_pulse signal is determined by the control word that sets whether the signal crosses the level threshold upward or downward, while the stop_pulse signal is a separate signal. When no trigger is generated, the pulse width trigger state machine is in the IDLE state. When the start_pulse pulse is detected, the state machine transitions from the IDLE state to the CNT_FIRST state. In the CNT_FIRST state, the pulse width is counted using the counter cnt. When cnt is less than the user-set pulse width upper limit and the stop_pulse pulse is detected, the state machine enters the HOLD state. If the cnt count reaches the upper limit, the state machine returns to the IDLE state, indicating that the pulse detection did not generate a trigger. In the HOLD state, cnt continues to count based on the input signal and sets the trigger_out_r0 signal to 1. When cnt reaches the upper limit in the HOLD state, the state machine returns from the HOLD state to the IDLE state. The trigger_out_r0 signal output by the state machine is processed in the same way as other trigger modules. It is selected and output by the trigger event processing module, and finally outputs the pulse width triggered output signal trigger_out.

[0069] When any of the eight channels in the digital trigger module 200 can be selected to be turned on or off, any of the above triggering modes can be selected for triggering, and finally the trigger output module 300 outputs the final trigger result through or or and operation.

[0070] The embodiment of the present invention is further described below through a specific embodiment.

[0071] Step 1: ADC converts the analog signal into a digital signal and inputs it into the trigger system;

[0072] Step 2: Control the 8 channels on and off, and the user selects the specific trigger channel to use;

[0073] Step 3: Select different trigger types for each enabled channel. Different trigger types require different parameters to be set, as shown in Table 1 below. The effects of the relevant trigger types are as follows: Figures 12-17 shown.

[0074] Table 1 Parameters required for configuration of different trigger types

[0075]

[0076] Step 4: Perform logical operations of and or or on the enabled channel trigger results. The related logical combination effects are as follows: Figure 18 As shown, the trigger result is finally output.

[0077] In summary, the multi-type trigger system for waveform acquisition and recording based on FPGA proposed in an embodiment of the present invention is applied to the trigger system of the storage recorder. The system can capture multiple features of the input waveform, and the user can select one or more trigger sources for triggering, which enriches the trigger function of the oscilloscope and improves the waveform capture capability of the storage recorder. In terms of code writing, common functions are extracted from the functions of various triggers, thereby greatly reducing the complexity of the state machines of various triggers, reducing the number of state machine state transitions, and improving the reusability of the code.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0079] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0080] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A multi-type trigger system for waveform acquisition and recording based on FPGA, characterized in that: include: Storage recorder, digital trigger module and trigger output module, among which, The storage recorder is used to collect analog signals and convert the analog signals into digital signals to enter the digital trigger module; The digital trigger module includes a level filter detection module, a trigger event processing module and a channel selection module, which is used to open or close any of the eight trigger channels and select any preset trigger type; The trigger output module is used to perform a logical combination of or or and on the trigger outputs of the channels set to on among the eight channels and then perform a final trigger output; The trigger event processing module is used to process the trigger output module, wherein the trigger event number events and the module enable signal events_en are set, and a counter is used to count the trigger times of the trigger input signal trigger_in. If the number of trigger events is lower than the set number, no trigger is generated. If the number of trigger events reaches the set number, a trigger output signal trigger_out is generated. For different trigger mode selections, the trigger signal is output after detection and processing by three modules. The first and second modules are multiplexing modules, while the second module is a state machine unique to each trigger mode. As for which state machine is selected to trigger the signal, it depends on the trigger mode and configuration parameters selected by the user.

2. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 1, characterized in that: The level filtering detection module is used to perform level detection on the digital signal and output a pulse, wherein a threshold Vth is set. When the waveform crosses the threshold upward, a pulse cmp_up_pulse is output; when the waveform crosses the threshold downward, another pulse cmp_up_pulse is output. At the same time, a delay filter is used for filtering. When it is detected that the signal crosses the threshold, a delay judgment is started. The delay value is time_dly. If the voltage threshold after a period of delay is lower or higher than the set threshold, it is considered that the signal is relatively stable and meets the conditions for pulse output.

3. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 1, characterized in that: The trigger event processing module is only valid when each channel selects the or trigger logic combination mode, and is invalid when the and mode is selected.

4. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 1, characterized in that: The preset trigger types include level trigger, window trigger, voltage drop trigger, period trigger, and pulse trigger.

5. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 4, characterized in that: When the level trigger is selected, the level threshold and the delay parameter of the delay filter are set, the digital signal is input and two pulse signals are output through the level filter detection module. The control word that crosses the threshold upward or downward determines which of the two signals is used as the trigger input for level detection, and the signal is named start_pulse signal and the other signal is named stop_pulse signal. The state machine of the level detection is in the idle state. After encountering the start_pulse pulse, the state machine enters the HOLD state. During the HOLD state, the signal trigger_out_r0 is always in the high level state. When encountering the stop_pulse pulse, the level detection trigger state machine exits the HOLD state and returns to the IDLE state, and sets the signal trigger_out_r0 to 0. When the or mode is selected, the rising edge of the signal trigger_out_r0 is detected, and the output signal trigger_out_or is sent to the trigger event processing module. After detection by the trigger event processing module, the trigger signal of the final level trigger module is output. When the and mode is selected, the output signal trigger_out_and is equal to trigger_out_r0, and trigger_out_and is also input into the trigger event processing module, but no processing is done.

6. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 4, characterized in that: When the window trigger is selected, the input digital signal first passes through the level filter detection module. After the digital signal passes through the level filter detection module for detecting the high level, two pulse signals are output, namely, an output pulse signal th_cmp_up_pulse that crosses the high level threshold upward and an output pulse signal th_cmp_down_pulse that crosses the low level threshold downward. When the user selects internal window trigger, th_cmp_down_pulse and tl_cmp_up_pulse serve as start_pulse signals, and th_cmp_up_pulse and tl_cmp_down_pulse serve as stop_pulse signals; when the user selects external window trigger signal, the signal sources of start_pulse and stop_pulse are opposite; The state machine is initially in the IDLE state. When the start_pulse signal is detected, it means that the input signal enters the set level range. At this time, the state of the state machine enters the HOLD state, and the signal trigger_out_r0 is always set to 1 in the HOLD state. When the state machine is in the HOLD state, when the stop_pulse signal is detected, it returns to the IDLE state and sets trigger_out_r0 to 0. When the same level is triggered, trigger_out_r0 is processed by the trigger event processing module.

7. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 4, characterized in that: When the voltage drop trigger is selected and the voltage peak value continues to be lower than the set level for 1 / 2 cycle, the voltage drop trigger condition is met. The voltage drop trigger has two thresholds for triggering, which are set by the RMS effective value and the level threshold Vth to obtain the high and low level thresholds, and output th_cmp_up_pulse and th_cmp_down_pulse compared with the high level threshold, and tl_cmp_up_pulse and tl_cmp_down_pulse compared with the low level threshold; The state machine triggered by voltage drop is in IDLE state when it is not lower than the low level threshold; When the digital signal crosses the low level threshold, it cannot be determined that the level has reached the lowest value, so triggering is not selected here; When the digital signal crosses the low-level threshold upward, the state of the state machine changes and enters the CNT state. A counter cnt is used to count the input waveform to count the time the waveform is lower than the set level state. When the counter is lower than 1 / 2 cycle half_period_Max and the signal crosses the high-level threshold upward or crosses the low-level threshold downward, it means that the trigger condition is not met. At this time, the state machine returns to the IDLE state and re-detects; when the counter cnt is equal to half_period_Max, it enters the HOLD state, and the signal trigger_out_r0 is in a high-level state. When a pulse signal crossing the high-level threshold upward or crossing the low-level threshold downward is detected, the state machine returns from the HOLD state to the IDLE state machine, and clears cnt and trigger_out_r0 at the same time; When the same level is triggered, trigger_out_r0 is processed by the trigger event processing module.

8. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 4, characterized in that: When the period trigger is selected, the period trigger condition is met when the time between two rising edges or falling edges of the signal is within the set period range or outside the period range. When the outside-period trigger is selected, a trigger is generated if the signal period is less than the set period lower limit or greater than the set period upper limit; when the inside-period trigger is selected, a trigger is generated if the signal period is within the set period lower limit or less than the period upper limit.

9. The multi-type trigger system for waveform acquisition and recording based on FPGA according to claim 4, characterized in that: When the pulse trigger is selected, if the pulse width is shorter than the set pulse width, the pulse trigger condition is met.

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