Edge defect detection module, display panel and edge defect detection method

Abstract

The application relates to an edge defect detection module, a display panel and an edge defect detection method. The display panel comprises a middle area and an edge area, and the middle area is provided with a pixel unit. The middle area is arranged with a plurality of data lines, and the data lines extend along a second direction. The edge defect detection module comprises a plurality of power lines and a detection line. The plurality of power lines are arranged at least in the middle area of the display panel. The power lines extend along a first direction, and the first direction intersects the second direction. The detection line is arranged in the edge area of the display panel. The detection line extends along the second direction, and the detection line is electrically connected with the plurality of power lines and is configured to provide a test signal to the power lines in a detection process. Through the above edge defect detection module, whether the edge area of the display panel has defects can be determined, and the position of the defects can be determined.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an edge defect detection module, a display panel, and an edge defect detection method. Background Art

[0002] Display panels are typically equipped with a defect detection module or circuit to detect cracks in the periphery (edge ​​area) of the display panel during production and transportation. Because moisture from the external environment can enter the active display area through these cracks, causing display panel failure, detection of these cracks is essential.

[0003] There are generally two testing methods: eddy current testing (ET testing) and resistance testing.

[0004] Both of these inspection methods can only detect cracks in the edge area, but cannot accurately locate the defect. This requires workers to use a microscope to slowly search the entire edge area of ​​the display panel, which consumes a lot of time and energy.

[0005] Therefore, it is necessary to improve the above-mentioned shortcomings. Summary of the Invention

[0006] According to a first aspect of an embodiment of the present application, there is provided an edge defect detection module for a display panel, wherein the display panel includes a middle region and an edge region, wherein the middle region is provided with pixel units, and wherein a plurality of data lines are arranged in the middle region, and wherein the data lines extend along a second direction; the edge defect detection module includes:

[0007] a plurality of power lines, at least disposed in a middle area of ​​the display panel, the power lines extending along a first direction, the first direction intersecting the second direction;

[0008] A detection line is provided in an edge region of the display panel, the detection line extends along the second direction, the detection line is electrically connected to the plurality of power lines, and is configured to provide a test signal to the power lines during a detection process.

[0009] In some embodiments, one end of the detection line is connected to a first transistor, the first transistor includes a gate, a source, and a drain, one of the source and the drain serves as an input end, and the other serves as an output end;

[0010] The test signal is applied to the input end, and the output end is electrically connected to the detection line to conduct the test signal to the detection line.

[0011] In some embodiments, the edge defect detection module further includes a control chip, which is disposed in the pad area and electrically connected to the first transistor. The control chip includes:

[0012] a test signal interface, connected to the input terminal of the first transistor, and applying the test signal to the input terminal of the first transistor;

[0013] The gate control signal interface is connected to the gate of the first transistor and applies a gate control signal to the gate of the first transistor.

[0014] In some embodiments, the control chip further includes:

[0015] The power signal interface is electrically connected to the power line and applies a power signal to the power line.

[0016] In some embodiments, a second transistor is provided between the power signal interface and the power line, and the power signal interface applies the power signal to the power line through the second transistor.

[0017] In some embodiments, the power signal includes a VDD signal.

[0018] In some embodiments, the display panel is further provided with a power trunk line, which extends along the second direction and is electrically connected to the plurality of power lines.

[0019] In some embodiments, the detection lines are provided at the edge regions on both the left and right sides of the display panel, and each of the detection lines operates independently.

[0020] In some embodiments, the power line includes a VDD power line, and the first direction is a row direction;

[0021] The power line and the data line are arranged in film layers at different heights; one of the power line and the data line is arranged in the first source-drain layer, and the other is arranged in the second source-drain layer.

[0022] According to a second aspect of an embodiment of the present application, a display panel is provided, comprising the edge defect detection module as described above.

[0023] According to a third aspect of an embodiment of the present application, there is provided an edge defect detection method, which is applied to the display panel as described above. The edge defect detection method includes:

[0024] applying a test signal to the power line;

[0025] According to the light-emitting state of the pixel unit, it is determined whether there are defects in the edge area and the location of the defects.

[0026] In some embodiments, one end of the detection line is connected to a first transistor, the first transistor including a gate, a source, and a drain, one of the source and the drain serving as an input end, and the other serving as an output end; the test signal is applied to the input end, and the output end is electrically connected to the detection line to conduct the test signal to the detection line;

[0027] The edge defect detection module further includes a control chip, which is disposed in the pad area and electrically connected to the first transistor. The control chip includes:

[0028] a test signal interface, connected to the input terminal of the first transistor, and applying the test signal to the input terminal of the first transistor;

[0029] a gate control signal interface connected to the gate of the first transistor and applying a gate control signal to the gate of the first transistor;

[0030] The applying of the test signal to the power line includes: applying the test signal to the input terminal of the first transistor and applying a gate control signal to the gate of the first transistor at the same time.

[0031] In some embodiments, the control chip further includes:

[0032] a power signal interface, electrically connected to the power line, and applying a power signal to the power line;

[0033] When applying a test signal to the power line, a power signal is simultaneously applied to the power line through the power signal interface, and the voltage of the applied power signal is opposite to that of the test signal.

[0034] In some embodiments, the control chip further includes:

[0035] a power signal interface, electrically connected to the power line, and applying a power signal to the power line;

[0036] When a test signal is applied to the power line, the power signal interface is kept at zero voltage.

[0037] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] Figure 1This is a wiring diagram of a display panel according to an embodiment of the present application;

[0040] Figure 2 This is a circuit diagram of an edge defect detection module according to an embodiment of the present application. The edge defect detection module can be applied to Figure 1 In the display panel shown;

[0041] Figure 3 1 is a circuit diagram of a display panel according to an embodiment of the present application, which not only shows the circuit of the edge defect detection module but also shows some other circuits;

[0042] Figure 4 This is a schematic diagram of the light emission of a display panel during edge defect detection according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0044] An embodiment of the present application provides an edge defect detection module for a display panel, which is used to detect whether there are defects, such as cracks, in the edge area of ​​the display panel and can detect the location of the defects.

[0045] Figure 1 This is a wiring diagram of a display panel according to an embodiment of the present application. Figure 2 This is a circuit diagram of an edge defect detection module according to an embodiment of the present application. The edge defect detection module can be applied to Figure 1 The display panel shown. Figure 3 This is a circuit diagram of a display panel according to an embodiment of the present application, which not only shows the circuit of the edge defect detection module, but also shows some other circuits.

[0046] Please refer to Figures 1 to 3 , the display panel 100 includes a middle area and an edge area. The middle area is provided with a plurality of pixel units (not shown) arranged in an array for displaying images. When the display panel is a touch screen, the middle area can also be touched by the user. The middle area is provided with a plurality of data lines 25, and the data lines 25 extend along the second direction Y. The data lines 25 extending along the second direction Y are used to provide data information related to the image to be displayed to a row or a column of pixel units also extending along the second direction Y. The edge defect detection module applied to the display panel 100 may include:

[0047] A plurality of power lines 23 are provided at least in a middle area of ​​the display panel 100 , wherein the power lines 23 extend along a first direction X, and the first direction X intersects with the second direction Y;

[0048] The detection line 30 is provided at an edge region of the display panel 100 . The detection line 30 extends along the second direction Y. The detection line 30 is electrically connected to the plurality of power lines 23 and is configured to provide a test signal to the power lines 23 during the detection process.

[0049] In the above embodiment, the power lines 23 extending along the first direction X are used to provide power to a row or column of pixel units also extending along the first direction X. During the detection process, the detection line 30 provides test information to each power line 23. The test information can be applied to the pixel units connected to the power lines through each power line 23, affecting or determining the display of the corresponding pixel units.

[0050] During the manufacturing and transportation process, if the edge region of the display panel 100 is free of defects such as cracks, then the inspection lines 30 provided in the edge region are free of defects. Accordingly, during the inspection process, the test signal can be provided to each power line 23 via the inspection line 30. The display of the pixel units connected to each power line 23 is the same and is affected by the test signal.

[0051] If a crack or other defect exists at the edge of the display panel 100, a similar breakage defect will appear on the portion of the test line 30 located at the defective location. Due to the presence of the breakage defect, the power line 23 at the defective location (the rear end) will not receive the test signal. This will cause the display of the pixel unit at this location to differ from that of the pixel unit at the unbroken location (which can normally receive the test signal).

[0052] It can be seen that in the above embodiment, by providing a test signal to each of the power lines 23 during the detection process through the detection line 30, it is possible to detect whether there is a defect in the edge area and the location of the defect.

[0053] In some embodiments, the data line 25 is disposed only in the middle region of the display panel 100. In some embodiments, the data line 25 is not only disposed in the middle region of the display panel 100 but also extends to the edge region of the display panel 100. In some embodiments, a data supply bus or a data supply circuit 70 is disposed at one or both ends of the data line 25.

[0054] In some embodiments, the power line 23 is only disposed in the middle region of the display panel 100 . In some embodiments, the power line 23 is not only disposed in the middle region of the display panel 100 , but also extends to edge regions of the display panel 100 .

[0055] In some embodiments, the power line 23 includes or is a VDD power line. In some embodiments, the power line 23 includes or is a VSS power line.

[0056] In the above embodiments, the number of power lines 23 is not limited and can be determined according to the wiring space of the display panel. The more power lines 23 there are, the more accurate the detection.

[0057] To prevent a short circuit caused by the reverse flow of the test signal during the above-mentioned detection process, a first transistor 40 can be provided at the test signal input terminal (the lower end in the figure) of the detection line 30. The first transistor 40 may include a gate 47, a source, and a drain. One of the source and drain serves as an input terminal 43, and the other serves as an output terminal 45. The test signal is applied to the input terminal 43, and the output terminal 45 is electrically connected to the detection line 30, transmitting the test signal to the detection line 30.

[0058] Furthermore, the edge defect detection module may further include a control chip 80, which may be disposed in a pad area (Pad area) and electrically connected to the first transistor 40. The control chip 80 includes:

[0059] a test signal interface 83 connected to the input terminal 43 of the first transistor 40 and applying the test signal to the input terminal 43 of the first transistor 40;

[0060] The gate control signal interface 85 is connected to the gate 47 of the first transistor 40 and applies a gate control signal to the gate 47 of the first transistor 40 .

[0061] During the detection process, the control chip 80 applies a test signal and a gate control signal to the input terminal 43 and the gate 47 of the first transistor 40 through the test signal interface 83 and the gate control signal interface 85 respectively, thereby turning on the first transistor 40 and realizing the application of the test signal to the detection line 30.

[0062] In some embodiments, the control chip 80 further includes a power signal interface 87. The power signal interface 87 is electrically connected to the plurality of power lines 23 and is configured to apply a power signal to the power lines 23. The power signal may be a VDD signal. During both the normal display process and the aforementioned detection process, the power signal interface 87 may provide an operating power signal or an auxiliary power signal to the power lines 23.

[0063] For example, during the detection process, a normal operating power supply voltage, such as 4.6V, can be provided to the power line 23 through the power signal interface 87, and a test signal can be provided to the power line 23 through the test signal interface 83 at the same time. The voltage of the test signal is opposite to the positive and negative voltages of the normal operating power supply voltage, such as -7V. In other words, if there is no defect in the edge area of ​​the display panel 100, the test signal will be smoothly applied to the power line 23, offsetting or lowering the operating power supply voltage provided by the power signal interface 87, so that the pixel unit at the edge area cannot work normally and cannot display normally, such as displaying black lines. Figure 4 This indicates that there are no defects in the edge area. On the contrary, during the inspection process, the area that can still be displayed normally, such as the area where bright lines appear, is the area where edge defects occur. Figure 4 That is, for the pixel row / column where the bright line appears, the corresponding edge area is the edge area where the defect occurs.

[0064] For another example, during the detection process, no voltage, i.e., 0V, can be provided to the power line 23 via the power signal interface 87, and at the same time, a test signal can be provided to the power line 23 via the test signal interface 83. The voltage of the test signal is equal to or slightly greater than the normal operating power voltage, for example, the test signal is 4.6V. In other words, if there is no defect in the edge area of ​​the display panel 100, the test signal will be smoothly applied to the power line 23, so that the pixel unit at the edge area can emit light normally, such as displaying a bright line. Figure 4 This indicates that there are no defects in the edge area. On the contrary, during the inspection process, the area that cannot emit light normally, such as the area where black lines appear, is the area where edge defects occur. Figure 4 That is, for the pixel row / column where the black line appears, the corresponding edge area is the edge area where the defect occurs.

[0065] The display panel 100 may further include a power trunk line 78 extending along the second direction Y and electrically connected to each power line 23 to facilitate simultaneous provision of a power signal from the power signal interface 87 to each power line 23. The power signal may be a VDD signal.

[0066] In one embodiment, a second transistor 50 is provided between the power signal interface 87 and the power lines 23 (more specifically, between the power signal interface 87 and the power trunk line 78). The power signal interface 87 applies the power signal to each power line 23 via the second transistor 50. The second transistor 50 may include a gate 57, a source, and a drain. One of the source and drain serves as an input terminal 53, and the other serves as an output terminal 55. The power signal is applied to the input terminal 53, and the output terminal 55 is electrically connected to the power trunk line 78 to transmit the power signal to each power line 23.

[0067] If necessary, the detection lines 30 or edge defect detection modules (including the first transistor 40) can be installed in the left and right edge regions of the display panel 100, and each detection line 30 can operate independently. The detection line 30 installed in the left edge region is used to detect edge defects in the left edge region, and the detection line 30 installed in the right edge region is used to detect edge defects in the right edge region.

[0068] In the above embodiment, the first direction is a row direction, and the second direction is a column direction. In some embodiments, the first direction is a column direction, and the second direction is a row direction.

[0069] To avoid mutual interference and facilitate manufacturing, the power line 23 and the data line 25 are disposed in film layers at different heights. For example, one of the power line 23 and the data line 25 can be disposed in the first source-drain layer (SD1), and the other can be disposed in the second source-drain layer (SD2).

[0070] In some embodiments, the display panel 100 further includes V int Supply bus 72 and multiple V int Line 27. Each V int The line 27 extends along the first direction X and is used to provide V for the driving circuits of a row or a column of pixel units extending along the first direction X. int Signal. V int Supply bus 72 and each V int Line 27 is connected to each V int Line 27 provides V int Signal.

[0071] In some embodiments, the display panel 100 further includes other signal lines, such as a VSS power line, a Reset signal line, an EM signal line, and the like.

[0072] The present application also provides an edge defect detection method, which can be applied to the display panel 100 and is used to detect whether there are defects in the edge area of ​​the display panel 100 and the location of the defects. The edge defect detection method includes:

[0073] applying a test signal to the power line 23;

[0074] According to the light-emitting state of the pixel unit, it is determined whether there are defects in the edge area and the location of the defects.

[0075] If a crack or other defect exists at the edge of the display panel 100, a similar breakage defect will appear on the portion of the test line 30 located at the defective location. Due to the presence of the breakage defect, the power line 23 at the defective location (the rear end) will not receive the test signal. This will cause the display of the pixel unit at this location to differ from that of the pixel unit at the unbroken location (which can normally receive the test signal).

[0076] It can be seen that in the above embodiment, by providing a test signal to each of the power lines 23 during the detection process through the detection line 30, it is possible to detect whether there is a defect in the edge area and the location of the defect.

[0077] In some embodiments, one end of the detection line 30 is connected to a first transistor 40, which includes a gate 47, a source, and a drain. One of the source and drain serves as an input terminal 43, and the other serves as an output terminal 45. The test signal is applied to the input terminal 43, and the output terminal 45 is electrically connected to the detection line 30 to transmit the test signal to the detection line 30.

[0078] Furthermore, the edge defect detection module further includes a control chip 80, which can be disposed in a pad area (Pad area) and electrically connected to the first transistor 40. The control chip 80 includes:

[0079] a test signal interface 83 connected to the input terminal 43 of the first transistor 40 and applying the test signal to the input terminal 43 of the first transistor 40;

[0080] The gate control signal interface 85 is connected to the gate 47 of the first transistor 40 and applies a gate control signal to the gate 47 of the first transistor 40 .

[0081] The applying of the test signal to the power line 23 includes applying the test signal to the input terminal of the first transistor 40 and applying a gate control signal to the gate 47 of the first transistor 40 at the same time.

[0082] Specifically, during the detection process, the control chip 80 applies a test signal and a gate control signal to the input terminal 43 and the gate 47 of the first transistor 40 through the test signal interface 83 and the gate control signal interface 85 respectively, thereby turning on the first transistor 40 and realizing the application of the test signal to the detection line 30.

[0083] In some embodiments, the control chip 80 further includes a power signal interface 87. The power signal interface 87 is electrically connected to the plurality of power lines 23 and applies a power signal to the power lines 23;

[0084] When applying the test signal to the power line 23 , a power signal is simultaneously applied to the power line 23 through the power signal interface 87 , and the voltage of the applied power signal is opposite to that of the test signal.

[0085] In some embodiments, the control chip 80 further includes a power signal interface 87. The power signal interface 87 is electrically connected to the plurality of power lines 23 and is configured to apply a power signal to the power lines 23. The power signal may be a VDD signal. During both the normal display process and the aforementioned detection process, the power signal interface 87 may provide an operating power signal or an auxiliary power signal to the power lines 23.

[0086] For example, during the detection process, a gate control signal, such as a voltage of -7V, can be applied to the gate 47 of the first transistor 40 through the gate control signal interface 85 to turn on the first transistor 40; a normal operating power supply voltage, such as a voltage of 4.6V, can be provided to the power line 23 through the power signal interface 87, and a test signal can be provided to the power line 23 through the test signal interface 83 at the same time. The voltage of the test signal is opposite to the positive and negative voltages of the normal operating power supply voltage, such as the test signal is a voltage of -7V. In other words, if there are no defects in the edge area of ​​the display panel 100, the test signal will be smoothly applied to the power line 23, offsetting or lowering the operating power supply voltage provided by the power signal interface 87, so that the pixel unit at the location cannot work normally and cannot display normally, such as displaying black lines. Figure 4 This indicates that there are no defects in the edge area. On the contrary, during the inspection process, the area that can still be displayed normally, such as the area where bright lines appear, is the area where edge defects occur. Figure 4 That is, for the pixel row / column where the bright line appears, the corresponding edge area is the edge area where the defect occurs.

[0087] For another example, during the detection process, a gate control signal, such as a voltage of -7V, can be applied to the gate 47 of the first transistor 40 through the gate control signal interface 85 to turn on the first transistor 40; no voltage, i.e., 0V, can be provided to the power line 23 through the power signal interface 87, and a test signal can be provided to the power line 23 through the test signal interface 83 at the same time. The voltage of the test signal is equal to or slightly greater than the normal operating power supply voltage, such as a voltage of 4.6V. In other words, if there are no defects in the edge area of ​​the display panel 100, the above test signal will be smoothly applied to the power line 23, so that the pixel unit at that location can emit light normally, such as displaying a bright line. Figure 4 This indicates that there are no defects in the edge area. On the contrary, during the inspection process, the area that cannot emit light normally, such as the area where black lines appear, is the area where edge defects occur. Figure 4 That is, for the pixel row / column where the black line appears, the corresponding edge area is the edge area where the defect occurs.

[0088] In the above embodiments, the first transistor 40 and the second transistor 50 are both PMOS transistors.

[0089] In the above embodiments, the voltage values ​​of the gate control signal, the voltage value of the normal working power supply, and the voltage value of the test signal are only examples. There is no special requirement for the above voltage values, as long as they can achieve the above detection effect.

[0090] The above embodiments of the present application can complement each other if no conflict occurs.

[0091] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0092] The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0093] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0094] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An edge defect detection module for a display panel, characterized in that: The display panel includes a middle area and an edge area, the middle area is provided with pixel units, the middle area is arranged with a plurality of data lines, and the data lines extend along the second direction; The edge defect detection module includes: a plurality of power lines, at least disposed in a middle area of ​​the display panel, the power lines extending along a first direction, the first direction intersecting the second direction; a detection line, disposed in an edge region of the display panel, the detection line extending along the second direction, the detection line being electrically connected to the plurality of power lines, and being configured to provide a test signal to the power lines during a detection process; A control chip comprising a power signal interface and a test signal interface, wherein the power signal interface is electrically connected to the power line and is used to apply a power signal to the power line; and the test signal interface is electrically connected to the detection line and is used to apply the test signal to the detection line. A second transistor is provided between the power signal interface and the power line, and the power signal interface applies the power signal to the power line through the second transistor; wherein, During the detection process, the power signal interface simultaneously applies power signals with opposite positive and negative types to the test signal voltages to the multiple power lines.

2. The edge defect detection module according to claim 1, wherein: One end of the detection line is connected to a first transistor, the first transistor including a gate, a source and a drain, one of the source and the drain serving as an input end and the other serving as an output end; The test signal is applied to the input end, and the output end is electrically connected to the detection line to conduct the test signal to the detection line.

3. The edge defect detection module according to claim 2, wherein: The control chip is arranged in the pad area and is electrically connected to the first transistor. The test signal interface is connected to the input terminal of the first transistor and applies the test signal to the input terminal of the first transistor. The control chip further includes: The gate control signal interface is connected to the gate of the first transistor and applies a gate control signal to the gate of the first transistor.

4. The edge defect detection module according to claim 1, wherein: The power signal includes a VDD signal.

5. The edge defect detection module according to claim 1, wherein: The display panel is further provided with a power trunk line, which extends along the second direction and is electrically connected to the plurality of power lines.

6. The edge defect detection module according to claim 1, wherein: The detection lines are arranged on the edge areas on the left and right sides of the display panel, and each of the detection lines works independently.

7. The edge defect detection module according to claim 1, wherein: The power line includes a VDD power line, and the first direction is a row direction; The power line and the data line are arranged in film layers at different heights; one of the power line and the data line is arranged in the first source-drain layer, and the other is arranged in the second source-drain layer.

8. A display panel, characterized in that: The display panel includes the edge defect detection module according to any one of claims 1 to 7.

9. An edge defect detection method, applied to the display panel according to claim 8, characterized in that: The edge defect detection method comprises: applying a test signal to the power line; According to the light-emitting state of the pixel unit, it is determined whether there are defects in the edge area and the location of the defects.

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