A semiconductor structure and a method for fabricating the semiconductor structure.

Abstract

This invention discloses a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure may include: a substrate; a shallow trench isolation structure disposed in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate; and a first gate structure at least partially disposed on the shallow trench isolation structure. The first gate structure includes a first dielectric layer, a first conductive layer, and a sidewall insulating layer covering the sidewalls of both the first dielectric layer and the first conductive layer. The top two ends of the first conductive layer each have an irregularly shaped protrusion. The distance between the vertices of the two irregularly shaped protrusions of the first conductive layer in the orthographic projection onto the substrate is less than the distance between the top surfaces of the sidewall insulating layer in the orthographic projection onto the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] Shallow trench isolation is currently the primary method for achieving device isolation in large-scale integrated circuits. For example, trench isolation structures can be used to isolate adjacent active regions from each other, thereby preventing interference between components formed on different active regions. Furthermore, semiconductor integrated circuits typically contain a large number of electrically conductive structures. With the continuous development of semiconductor technology, the size of integrated circuits tends to decrease. Even though the size of integrated circuits can be reduced by shrinking the size of electrically conductive structures, the large space still needed to accommodate these structures makes it difficult to further reduce the overall size of semiconductor integrated circuits. Summary of the Invention

[0003] The technical problem to be solved by this invention is: how to effectively reduce the size of semiconductor structures.

[0004] To address the aforementioned technical problems, this invention provides a semiconductor structure and a method for fabricating the semiconductor structure.

[0005] A first aspect of the present invention provides a semiconductor structure comprising:

[0006] Base;

[0007] A shallow trench isolation structure is disposed in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate;

[0008] A first gate structure is at least partially disposed on the shallow trench isolation structure. The first gate structure includes a first dielectric layer and a first conductive layer, and the top of the first conductive layer has an irregular protrusion.

[0009] In some embodiments, having irregular protrusions on the top of the first conductive layer includes having irregular protrusions at both ends of the top of the first conductive layer.

[0010] In some embodiments, the top center of the first conductive layer is flat.

[0011] In some embodiments, the bottom surface of the first conductive layer is concave from the edge to the center, the upper surface of the first dielectric layer is concave from the edge to the center, and the upper surface of the first dielectric layer is fitted with the bottom surface of the first conductive layer.

[0012] In some embodiments, the semiconductor structure further includes a second gate structure disposed on the substrate, the second gate structure including a second dielectric layer and a second conductive layer sequentially deposited on the substrate.

[0013] In some embodiments, the top of the irregular protrusion is lower than the top of the second conductive layer.

[0014] In some embodiments, the shallow trench isolation structure includes at least three insulating layers.

[0015] In some embodiments, the shallow trench isolation structure includes:

[0016] First insulating layer;

[0017] A second insulating layer, which covers the sidewalls and bottom of the first insulating layer;

[0018] A third insulating layer, which fills the groove formed by the second insulating layer.

[0019] In some embodiments, the lateral dimension of the first gate structure is smaller than the lateral dimension of the third insulating layer.

[0020] In some embodiments, the first gate structure further includes:

[0021] A fourth insulating layer covers the upper surface of the third insulating layer and the sidewalls of the first dielectric layer and the first conductive layer.

[0022] In some embodiments, the semiconductor structure further includes:

[0023] A shielding layer that covers the first conductive layer and at least a portion of the fourth insulating layer;

[0024] A gate spacer that covers the upper surface of the fourth insulating layer, the shielding layer, the second insulating layer, and a portion of the first insulating layer.

[0025] A second aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:

[0026] Provide a base;

[0027] A shallow trench isolation structure is formed in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate;

[0028] A dielectric layer is deposited covering the substrate and the upper surface of the shallow trench isolation structure;

[0029] Deposit a conductive layer covering the dielectric layer;

[0030] The conductive layer and the dielectric layer are etched to form a first gate structure at least on the shallow trench isolation structure, wherein the top of the conductive layer in the first gate structure has an irregular protrusion.

[0031] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0032] The semiconductor structure provided by this invention may include a shallow trench isolation structure disposed in a substrate, and a first gate structure at least partially disposed on the shallow trench isolation structure. At least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate. The first gate structure may include a first dielectric layer and a first conductive layer, and the top two ends of the first conductive layer have irregularly shaped protrusions. By disposing the first gate structure on the shallow trench isolation structure, the space on the shallow trench isolation structure can be fully utilized, effectively reducing the overall size of the semiconductor structure. Attached Figure Description

[0033] The scope of this disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings are:

[0034] Figure 1 This diagram shows a cross-sectional view of a semiconductor structure provided in Embodiment 1 of the present invention;

[0035] Figure 2 This shows a cross-sectional schematic diagram of a semiconductor structure provided in Embodiment 2 of the present invention;

[0036] Figure 3 A schematic flowchart of a semiconductor structure fabrication method provided by an embodiment of the present invention is shown;

[0037] Figures 4 to 9 The diagram shows the cross-sectional structure of each step in the semiconductor structure fabrication method. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the implementation method of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0039] Shallow trench isolation is currently the primary method for achieving device isolation in large-scale integrated circuits. For example, trench isolation structures can be used to isolate adjacent active regions from each other, thereby preventing interference between components formed on different active regions. Furthermore, semiconductor integrated circuits typically contain a large number of electrically conductive structures. With the continuous development of semiconductor technology, the size of integrated circuits tends to decrease. Even though the size of integrated circuits can be reduced by shrinking the size of electrically conductive structures, the large space still needed to accommodate these structures makes it difficult to further reduce the overall size of semiconductor integrated circuits.

[0040] In view of this, the present invention provides a semiconductor structure that may include a shallow trench isolation structure disposed in a substrate, and a first gate structure at least partially disposed on the shallow trench isolation structure. The upper surface of the shallow trench isolation structure is at least partially lower than the upper surface of the substrate. The first gate structure may include a first dielectric layer and a first conductive layer, and the top two ends of the first conductive layer have irregularly shaped protrusions. By disposing the first gate structure on the shallow trench isolation structure, the space on the shallow trench isolation structure can be fully utilized, effectively reducing the overall size of the semiconductor structure.

[0041] Example 1

[0042] See Figure 1 As shown, Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention is shown, which includes:

[0043] Base 10;

[0044] A shallow trench isolation structure 11 is disposed in the substrate 10, and at least a portion of the upper surface of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10.

[0045] A first gate structure 12 is at least partially disposed on a shallow trench isolation structure 11. The first gate structure 12 includes a first dielectric layer 121 and a first conductive layer 122. The top of the first conductive layer 122 has an irregular protrusion.

[0046] The substrate 10 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the substrate 10 can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator).

[0047] In some embodiments, a shallow trench isolation structure 11 can be formed in the substrate 10 using a shallow trench isolation process. Specifically, multiple shallow trenches can be etched on the substrate 10, and insulating material can be deposited to fill each shallow trench to form the shallow trench isolation structure 11. At least a portion of the upper surface of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10.

[0048] In this embodiment of the invention, the shallow trench isolation structure 11 may include at least three insulating layers. In some embodiments, the shallow trench isolation structure 11 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The first insulating layer 111 may have a concave cross-section. The second insulating layer 112 covers the sidewalls and bottom of the first insulating layer 111, and the third insulating layer 113 fills the groove of the second insulating layer 112. The shallow trench isolation structure 11 formed by the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 has an upper surface lower than the upper surface of the substrate 10. In some embodiments, the upper surface of the shallow trench isolation structure 11 may be concave from both sides to the middle; in other embodiments, the first insulating layer 111, the second insulating layer 112, and the upper surface of the substrate 10 may be substantially on the same plane, and the upper surface of the third insulating layer 113 may be lower than the upper surface of the substrate 10. See [link to relevant documentation] for details. Figure 1 As shown. As a specific example, the first insulating layer 111 can be silicon oxide, the second insulating layer 112 can be silicon nitride, and the third insulating layer 113 can be silicon oxide.

[0049] In the first direction, the lateral dimension of the first gate structure 12 may be less than or equal to the lateral dimension of the third insulating layer 113.

[0050] In this embodiment of the invention, the first gate structure 12 may further include a fourth insulating layer 123, which covers the upper surface of the third insulating layer 113 and the sidewalls of the first dielectric layer 121 and the first conductive layer 122. In some embodiments, when the upper surface of the third insulating layer 113 is lower than the upper surface of the substrate 10, the fourth insulating layer 123 may be provided to cover the upper surface of the third insulating layer 113, a portion of the sidewalls of the second insulating layer 112, and the sidewalls of the first dielectric layer 121 and the first conductive layer 122, wherein the fourth insulating layer 123 may include silicon oxide.

[0051] It should be noted that, in this embodiment of the invention, the first gate structure 12 can be completely disposed on the shallow trench isolation structure 11, such as... Figure 1 As shown, in other embodiments, the first gate structure 12 may also be partially disposed on the shallow trench isolation structure 11, wherein the top of the first conductive layer 122 disposed on the shallow trench isolation structure 11 has an irregular protrusion.

[0052] In some embodiments, the semiconductor structure may further include a shielding layer 13 and a gate spacer 14, wherein the shielding layer 13 covers the first conductive layer 122 and at least a portion of the fourth insulating layer 123, and the gate spacer 14 covers the upper surface of the fourth insulating layer 123, the shielding layer 13, the second insulating layer 112, and a portion of the upper surface of the first insulating layer 111. The shielding layer 13 may include silicon nitride, and the gate spacer 14 may include silicon oxide or silicon nitride.

[0053] The above describes a semiconductor structure provided by an embodiment of the present invention. This semiconductor structure may include a shallow trench isolation structure 11 disposed in a substrate 10, and a first gate structure 12 disposed on the shallow trench isolation structure 11. At least a portion of the upper surface of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10. The first gate structure 12 may include a first dielectric layer 121 and a first conductive layer 122, with irregularly shaped protrusions at both ends of the top of the first conductive layer 122 and a flat surface in the middle of the top. By disposing the first gate structure 12 on the shallow trench isolation structure 11 and using the first gate structure 12 as a support or device interconnect, the space on the shallow trench isolation structure 11 can be fully utilized, effectively reducing the overall size of the semiconductor structure.

[0054] In this embodiment of the invention, a second gate structure 15 may also be provided, as described in the following embodiment three.

[0055] Example 2

[0056] It should be noted that Embodiment 2 can be implemented based on Embodiment 1 above. For the sake of brevity, Embodiment 2 will mainly focus on the differences between Embodiment 2 and Embodiment 1.

[0057] See Figure 2 As shown, Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of the present invention is shown, which includes:

[0058] Base 10;

[0059] A shallow trench isolation structure 11 is disposed in the substrate 10, and at least a portion of the upper surface of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10.

[0060] A first gate structure 12 is at least partially disposed on a shallow trench isolation structure 11. The first gate structure 12 includes a first dielectric layer 121 and a first conductive layer 122. The top of the first conductive layer 122 has an irregular protrusion.

[0061] The second gate structure 15 is disposed on the substrate 10 and includes a second dielectric layer 151 and a second conductive layer 152 sequentially deposited on the substrate 10.

[0062] The substrate 10, the shallow trench isolation structure 11, and the first gate structure 12 can be configured in the same manner as in Embodiment 1. In the following description, it will be described based on the fact that the upper surface of a portion of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10, and the first gate structure 12 is completely disposed on the shallow trench isolation structure 11. In some embodiments, specifically, the upper surfaces of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 in the shallow trench isolation structure 11 are all lower than the upper surface of the substrate 10, and the upper surface of the third insulating layer 113 is lower than the upper surfaces of the first insulating layer 111 and the second insulating layer 112.

[0063] In this embodiment of the invention, the second gate structure 15 can be disposed on the substrate 10 and spaced apart from the first gate structure 12, wherein the upper surface of the second dielectric layer 151 and the upper surface of the second conductive layer 152 are both substantially parallel surfaces. (See also...) Figure 2 As indicated by the dashed lines at the top and bottom of the irregular protrusion, the top of the irregular protrusion in the first conductive layer 122 may be lower than the top of the second conductive layer 152. Similarly, the top of the first dielectric layer 121 may also be lower than the top of the second dielectric layer 151. In some embodiments, the second dielectric layer 151 may be made of the same material as the first dielectric layer 121, and the second conductive layer 152 may also be made of the same material as the first conductive layer 122.

[0064] In some embodiments, the second gate structure 15 may also have the same structure as the first gate structure 12. For example, the second gate structure 15 may also have a fifth insulating layer 153. The fifth insulating layer 153 may be made of the same material as the fourth insulating layer 123. The fifth insulating layer 153 covers the substrate 10 and the sidewalls of the second dielectric layer 151 and the second conductive layer 152. In some embodiments, the semiconductor structure may also have a shielding layer 13 covering the second conductive layer 152 and at least part of the fifth insulating layer 153, and a gate spacer 14 covering the fifth insulating layer 153, the shielding layer 13 and the substrate 10.

[0065] The above describes a semiconductor structure provided by an embodiment of the present invention. This semiconductor structure may include a shallow trench isolation structure 11 disposed in a substrate 10, and a first gate structure 12 at least partially disposed on the shallow trench isolation structure 11. At least a portion of the upper surface of the shallow trench isolation structure 11 is lower than the upper surface of the substrate 10. The first gate structure 12 may include a first dielectric layer 121 and a first conductive layer 122, with irregular protrusions at both ends of the top of the first conductive layer 122 and a flat surface in the middle of the top. Furthermore, the semiconductor structure also includes a second gate structure 15 disposed on the substrate 10, comprising a second dielectric layer 151 and a second conductive layer 152 sequentially deposited on the substrate 10. The upper surfaces of the second dielectric layer 151 and the second conductive layer 152 are substantially parallel surfaces. In addition to achieving the beneficial effects of Embodiment 1 of the present invention, this semiconductor structure can also provide more gate structures for support or interconnection.

[0066] In this embodiment of the invention, a method for preparing a semiconductor structure is also provided, as described in Embodiment 3.

[0067] Example 3

[0068] See Figures 3 to 9 As shown, Figure 3 This diagram illustrates a process flow chart of a semiconductor structure fabrication method provided by an embodiment of the present invention. Figures 4 to 9 This diagram shows cross-sectional structural schematics corresponding to each step in the semiconductor structure fabrication method, which includes:

[0069] Step S101: Provide a substrate;

[0070] Step S102: Form a shallow trench isolation structure in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate;

[0071] Step S103: Deposit a dielectric layer covering the substrate and the upper surface of the shallow trench isolation structure;

[0072] Step S104: Deposit a conductive layer covering the dielectric layer;

[0073] Step S105: Etch the conductive layer and the dielectric layer to form a first gate structure at least on the shallow trench isolation structure, wherein the top of the conductive layer in the first gate structure has an irregular protrusion.

[0074] See Figure 4 As shown, Figure 4The illustration shows a substrate 20 provided in an embodiment of the present invention. The substrate 20 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator), etc. In other embodiments, the substrate 20 can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0075] Step S102 can specifically involve forming a shallow trench isolation structure 21 in the substrate 20 using a shallow trench isolation process. Specifically, multiple shallow trenches can be etched on the substrate 20, and insulating material can be deposited to fill each shallow trench to form the shallow trench isolation structure 21. The upper surface of the shallow trench isolation structure 21 is lower than that of the substrate 20. For details, please refer to [link to relevant documentation]. Figure 5 As shown.

[0076] In other embodiments, the shallow trench isolation structure 21 may also include at least three insulating layers.

[0077] Step S103 can specifically involve forming a dielectric layer 22 on the upper surface of the conformal covering substrate 20 and the shallow trench isolation structure 21, see [link to previous section]. Figure 6 As shown.

[0078] Step S104 can specifically involve forming a conductive layer 23 over the conformal covering dielectric layer 22, as detailed in [reference needed]. Figure 7 As shown.

[0079] Step S105 can specifically involve etching the conductive layer 23 and the dielectric layer 22 using a dry etching or wet etching process to form a first gate structure 24 at least on the shallow trench isolation structure 21. The top of the conductive layer 23 in the first gate structure 24 has an irregularly shaped protrusion, as detailed in [reference needed]. Figure 8 As shown.

[0080] In the first direction, the lateral dimension of the first gate structure 24 is smaller than the lateral dimension of the shallow trench isolation structure 21. The irregular protrusions on the top of the conductive layer 23 in the first gate structure 24 may include irregular protrusions at both ends of the top of the conductive layer 23, wherein the middle of the top of the conductive layer 23 in the first gate structure 24 is flat.

[0081] In other embodiments, a first gate structure 24 can be formed on the shallow trench isolation structure 21 and a second gate structure 25 can be formed on the substrate 20 by simultaneously etching the conductive layer 23 and the dielectric layer 22 located on the shallow trench isolation structure 21 and the substrate 20. In some embodiments, the height of each component of the first gate structure 24 may be lower than the height of the corresponding component in the second gate structure 25. For details, please refer to [link to relevant documentation]. Figure 9 As shown.

[0082] The above describes a semiconductor structure fabrication method provided by an embodiment of the present invention. A shallow trench isolation structure 21 is formed in a substrate 20, with at least a portion of its upper surface lower than the upper surface of the substrate 20. A dielectric layer 22 covering the substrate 20 and the upper surface of the shallow trench isolation structure 21, and a conductive layer 23 covering the dielectric layer 22 are deposited. The conductive layer 23 and the dielectric layer 22 are etched, thereby forming a first gate structure 24 at least on the shallow trench isolation structure 21. The top of the conductive layer 23 in the first gate structure 24 has an irregularly shaped protrusion. This method, by setting the first gate structure 24 on the shallow trench isolation structure 21 and utilizing the first gate structure 24 as a support or for subsequent device interconnection, can fully utilize the space on the shallow trench isolation structure 21, achieving an effective reduction in the overall size of the semiconductor structure.

[0083] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A shallow trench isolation structure is disposed in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate; A first gate structure is at least partially disposed on the shallow trench isolation structure. The first gate structure includes a first dielectric layer, a first conductive layer, and a sidewall insulating layer covering the sidewalls of both the first dielectric layer and the first conductive layer. The top two ends of the first conductive layer each have an irregular protrusion. Wherein, the distance between the vertices of the two irregular protrusions of the first conductive layer in the orthographic projection of the substrate is less than the distance between the top surface of the sidewall insulating layer in the orthographic projection of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The top center of the first conductive layer is flat.

3. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the first conductive layer is concave from the edge to the center, and the upper surface of the first dielectric layer is concave from the edge to the center, and the upper surface of the first dielectric layer is fitted with the bottom surface of the first conductive layer.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second gate structure disposed on the substrate, the second gate structure comprising a second dielectric layer and a second conductive layer sequentially deposited on the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The top of the irregular protrusion is lower than the top of the second conductive layer.

6. The semiconductor structure according to claim 1, characterized in that, The shallow trench isolation structure includes at least three insulating layers.

7. The semiconductor structure according to claim 6, characterized in that, The shallow trench isolation structure includes: First insulating layer; A second insulating layer, which covers the sidewalls and bottom of the first insulating layer; A third insulating layer, which fills the groove formed by the second insulating layer.

8. The semiconductor structure according to claim 7, characterized in that, The lateral dimension of the first gate structure is smaller than the lateral dimension of the third insulating layer.

9. The semiconductor structure according to claim 8, characterized in that, The sidewall insulation layer also covers the upper surface of the third insulation layer.

10. The semiconductor structure according to claim 9, characterized in that, Also includes: A shielding layer is located between the apex of the irregular protrusion and the sidewall insulating layer, and the shielding layer covers the first conductive layer and at least a portion of the sidewall insulating layer; A gate spacer that covers the upper surface of the sidewall insulating layer, the shielding layer, the second insulating layer, and a portion of the first insulating layer.

11. The semiconductor structure according to claim 10, characterized in that, The shielding layer completely covers the irregular protrusion on top of the first conductive layer.

12. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A shallow trench isolation structure is formed in the substrate, wherein at least a portion of the upper surface of the shallow trench isolation structure is lower than the upper surface of the substrate; A dielectric layer is deposited covering the substrate and the upper surface of the shallow trench isolation structure; Deposit a conductive layer covering the dielectric layer; The conductive layer and the dielectric layer are etched to form a first gate structure at least on the shallow trench isolation structure, wherein the top two ends of the conductive layer in the first gate structure each have an irregular protrusion. A sidewall insulating layer is formed covering the sidewalls of both the dielectric layer and the conductive layer in the first gate structure, wherein the distance between the vertices of the two irregular protrusions of the conductive layer in the orthographic projection of the substrate is smaller than the distance between the top surface of the sidewall insulating layer in the orthographic projection of the substrate.

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