A method of forming a via, wafer level package structure, method and communication device

Abstract

The application provides a via hole forming method, a wafer level packaging structure, a method and a communication device. The via hole forming method comprises the following steps: providing a cover plate, wherein the cover plate comprises a first surface and a second surface arranged opposite to the first surface; forming a blind hole on the first surface of the cover plate; forming a protective layer in the blind hole; performing a thinning treatment on the second surface of the cover plate to expose the protective layer at the bottom of the blind hole; and removing the protective layer to convert the blind hole into a via hole. The technical solution provided by the application improves the yield of forming the via hole in the cover plate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming a through-hole, a wafer-level packaging structure, a method, and a communication device. Background Technology

[0002] A wafer-level package structure includes a substrate and a cover plate bonded together. The substrate surface has conductive structures, and the cover plate has through-silicon vias (TSVs). The TSVs are used to bring out the electrical signals of the conductive structures on the substrate surface. The TSVs consist of the via and a conductive layer inside the via.

[0003] Figures 1-4 This is a schematic diagram showing the structure of each step in a wafer-level packaging method provided by existing technology. (See also...) Figure 1 A substrate 001 and a cover plate 002 are provided. The surface of the substrate 001 is provided with a conductive structure 10, a resonant unit 11, and a first connection structure 12. The resonant unit 11 includes a stack of a bottom electrode, a piezoelectric layer, and a top electrode. The conductive structure 10 is connected to the electrode (e.g., the bottom electrode or the top electrode) of the resonant unit 11. The first surface of the cover plate 002 is provided with a blind hole 20, a second connection structure 21, and a third connection structure 22. See also... Figure 2 The first surface of the cover plate 002 is fixed to the substrate 001, wherein the first connection structure 12 of the substrate 001 and the second connection structure 21 of the cover plate 002 are fixedly connected, and the third connection structure 22 of the cover plate 002 is fixedly connected to the conductive structure 10 of the substrate 001. See also Figure 3 The second surface of the cover plate 002 was thinned for the first time through a grinding process, and the bottom of the blind hole 20 was not yet exposed. See also Figure 4 The second surface of the cover plate 002 is thinned a second time by etching to expose the bottom of the blind hole 20, thus converting the blind hole 20 into a through hole 200. A conductive layer is then formed in the through hole 200, and the electrical signals of the conductive structure 10 of the substrate 001 are brought out using the conductive layer.

[0004] In the above wafer-level packaging method, both the substrate 001 and the cover plate 002 are illustrated using a silicon wafer as an example. The blind via 20 is a blind via on the silicon wafer, and the through-hole 200 is a silicon through-hole. When the second surface of the cover plate 002 is thinned for the first time using a polishing process, if the bottom of the blind via 20 is directly exposed, impurities such as polishing slurry used in the polishing process and silicon debris from the cover plate 002 can easily enter the hole. Furthermore, these impurities are not easily cleaned, thus reducing the yield of the through-hole 200.

[0005] In the aforementioned wafer-level packaging method, a dry etching process is typically used to perform a second thinning treatment on the second surface of the cover plate 002, see [link to relevant documentation]. Figure 4During the process of etching away the bottom of the blind via 20 to convert it into a through via 200, the second surface side of the through via 200 near the cover plate 002 is easily etched and enlarged. On the one hand, this increases the probability that the edge material of the photomask used for etching and the silicon debris of the cover plate 002 will fall into the through via 200, which is not easy to clean. On the other hand, it makes the shape of the through via 200 inconsistent with the preset shape, thereby reducing the yield of the through via 200.

[0006] In summary, the existing wafer-level packaging methods have low yield rates for vias during the fabrication of the cover plate. Summary of the Invention

[0007] This application provides a method for forming vias, a wafer-level packaging structure, a method, and a communication device to improve the yield of forming vias in a cover plate.

[0008] According to one aspect of this application, a method for forming a through hole is provided, comprising:

[0009] A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface;

[0010] A blind hole is formed on the first surface of the cover plate;

[0011] A protective layer is formed inside the blind hole;

[0012] The second surface of the cover plate is thinned to expose the protective layer at the bottom of the blind hole;

[0013] Remove the protective layer to convert the blind hole into a through hole.

[0014] Optionally, forming a blind hole on the first surface of the cover plate includes:

[0015] A blind hole with a trapezoidal longitudinal cross-section is formed on the first surface of the cover plate.

[0016] The ratio of the depth of the blind hole to the thickness of the cover plate is greater than or equal to a preset ratio, and less than the thickness of the cover plate.

[0017] Optionally, after the second surface of the cover plate is thinned, the thickness of the protective layer at the bottom of the blind hole is greater than or equal to a preset thickness.

[0018] Optionally, thinning the second surface of the cover plate includes:

[0019] The second surface of the cover plate is uniformly thinned at various locations.

[0020] Optionally, after removing the protective layer to convert the blind via into a through via, the method further includes:

[0021] A seed layer is formed within the through hole, wherein the seed layer extends to the surface of the cover plate;

[0022] A conductive plating layer is formed on the surface of the seed layer away from the cover plate, and the stack of the seed layer and the conductive plating layer constitutes a conductive layer.

[0023] Optionally, the conductive layer formed within the through-hole, consisting of a stack of the seed layer and the conductive plating layer, includes:

[0024] A conductive layer with a thickness smaller than the radius of the through hole is formed inside the through hole.

[0025] According to another aspect of this application, a wafer-level packaging method is provided, comprising:

[0026] A substrate is provided, wherein a conductive structure is provided on the surface of the substrate;

[0027] A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface;

[0028] A blind hole is formed on the first surface of the cover plate;

[0029] A protective layer is formed inside the blind hole;

[0030] The first surface side of the cover plate is fixed to the substrate, wherein the orthographic projection of the blind hole on the substrate covers at least a portion of the orthographic projection of the conductive structure on the substrate;

[0031] The second surface of the cover plate is thinned to expose the protective layer at the bottom of the blind hole;

[0032] Remove the protective layer to convert the blind via into a through via;

[0033] A conductive layer is formed within the via, wherein the orthographic projection of the conductive layer onto the substrate covers at least a portion of the orthographic projection of the conductive structure onto the substrate, and is connected to the conductive structure.

[0034] According to another aspect of this application, a wafer-level packaging structure is provided, which is fabricated using any of the wafer-level packaging methods described in this application.

[0035] According to another aspect of this application, a communication device is provided, comprising any of the wafer-level packaging structures described in this application, wherein the communication device includes at least one of a resonator, a filter, and a multiplexer.

[0036] In the technical solution provided in this application, a blind hole is first formed on the first surface of the cover plate. Then, a protective layer is formed inside the blind hole and on the second surface of the cover plate. This protective layer is removed only after the second surface of the cover plate has been thinned. Even if debris falls into the surface of the protective layer, the debris can be removed along with the protective layer. Therefore, whether the second surface of the cover plate is thinned using only a grinding process or by combining grinding and etching processes in two stages, debris falling into the through hole can be avoided, thereby improving the yield of the through hole in the cover plate. Furthermore, when the second surface of the cover plate is thinned in two stages using grinding and etching processes, the protective layer inside the blind hole also prevents the through hole from being enlarged by etching during the thinning process of the second surface of the cover plate. This ensures that the shape of the through hole matches the preset shape (e.g., an inverted trapezoid), thereby improving the yield of the through hole.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figures 1-4 This is a schematic diagram of the structure corresponding to each step of a wafer-level packaging method provided by existing technology;

[0040] Figure 5 This is a flowchart of a wafer-level packaging method provided in this application;

[0041] Figures 6-17 This is a schematic diagram of the structure corresponding to each step of a wafer-level packaging method provided in this application;

[0042] Figure 18 yes Figure 5 The flowchart included in S180;

[0043] Figures 19-21 yes Figure 18 The flowchart shows the structural diagrams corresponding to each step. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or apparatuses is not necessarily limited to those explicitly listed, but may include other steps or apparatuses not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0046] To improve the yield of through holes in the cover plate, the embodiments of this application provide the following technical solutions:

[0047] This application provides a method for forming a through hole, the method comprising the following steps:

[0048] A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface;

[0049] A blind hole is formed on the first surface of the cover plate.

[0050] A protective layer is formed inside the blind hole.

[0051] The second surface of the cover plate is thinned to expose the protective layer at the bottom of the blind hole.

[0052] Remove the protective layer to convert the blind via into a through via.

[0053] In the technical solution provided in this embodiment, a blind hole is first formed on the first surface of the cover plate. Then, a protective layer is formed inside the blind hole and on the second surface of the cover plate. This protective layer is removed only after the second surface of the cover plate has been thinned. Even if debris falls into the surface of the protective layer, the debris can be removed along with the protective layer. Therefore, whether the second surface of the cover plate is thinned using only a grinding process or by combining grinding and etching processes in two stages, debris falling into the through hole can be avoided, thereby improving the yield of the through hole in the cover plate. Furthermore, when the second surface of the cover plate is thinned in two stages using grinding and etching processes, the protective layer inside the blind hole also prevents the through hole from being enlarged by etching during the thinning process of the second surface of the cover plate. This ensures that the shape of the through hole matches the preset shape (e.g., an inverted trapezoid), thereby improving the yield of the through hole.

[0054] It should be noted that the wafer-level packaging structure includes through-holes. In this application, during the process of forming the wafer-level packaging structure using the wafer-level packaging method, the through-holes are formed using any of the through-hole formation methods described in this application. Therefore, in this application, the through-hole formation method is specifically described within the wafer-level packaging method.

[0055] Figure 5 This is a flowchart of a wafer-level packaging method according to this application. See also... Figure 5 The wafer-level packaging method includes the following steps:

[0056] S110, A substrate is provided, wherein a conductive structure is provided on the surface of the substrate.

[0057] See Figure 6 A substrate 001 is provided, and a conductive structure 10 is disposed on the surface of the substrate 001. When the wafer-level packaging method provided in this application is used to fabricate a wafer-level package structure including at least one of a resonator, a filter, and a multiplexer, a resonant unit 11 is further disposed on the surface of the substrate 001. The resonant unit 11 includes a stack of a bottom electrode, a piezoelectric layer, and a top electrode. The conductive structure 10 is connected to the electrode (e.g., the bottom electrode or the top electrode) of the resonant unit 11.

[0058] S120. A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface.

[0059] See Figure 7 A cover plate 002 is provided, the cover plate 002 includes a first surface 2a and a second surface 2b disposed opposite to the first surface 2a.

[0060] S130, A blind hole is formed on the first surface of the cover plate.

[0061] See Figure 8 A first photoresist 003 is formed on the first surface 2a of the cover plate 002, and a photomask with a preset pattern is formed after photolithography. See also Figure 8 and Figure 9 Using the first photoresist 003 as a mask, the cover plate 002 is etched to form a blind hole 20 on the first surface 2a of the cover plate 002. For example, Figure 9 Two blind holes 20 were formed in the middle.

[0062] S140. A protective layer is formed inside the blind hole.

[0063] See Figure 10 A protective layer 004 is formed throughout the blind via 20 and on the second surface 2b of the cover plate 002 using a high-density plasma chemical vapor deposition (HPD CVD) process. Exemplarily, the protective layer 004 can be a film layer such as silicon oxide or silicon nitride. See [link to other documentation] Figure 11 The protective layer 004 on the second surface 2b of the cover plate 002 is removed by chemical mechanical polishing (CMP), leaving only the protective layer 004 located within the blind via 20. It should be noted that, due to the large aspect ratio of the blind via 20 in this application, a high-density plasma chemical vapor deposition process is employed, which includes a deposition-etching-deposition cycle. This reduces the number of breaks and voids within the protective layer 004, thereby improving the yield of the protective layer 004, enhancing its protective effect on the blind via 20, and ultimately improving the yield of the through-hole 200.

[0064] S150. The first surface side of the cover plate is fixed to the substrate, wherein the orthographic projection of the blind hole onto the substrate covers at least a portion of the orthographic projection of the conductive structure onto the substrate.

[0065] See Figure 12 The first surface 2a of the cover plate 002 can be fixed to the substrate 001 by a bonding process, wherein the orthographic projection of the blind via 20 onto the substrate 001 covers part or all of the orthographic projection of the conductive structure 10 onto the substrate 001. Further, see... Figure 13 Before fixing the first surface 2a side of the cover plate 002 onto the substrate 001, a second connection structure 21 and a third connection structure 22 for bonding can be formed on the first surface 2a of the cover plate 002. See also Figure 12The second connection structure 21 and the first connection structure 12 are bonded together; the third connection structure 22 is bonded together with the conductive structure 10; wherein the second connection structure 21 and the first connection structure 12 are located outside the conductive structure 10 and are bonded together, which can realize the sealed connection between the substrate 001 and the cover plate 002, which helps to reduce the energy loss of at least one of the resonators, filters and multiplexers, thereby improving product performance.

[0066] S160. The second surface of the cover plate is thinned to expose the protective layer at the bottom of the blind hole.

[0067] See Figure 14 The second surface 2b of the cover plate 002 can be thinned using a grinding process to improve the efficiency of the thinning process. See [link / reference] Figure 15 The second surface 2b of the cover plate 002 is further thinned by etching, and the thinning thickness can be precisely controlled to expose the protective layer 004 at the bottom of the blind hole 20. Preferably, the thinning can be directly performed on the second surface 2b of the cover plate 002 until the protective layer 004 is fully exposed.

[0068] S170. Remove the protective layer to convert the blind via into a through via.

[0069] See Figure 16 The protective layer 004 can be removed by a wet etching process, so that the blind via 20 can be converted into a through via 200. In the above wafer-level packaging method, both the substrate 001 and the cover plate 002 are illustrated using a silicon wafer as an example. The blind via 20 is a blind via on the silicon wafer, and the through via 200 is a silicon through-hole.

[0070] S180. A conductive layer is formed inside the through hole, wherein the conductive layer is connected to the conductive structure.

[0071] See Figure 17 A conductive layer 005 is formed within the via 200. The orthogonal projection of the conductive layer 005 onto the substrate 001 covers the orthogonal projection of the conductive structure 10 onto the substrate, and the conductive layer 005 is connected to the conductive structure 10. The conductive layer 005 is used to extract the electrical signals of the conductive structure 10 on the substrate 001. It can be understood that, in other embodiments, the orthogonal projection of the conductive layer 005 onto the substrate 001 may also completely cover the orthogonal projection of the conductive structure 10 onto the substrate.

[0072] In the technical solution provided in this embodiment, a blind hole 20 is first formed on the first surface 2a of the cover plate 002. Then, a protective layer 004 is formed in the blind hole 20 and on the second surface 2b of the cover plate 002. The protective layer 004 is removed after the second surface 2b of the cover plate 002 is thinned. Even if debris falls into the surface of the protective layer 004, the debris can be removed along with the protective layer 004. Therefore, whether the second surface 2b of the cover plate 002 is thinned by grinding alone, or the second surface 2b of the cover plate 002 is thinned in two steps by grinding and etching, debris can be prevented from falling into the through hole 200, thereby improving the yield of the through hole 200 in the cover plate 002. Furthermore, when the second surface 2b of the cover plate 002 is thinned in two stages through grinding and etching processes, the protective layer 004 inside the blind hole 20 can prevent the through hole 200 from being etched and enlarged during the thinning process of the second surface 2b of the cover plate 002 through etching. This allows the shape of the through hole 200 to match the preset shape (e.g., inverted trapezoid), thereby improving the yield of the through hole 200.

[0073] Optionally, the step of forming a blind hole on the first surface of the cover plate in S130 includes: forming a blind hole with a trapezoidal longitudinal cross-sectional shape on the first surface of the cover plate. Specifically, see... Figure 9 A blind hole 20 with a trapezoidal longitudinal cross-section is formed on the first surface 2a of the cover plate 002, meaning that the diameter of the blind hole 20 near the first surface 2a is smaller than its diameter away from the first surface 2a. Optionally, see... Figure 9 The ratio of the depth of the blind hole 20 to the thickness of the cover plate 002 is greater than or equal to a preset ratio, and the depth of the blind hole 20 is less than the thickness of the cover plate 002.

[0074] because Figure 9 In the middle, the longitudinal section of blind hole 20 is a regular trapezoid, see [reference]. Figure 12 When the first surface 2a of the cover plate 002 is fixed to the substrate 001 via a bonding process, the longitudinal cross-sectional shape of the blind via 20 is an inverted trapezoid, meaning the diameter of the blind via 20 near the substrate 001 is smaller than its diameter away from the substrate 001. See [link to documentation]. Figure 16 and Figure 17The protective layer 004 can be removed using a wet etching process, converting the blind via 20 into a through via 200. The longitudinal cross-sectional shape of the through via 200 is an inverted trapezoid, meaning the diameter of the through via 200 near the substrate 001 is smaller than its diameter away from the substrate 001. This reduces the difficulty of forming the conductive layer 005 within the through via 200. If the longitudinal cross-sectional shape of the through via 200 is a regular trapezoid or rectangle, meaning the diameter of the through via 200 near the substrate 001 is larger than its diameter away from the substrate 001, then when forming the conductive layer 005 within the through via 200, the material of the conductive layer 005 will not easily enter the through via 200, thus increasing the difficulty of forming the conductive layer 005 within the through via 200. Understandably, the size and depth of the blind hole 20 (i.e., through hole 200) on the cover plate 002 are related to the product design; the depth of the through hole 200 determines the remaining thickness of the cover plate 002 after thinning. If the cover plate 002 is too thin, it is easy to crack. The specific thickness of the cover plate 002 can be set at around 100 micrometers. Preferably, the specific thickness of the cover plate 002 is greater than or equal to 10 micrometers.

[0075] Optionally, see Figure 15 After the second surface 2b of the cover plate 002 is thinned, the thickness of the protective layer 004 at the bottom of the blind hole 20 is greater than or equal to the preset thickness.

[0076] Furthermore, the preset thickness can be 1 micrometer, meaning that after thinning the second surface 2b of the cover plate 002, the thickness of the protective layer 004 at the bottom of the blind hole 20 is greater than or equal to 1 micrometer. Understandably, the relatively large thickness of the protective layer 004 at the bottom of the blind hole 20, exceeding or equal to the preset thickness, ensures that the entire protective layer 004 is not removed during the thinning process of the second surface 2b of the cover plate 002. This prevents debris from falling into the through hole 200, thus improving the yield of the through hole 200 within the cover plate 002. Furthermore, it avoids the through hole 200 being enlarged by etching during the thinning process of the second surface 2b of the cover plate 002, ensuring that the shape of the through hole 200 matches the preset shape and further improving the yield of the through hole 200 within the cover plate 002.

[0077] Optionally, the step of thinning the second surface of the cover plate in S160 includes: uniformly thinning the second surface of the cover plate at various locations.

[0078] See Figure 15 The second surface 2b of the cover plate 002 is uniformly thinned at various positions, which improves the surface flatness of the second surface 2b of the cover plate 002 after thinning.

[0079] Optionally, the step of thinning the second surface of the cover plate in S160 includes: see Figure 15The second surface 2b of the cover plate 002 was thinned multiple times.

[0080] Understandably, as the number of times the second surface 2b of the cover plate 002 is thinned increases, the thickness of the second surface 2b of the cover plate 002 in a single thinning process does not need to be too thick, thereby improving the accuracy of the single thinning process of the second surface 2b of the cover plate 002, and thus improving the accuracy of the entire thinning process for the second surface 2b of the cover plate 002.

[0081] Optionally, see Figure 17 The conductive layer 005 comprises a stack of a seed layer 50 and a conductive plating layer 51, see [link to documentation]. Figure 18 The step of forming a conductive layer inside the via in S180 includes:

[0082] S1801. A seed layer is formed in the through hole, wherein the seed layer extends to the surface of the cover plate.

[0083] See Figure 19 A seed layer 50 is formed within the via 200 using a sputtering process, wherein the seed layer 50 extends to the surface of the cover plate 002. The longitudinal cross-sectional shape of the via 200 is an inverted trapezoid, which reduces the difficulty of forming the seed layer 50 within the via 200. For example, the thickness of the seed layer 50 is greater than or equal to 500 angstroms. For example, the material of the seed layer 50 includes copper or titanium copper.

[0084] S1802, A conductive plating layer is formed on the surface of the seed layer away from the cover plate.

[0085] See Figure 20 A photomask composed of a second photoresist 006 is formed on the surface of the seed layer 50 facing away from the cover plate 002. Then, see... Figure 21 A conductive plating layer 51 is formed by electroplating, covering the photomask and seed layer 50. Then, see... Figure 17 The second photoresist 006 and the conductive plating layer 51 thereon are removed by a stripping process, and the seed layer 50 is patterned to form a conductive layer 005 with a preset pattern. For example, the conductive plating layer 51 includes a copper conductive plating layer.

[0086] Optionally, the step of forming a conductive layer in the via in S180 includes: forming a conductive layer in the via with a thickness less than the radius of the via, wherein the thickness of the conductive layer is the thickness in the direction perpendicular to the depth of the via.

[0087] See Figure 17A conductive layer 005 with a thickness less than the radius of the through hole 200 is formed inside the through hole 200. The thickness of the conductive layer 005 is the thickness of the conductive layer 005 in the direction perpendicular to the depth of the through hole 200. Since the inner diameter of the through hole 200 is small and the depth is large, if the thickness of the conductive layer 005 is too thick, to the point that it is equal to the radius of the through hole 200, the conductive layer 005 will fill the through hole 200. When the ambient temperature changes, due to the difference in the coefficients of thermal expansion of the conductive layer 005 and the cover plate 002, the deformation of the two will differ, which will lead to a decrease in the adhesion between the through hole 200 and the conductive layer 005, thereby reducing the yield of the conductive through hole formed by the through hole 200 and the conductive layer 005. Therefore, the thickness of the conductive layer 005 is limited to prevent product defects.

[0088] Optionally, in this application, references Figure 21 Furthermore, a groove 23 can be formed on the first surface 2a of the cover plate 002. The orthogonal projection of the groove 23 onto the substrate 001 covers the orthogonal projection of the resonant unit 11 onto the substrate 001, which can reduce the energy loss of communication devices including at least one of resonators, filters and multiplexers, thereby improving product performance.

[0089] This application also provides a wafer-level packaging structure, fabricated using any of the wafer-level packaging methods described in this application. Therefore, the wafer-level packaging structure provided by this application also possesses the beneficial effects described in any of the aforementioned wafer-level packaging methods, which will not be elaborated upon here.

[0090] This application also provides a communication device comprising any of the wafer-level packaging structures described in this application. The communication device includes at least one of a resonator, a filter, and a multiplexer. Therefore, the communication device provided in this application also possesses the beneficial effects described in the above-described wafer-level packaging structures, which will not be repeated here.

[0091] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for forming a through hole, characterized in that, include: A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface; A blind hole with a trapezoidal longitudinal cross-sectional shape is formed on the first surface of the cover plate; Forming a protective layer within the blind hole includes: forming a full-layer protective layer within the blind hole and on the first surface of the cover plate; removing the protective layer from the first surface of the cover plate, leaving only the protective layer located within the blind hole; The second surface of the cover plate is thinned, and the thinning thickness is precisely controlled to expose the protective layer at the bottom of the blind hole; Remove the protective layer to convert the blind hole into a through hole.

2. The method for forming a through hole according to claim 1, characterized in that, The ratio of the depth of the blind hole to the thickness of the cover plate is greater than or equal to a preset ratio, and less than the thickness of the cover plate.

3. The method for forming a through hole according to claim 1, characterized in that, After the second surface of the cover plate is thinned, the thickness of the protective layer at the bottom of the blind hole is greater than or equal to the preset thickness.

4. The method for forming a through hole according to claim 1 or 3, characterized in that, The thinning process for the second surface of the cover plate includes: The second surface of the cover plate is uniformly thinned at various locations.

5. The method for forming a through hole according to claim 1, characterized in that, After removing the protective layer to convert the blind via into a through via, the process further includes: A seed layer is formed within the through hole, wherein the seed layer extends to the surface of the cover plate; A conductive plating layer is formed on the surface of the seed layer away from the cover plate, and the stack of the seed layer and the conductive plating layer constitutes a conductive layer.

6. The method for forming a through hole according to claim 5, characterized in that, The conductive layer formed within the through-hole, consisting of a stack of the seed layer and the conductive plating layer, comprises: A conductive layer with a thickness smaller than the radius of the through hole is formed inside the through hole.

7. A wafer-level packaging method, characterized in that, include: A substrate is provided, wherein a conductive structure is provided on the surface of the substrate; A cover plate is provided, wherein the cover plate includes a first surface and a second surface disposed opposite to the first surface; A blind hole with a trapezoidal longitudinal cross-sectional shape is formed on the first surface of the cover plate; Forming a protective layer within the blind hole includes: forming a full-layer protective layer within the blind hole and on the first surface of the cover plate; removing the protective layer from the first surface of the cover plate, leaving only the protective layer located within the blind hole; The first surface side of the cover plate is fixed to the substrate, wherein the orthographic projection of the blind hole on the substrate covers at least a portion of the orthographic projection of the conductive structure on the substrate; The second surface of the cover plate is thinned, and the thinning thickness is precisely controlled to expose the protective layer at the bottom of the blind hole; Remove the protective layer to convert the blind via into a through via; A conductive layer is formed within the through-hole, wherein the conductive layer is connected to the conductive structure.

8. A wafer-level packaging structure, characterized in that, It is prepared using the wafer-level packaging method described in claim 7.

9. A communication device, characterized in that, The communication device includes at least one of a resonator, a filter, and a multiplexer, comprising the wafer-level packaging structure of claim 8.

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