Memory device and method of manufacturing the same

Abstract

The present invention discloses a memory device and a method for manufacturing the same. The memory device includes a substrate, a plurality of trenches, an oxide semiconductor layer, a gate dielectric layer, and a plurality of word line structures. The substrate includes a plurality of active regions and an isolation structure located between the active regions, and the active regions contain silicon. A plurality of trenches are arranged in the active regions and the isolation structures. The oxide semiconductor layer is conformally arranged in each trench, and the gate dielectric layer is arranged on the oxide semiconductor layer and located in each trench. A plurality of word line structures are arranged on the gate dielectric layer and are respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is arranged between the oxide semiconductor layer and each word line structure. The method for manufacturing the memory device includes forming a plurality of trenches, conformally forming an oxide semiconductor layer in each trench, forming a gate dielectric layer on the oxide semiconductor layer, and forming a plurality of word line structures on the gate dielectric layer. In this way, the effect of improving the operating performance of the memory device can be achieved.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and in particular to a memory device comprising an oxide semiconductor layer and a method for manufacturing the same. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array area consisting of multiple memory cells and a peripheral area consisting of control circuits. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] To reduce the size of memory cells and create chips with higher density, memory cell structures have been moving towards three-dimensional (3D) designs, such as the use of buried word lines and stacked capacitors. However, in this context, improving device performance through new structural and / or manufacturing process designs remains a constant goal for the industry. Summary of the Invention

[0004] The present invention provides a memory device and a manufacturing method thereof, which achieves the effect of improving the operation performance of the memory device by arranging an oxide semiconductor layer in a groove.

[0005] One embodiment of the present invention provides a memory device comprising a substrate, a plurality of trenches, an oxide semiconductor layer, a gate dielectric layer, and a plurality of word line structures. The substrate comprises a plurality of active regions and an isolation structure, wherein the isolation structure is located between the plurality of active regions, and the plurality of active regions contain silicon. The plurality of trenches are disposed in the plurality of active regions and the isolation structures. The oxide semiconductor layer is conformally disposed in each of the trenches, and the gate dielectric layer is disposed on the oxide semiconductor layer and in each of the trenches. The plurality of word line structures are disposed on the gate dielectric layer and are respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures.

[0006] One embodiment of the present invention provides a method for manufacturing a memory device, comprising the following steps. A substrate is provided, the substrate comprising a plurality of active regions and an isolation structure. The isolation structure is located between the plurality of active regions, and the plurality of active regions contain silicon. A plurality of trenches are formed in the plurality of active regions and the isolation structure, an oxide semiconductor layer is conformally formed in each of the trenches, and a gate dielectric layer is formed on the oxide semiconductor layer. The gate dielectric layer is located in each of the trenches. A plurality of word line structures are formed on the gate dielectric layer, wherein the plurality of word line structures are respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into and become a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for illustrative and drawing convenience. The same symbols in different embodiments represent corresponding or similar features.

[0008] Figure 1 、 Figure 2 、 Figure 3 and Figure 4 FIG. 1 is a schematic diagram of a method for manufacturing a memory device according to an embodiment of the present invention, wherein Figure 1 A top-down schematic diagram is shown. Figure 2 for Figure 1 Schematic diagram of the situation afterwards, Figure 3 for Figure 2 The following diagram shows the situation: Figure 4 for Figure 3 Schematic diagram of the situation afterwards.

[0009] Figure 5 FIG. 1 is a schematic cross-sectional view of a memory device according to an embodiment of the present invention.

[0010] Figure 6 FIG. 1 is a schematic top view of a memory device according to an embodiment of the present invention.

[0011] The description of the accompanying drawings is as follows:

[0012] 10 bases

[0013] 10B bottom surface

[0014] 10T upper surface

[0015] 12 Isolation Structure

[0016] 20Oxide semiconductor layer

[0017] 22 gate dielectric layer

[0018] 24 work function layers

[0019] 26 conductive layer

[0020] 28 cap layer

[0021] 32 mask layers

[0022] 34 mask layers

[0023] 36 mask layers

[0024] 38 conductive layer

[0025] 42 dielectric layer

[0026] 44 dielectric layer

[0027] 50 storage node contact structure

[0028] 52-bit line contact structure

[0029] 54 silicide layer

[0030] 56 barrier layer

[0031] 58 conductive layer

[0032] 62 barrier layer

[0033] 64 conductive layers

[0034] 66 cap layer

[0035] 91 First Film Forming Process

[0036] 92 Second film forming process

[0037] 101 Storage Devices

[0038] AA active area

[0039] BL bit line structure

[0040] D1 direction

[0041] D2 direction

[0042] D3 direction

[0043] D4 direction

[0044] DP1 Depth

[0045] DP1' depth

[0046] DP2 Depth

[0047] DP2' depth

[0048] L1 length

[0049] L2 length

[0050] SP1 interstitial

[0051] SP2 interstitial

[0052] SS1 section

[0053] SS2 section

[0054] SS3 section

[0055] TK1 thickness

[0056] TK2 thickness

[0057] TR groove

[0058] TR1 Part 1

[0059] TR2 Part 2

[0060] WL word line structure DETAILED DESCRIPTION

[0061] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with accompanying diagrams, to provide a detailed description of the technical solutions and intended effects of the present invention. Those skilled in the art can, without departing from the spirit of the present invention, refer to the following embodiments and replace, reorganize, or combine the features of the various embodiments to create other embodiments.

[0062] See also Figure 1 、 Figure 2 、 Figure 3 and Figure 4 . Figure 1 、 Figure 2 、 Figure 3 and Figure 4 FIG. 1 is a schematic diagram of a method for manufacturing a memory device according to an embodiment of the present invention, wherein Figure 1 A top-down schematic diagram is shown. Figure 2 for Figure 1 Schematic diagram of the situation afterwards, Figure 3 for Figure 2 The following diagram shows the situation: Figure 4 for Figure 3 In some embodiments, Figure 2 Can be considered as Figure 1 The manufacturing method of this embodiment may include the following steps. Figure 4As shown, a substrate 10 is provided. The substrate 10 includes a plurality of active areas AA and an isolation structure 12, with the isolation structure 12 located between the plurality of active areas AA. A plurality of trenches TR are formed in the plurality of active areas AA and the isolation structure 12, and an oxide semiconductor layer 20 is conformally formed in each trench TR. A gate dielectric layer 22 is formed on the oxide semiconductor layer 20, and the gate dielectric layer 22 is located in each trench TR. A plurality of word line structures WL are formed on the gate dielectric layer 22, wherein the plurality of word line structures WL are respectively located in the plurality of trenches TR, and at least a portion of the gate dielectric layer 22 is disposed between the oxide semiconductor layer 20 and each word line structure WL.

[0063] To further illustrate, the manufacturing method of this embodiment may include but is not limited to the following steps. Figure 1 and Figure 2 As shown, in some embodiments, the substrate 10 may include a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. Before forming the aforementioned trenches TR, an isolation structure 12 may be formed in the substrate 10. The isolation structure 12 may be used to define a plurality of mutually separated active areas AA in the substrate 10. For example, when the substrate 10 is a substrate containing silicon, each active area AA may contain silicon. When silicon is the primary component of the substrate 10, silicon may also be the primary component of each active area AA. The isolation structure 12 may include a single layer or multiple layers of insulating material, such as silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials. In some embodiments, the isolation structure 12 may be considered shallow trench isolation (STI), but is not limited thereto. Furthermore, the aforementioned trenches TR may be formed in the substrate 10 after the isolation structure 12 is formed, and each trench TR may be staggered with one or more active areas AA. For example, each active area AA may be arranged along a horizontal direction (eg Figure 1 The trenches TR may extend in another horizontal direction (eg, Figure 1 The direction D2 and the direction D3 may extend in the direction D3 shown in FIG. 1 , and the ...3 may extend in the direction D3 shown in FIG. Figure 1 In some embodiments, each active area AA may be staggered with two trenches TR, and the two trenches TR divide each active area AA into three sections (e.g. Figure 2In other words, a portion of the substrate 10 (e.g., the segments SS1, SS2, and SS3 of the active area AA) may be disposed between two adjacent trenches TR and may be sandwiched between the two adjacent trenches TR in the horizontal direction (e.g., direction D2).

[0064] In some embodiments, the aforementioned direction D1 can be considered as the thickness direction of the substrate 10. The substrate 10 may have an upper surface 10T and a bottom surface 10B opposite to each other in the direction D1. Each trench TR may extend from the upper surface 10T of the substrate 10 toward the bottom surface 10B along the direction D1 without penetrating the substrate 10. Horizontal directions substantially perpendicular to the direction D1 (e.g., direction D2, direction D3, and other directions perpendicular to the direction D1) may be substantially parallel to the upper surface 10T and / or the bottom surface 10B of the substrate 10, but are not limited thereto. In this article, a relatively high position in the direction D1 and / or the distance between a component and the bottom surface 10B of the substrate 10 in the direction D1 may be greater than a relatively low position in the direction D1 and / or the distance between a component and the bottom surface 10B of the substrate 10 in the direction D1; the lower part or bottom of each component may be closer to the bottom surface 10B of the substrate 10 in the direction D1 than the upper part or top of this component; another component above a certain component may be regarded as relatively far away from the bottom surface 10B of the substrate 10 in the direction D1, and another component below a certain component may be regarded as relatively close to the bottom surface 10B of the substrate 10 in the direction D1.

[0065] In some embodiments, the trenches TR extending along direction D3 may partially overlap with multiple active areas AA. Therefore, each trench TR may include a first portion TR1 disposed in the active area AA and a second portion TR2 disposed in the isolation structure 12. Furthermore, the trenches TR may be formed by etching the substrate 10 and the isolation structure 12. Due to the difference in etching rates between the materials of the substrate 10 and the isolation structure 12 during the etching process, the depth of the trenches TR in the active area AA may differ from the depth of the trenches TR in the isolation structure 12. For example, the depth DP1 of the first portion TR1 may be less than the depth DP2 of the second portion TR2, but this is not limiting. Furthermore, the depth of the trenches TR may be considered the distance in direction D1 between the bottommost portion of the trench TR and the upper surface 10T of the substrate 10.

[0066] like Figure 2As shown, after the trench TR is formed, an oxide semiconductor layer 20 may be formed by a first film formation process 91. The oxide semiconductor layer 20 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin gallium zinc oxide (ITGZO), or other oxides having semiconductor properties, but is not limited thereto.

[0067] The oxide semiconductor layer 20 may be conformally formed on the surface of each trench TR, the upper surface 10T of the substrate 10, and the upper surface of the isolation structure 12. In other words, the oxide semiconductor layer 20 does not fill each trench TR, and the thickness of the oxide semiconductor layer 20 may be less than the depth of each trench TR. For example, the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., Figure 2 The thickness TK1 of the oxide semiconductor layer 20 in the first portion TR1 in the direction D1 and the thickness TK2 of the oxide semiconductor layer 20 in the second portion TR2 in the direction D1 shown in FIG. 9 may be less than the depth of each trench TR in the direction D1 (e.g., the depth DP1 and the depth DP2 described above). In some embodiments, the first film formation process 91 may include an atomic layer deposition (ALD) process or other suitable film formation method to ensure that the oxide semiconductor layer 20 is conformally formed on the surface of each trench TR and reduce the formation of voids between the oxide semiconductor layer 20 and the substrate 10. In addition, since each trench TR may include a first portion TR1 disposed in the active area AA and a second portion TR2 disposed in the isolation structure 12, and the oxide semiconductor layer 20 may be formed in the first portion TR1 and the second portion TR2 of the trench TR, a portion of the oxide semiconductor layer 20 may also be considered to be disposed in the isolation structure 12.

[0068] like Figure 2 and Figure 3 As shown, after the oxide semiconductor layer 20 is formed, a gate dielectric layer 22 may be formed by a second film forming process 92. The gate dielectric layer 22 may include a high dielectric constant (high-k) dielectric material or other suitable dielectric materials. The high-k dielectric material may include hafnium oxide (HfO X), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2) or other suitable high dielectric constant materials. The gate dielectric layer 22 can be conformally formed on the oxide semiconductor layer 20. In other words, the gate dielectric layer 22 does not fill each trench TR, so the thickness of the gate dielectric layer 22 can also be less than the depth of each trench TR. In some embodiments, the second film forming process 92 may include an atomic layer deposition process or other suitable film forming method to ensure that the gate dielectric layer 22 can be conformally formed on the oxide semiconductor layer 20 located in each trench TR. Furthermore, in some embodiments, the first film forming process 91 and the second film forming process 92 can be performed sequentially in the same process chamber to reduce the negative impact of the external environment and / or simplify the process. In some embodiments, a gate dielectric layer 22 having a higher dielectric constant and / or a smaller equivalent oxide thickness (EOT) can also be used to improve leakage of a corresponding semiconductor structure (e.g., a transistor structure), but the present invention is not limited thereto.

[0069] Then, if Figure 4 As shown, a plurality of word line structures WL may be formed in a substrate 10, and a storage node contact structure 50, a bit line contact structure 52, and a bit line structure BL may be formed on the substrate 10. Each word line structure WL is formed in a corresponding trench TR and on the gate dielectric layer 22 in the trench TR. In some embodiments, each word line structure WL may include a work function layer 24, a conductive layer 26, and a capping layer 28, but is not limited thereto. The work function layer 24 may include titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium aluminide, titanium aluminum nitride, or other suitable conductive work function materials. The conductive layer 26 may include tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable conductive materials with relatively low resistivity. The capping layer 28 may include silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials. In some embodiments, after the word line structure WL is formed, the oxide semiconductor layer 20, the gate dielectric layer 22 and / or other materials outside the trenches TR may be removed by a suitable process (e.g., chemical mechanical polishing process, but not limited thereto). After this process, the depth of each trench TR (e.g., Figure 4The depths DP1′ and DP2′ shown in FIG may be regarded as the distance between the bottom of each trench TR and the upper surface of the word line structure WL (eg, the upper surface of the cap layer 28 ) in the direction D1 , but are not limited thereto.

[0070] The wordline structure WL located in each trench TR may extend along a direction D1 and be surrounded by the gate dielectric layer 22 and the oxide semiconductor layer 20. In some embodiments, the length of each wordline structure WL in the direction D1 is affected by the depth of the trench TR. For example, the length L1 of the wordline structure WL located in the first portion TR1 of the trench TR in the direction D1 may be less than the length L2 of the wordline structure WL located in the second portion TR2 of the trench TR in the direction D1, but the present invention is not limited thereto. Furthermore, the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., thickness TK1 and thickness TK2) may be less than the depth of each trench TR in the direction D1 (e.g., depth DP1' and depth DP2'). Furthermore, the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., thickness TK1 and thickness TK2) may be less than the thickness of each wordline structure WL in the direction D1 (e.g., length L1 and length L2). This increases the overlap area between the wordline structure WL and the oxide semiconductor layer 20, thereby improving the operating performance of the corresponding transistor structure. In addition, the depth of each trench TR in the direction D1 may also be greater than the width of each trench TR in the horizontal direction (for example, the width in the direction D2 and / or the width in the horizontal direction). Figure 1 The width in the direction D4 shown in FIG), thereby cooperating with the oxide semiconductor layer 20 conformally formed in the trench TR to achieve the effect of increasing the overlapping area between the word line structure WL and the oxide semiconductor layer 20.

[0071] In some embodiments, the aforementioned segments SS1, SS2, and SS3 can also be considered as three segments of a plurality of word line structures WL spanning a plurality of active areas AA, dividing each active area AA into three segments. The bit line structure BL can be formed on segment SS1, and the two storage node contact structures 50 can be formed on segments SS2 and SS3, respectively, but this is not limiting. The storage node contact structures 50 may comprise silicon, such as amorphous silicon, polycrystalline silicon, other silicon-containing conductive materials, or other types of conductive materials. In some embodiments, the bit line structure BL may comprise a barrier layer 62, a conductive layer 64, and a capping layer 66, and the bit line structure BL may be electrically connected to the active area AA via the bit line contact structures 52. The bitline contact structure 52 may comprise a metal conductive material or a non-metallic conductive material, such as polysilicon, amorphous silicon, or other silicon-containing non-metallic conductive materials. The barrier layer 62 may comprise titanium, titanium nitride, tungsten nitride, or other suitable conductive barrier materials. The conductive layer 64 may comprise aluminum, tungsten, copper, a titanium-aluminum alloy, or other suitable low-resistance metal conductive materials. The cap layer 66 may comprise silicon nitride, silicon oxide, or other suitable insulating materials. In some embodiments, mask layers 32 and 34, and a dielectric layer 42 may be disposed between adjacent storage node contact structures 50 and / or between the storage node contact structures 50 and the bitline structure BL. Spacers SP1 and SP2 may be disposed on the sidewalls of the bitline structure BL. A dielectric layer 44, a silicide layer 54, a barrier layer 56, and a conductive layer 58 may be disposed on each storage node contact structure 50, but the present invention is not limited thereto. Mask layers 32 and 34 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials. Dielectric layers 42 and 44 may comprise nitride dielectric materials or other suitable dielectric materials. Silicide layer 54 may comprise a conductive metal silicide material. Barrier layer 56 may comprise titanium, titanium nitride, tungsten nitride, or other suitable conductive barrier materials. Conductive layer 58 may comprise aluminum, tungsten, copper, a titanium-aluminum alloy, or other suitable low-resistance metal conductive materials. Spacers SP1 and SP2 may each comprise a single layer or a stack of multiple layers of insulating material. In some embodiments, a capacitor structure (not shown) may be disposed above conductive layer 58, and the capacitor structure may be electrically connected to storage node contact structure 50 through conductive layer 58 and silicide layer 54, but the present invention is not limited thereto.

[0072] In some embodiments, the storage node contact structure 50 may be directly connected to the substrate 10. In some embodiments, the storage node contact structure 50 may be directly connected to one of the multiple active areas AA in the substrate 10 and the oxide semiconductor layer 20. A portion of the oxide semiconductor layer 20 may be horizontally sandwiched between the gate dielectric layer 22 and the storage node contact structure 50, but this is not limited to this. In some embodiments, a portion of the wordline structure WL may be considered the gate of a transistor structure, the storage node contact structure 50 and the bitline contact structure 52 may be considered the source and drain of this transistor structure, and a portion of the oxide semiconductor layer 20 and / or the active area AA may form the semiconductor channel region of this transistor structure, but this is not limited to this. By conformally forming the oxide semiconductor layer 20 in the trench TR and utilizing the material properties of the oxide semiconductor layer 20, the on-state current (Ion) of the transistor structure may be increased, the off-state current (Ioff) may be reduced, the write recovery time (tWR) of the memory device may be shortened, the refresh frequency of the memory device may be increased, and / or the operating power consumption of the memory device may be improved.

[0073] By the above-mentioned manufacturing method, the following can be formed: Figure 4 The memory device 101 is shown. Figure 4 As shown, the memory device 101 includes a substrate 10, a plurality of trenches TR, an oxide semiconductor layer 20, a gate dielectric layer 22, and a plurality of word line structures WL. The substrate 10 includes a plurality of active areas AA and an isolation structure 12, and the isolation structure 12 is located between the plurality of active areas AA. The plurality of trenches TR are disposed in the plurality of active areas AA and the isolation structure 12, the oxide semiconductor layer 20 is conformally disposed in each trench TR, and the gate dielectric layer 22 is disposed on the oxide semiconductor layer 20 and in each trench TR. The plurality of word line structures WL are disposed on the gate dielectric layer 22 and are respectively located in the plurality of trenches TR, and at least a portion of the gate dielectric layer 22 is disposed between the oxide semiconductor layer 20 and each word line structure WL.

[0074] See also Figure 4 、 Figure 5 and Figure 6 . Figure 5 FIG1 is a schematic cross-sectional view of a memory device according to an embodiment of the present invention. Figure 6 FIG. 1 is a schematic top view of a memory device according to an embodiment of the present invention. Figure 6 It mainly shows the layout of the active area AA, trench TR, word line structure WL and bit line structure BL. Figure 4 Can be considered as Figure 6 The cross-sectional view is shown along the BB' line. Figure 5 It can be regarded as a cross-sectional view along another horizontal direction, but is not limited thereto. Figure 4 、 Figure 5 and Figure 6 As shown, the memory device 101 may further include a plurality of storage node contact structures 50, a plurality of bit line contact structures 52, and a plurality of bit line structures BL. The word line structure WL is disposed on the substrate 10 and is electrically connected to the active area AA through the bit line contact structure 52. The plurality of word line structures WL may respectively extend along a direction D3 across the plurality of active areas AA and divide each active area AA into three sections (e.g., the above-mentioned section SS1, section SS2, and section SS3). Each bit line structure BL may respectively extend along a horizontal direction (e.g., direction D4) across the plurality of active areas AA and the plurality of trenches TR. The storage node contact structure 50 is disposed on the substrate 10, and the storage node contact structure 50 is directly connected to the substrate 10. In some embodiments, the storage node contact structure 50 may be directly connected to the active area AA and the oxide semiconductor layer 20 in the substrate 10.

[0075] In some embodiments, the gate dielectric layer 22 may be conformally disposed on the oxide semiconductor layer 20. The word line structure WL located in each trench TR may be surrounded by the gate dielectric layer 22 and the oxide semiconductor layer 20. The oxide semiconductor layer 20, the gate dielectric layer 22, and the work function layer may each have a U-shaped structure or a V-shaped structure in a cross-sectional view of the memory device 101, but are not limited thereto. In some embodiments, the memory device 101 may further include a mask layer 36 disposed between the bit line structure BL and the mask layer 34, and the bit line structure BL may further include a conductive layer 38 disposed between the mask layer 36 and the barrier layer 62. The conductive layer 38 may include a metallic conductive material or a non-metallic conductive material such as polysilicon, amorphous silicon, or other non-metallic conductive materials containing silicon, and the mask layer 36 may include silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials. In some embodiments, the bit line contact structure 52 may penetrate the conductive layer 38 , the mask layer 36 , the mask layer 34 , and the mask layer 32 to be directly connected to the active area AA, the oxide semiconductor layer 20 , and the gate dielectric layer 22 , but the present invention is not limited thereto.

[0076] In summary, in the memory device and its manufacturing method of the present invention, an oxide semiconductor layer can be disposed in the trench to improve the memory device's operating performance. Furthermore, the oxide semiconductor layer can be conformally formed on the surface of the trench and surrounding the wordline structure to increase the overlap area between the wordline structure and the oxide semiconductor layer, thereby improving the operating performance of the corresponding semiconductor structure.

[0077] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A memory device, characterized in that: include: A substrate comprising: multiple active regions; and an isolation structure located between the plurality of active regions, wherein the plurality of active regions contain silicon; A plurality of trenches are provided in the plurality of active regions and the isolation structure; each of the trenches is staggered with one or more active regions; an oxide semiconductor layer conformally disposed in each of the trenches; a gate dielectric layer disposed on the oxide semiconductor layer and located in each of the trenches; and a plurality of word line structures disposed on the gate dielectric layer and respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures; a storage node contact structure disposed on the substrate, wherein the storage node contact structure is directly connected to one of the plurality of active regions; The storage node contact structure is also directly connected to the oxide semiconductor layer.

2. The memory device according to claim 1, wherein: The thickness of the oxide semiconductor layer in a vertical direction is smaller than the depth of each trench in the vertical direction.

3. The memory device according to claim 1, wherein: The thickness of the oxide semiconductor layer in a vertical direction is smaller than the length of each word line structure in the vertical direction.

4. The memory device according to claim 1, wherein: A portion of the substrate is disposed between two adjacent grooves.

5. The memory device according to claim 1, wherein The oxide semiconductor layer has a U-shaped structure in a cross-sectional view of the memory device.

6. The memory device according to claim 1, wherein: The gate dielectric layer is conformally disposed on the oxide semiconductor layer.

7. The memory device according to claim 1, wherein: The word line structures cross the active regions and divide each active region into three sections.

8. The memory device according to claim 1, wherein: The method further includes a mask layer, wherein the mask layer is located on the word line structure and is in direct contact with the oxide semiconductor layer and the gate dielectric layer.

9. A method for manufacturing a memory device, characterized in that: include: A substrate is provided, comprising: multiple active regions; and an isolation structure located between the plurality of active regions, wherein the plurality of active regions contain silicon; forming a plurality of trenches in the plurality of active regions and the isolation structure; conformally forming an oxide semiconductor layer in each of the trenches; forming a gate dielectric layer on the oxide semiconductor layer, wherein the gate dielectric layer is located in each of the trenches; and forming a plurality of word line structures on the gate dielectric layer, wherein the plurality of word line structures are respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures; forming a storage node contact structure on the substrate, wherein the storage node contact structure is directly connected to one of the plurality of active regions; The storage node contact structure is also directly connected to the oxide semiconductor layer.

10. The method for manufacturing a memory device according to claim 9, wherein: The oxide semiconductor layer is conformally formed on the surface of each of the trenches through a first film forming process.

11. The method for manufacturing a memory device according to claim 10, wherein: The first film forming process includes an atomic layer deposition process.

12. The method for manufacturing a memory device according to claim 10, wherein: The gate dielectric layer is conformally formed on the oxide semiconductor layer by a second film forming process, wherein the first film forming process and the second film forming process are performed successively in the same process chamber.

13. The method for manufacturing a memory device according to claim 9, wherein: The thickness of the oxide semiconductor layer in a vertical direction is smaller than the depth of each trench in the vertical direction.

14. The method for manufacturing a memory device according to claim 9, wherein: The thickness of the oxide semiconductor layer in a vertical direction is smaller than the length of each word line structure in the vertical direction.

15. The method for manufacturing a memory device according to claim 9, wherein: A portion of the substrate is disposed between two adjacent grooves.

16. The method for manufacturing a memory device according to claim 9, wherein: The word line structures cross the active regions and divide each active region into three sections.

17. The method for manufacturing a memory device according to claim 9, wherein: Also includes: A mask layer is formed on the word line structure, wherein the mask layer is in direct contact with the oxide semiconductor layer and the gate dielectric layer.

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