A high conversion gain millimeter wave frequency quadrupler

Abstract

The application discloses a high conversion gain millimeter wave four frequency multiplier, which comprises an input matching network, a first frequency multiplication unit, a first interstage matching network, a second frequency multiplication unit, a second interstage matching network, a buffer amplification unit and an output matching network. The frequency multiplication unit adopts a single-end structure, an input signal is subjected to two secondary frequency multiplication units to finally generate a four frequency multiplication output signal, other harmonics at the output ends of the frequency multiplication units are suppressed through the first and second interstage matching networks, and a high-gain common-source driving amplifier is cascaded at the last stage of the circuit. The application effectively improves the problems of low conversion gain and poor harmonic suppression of the single-end frequency multiplier, and can meet the demand of some high-power local oscillator sources.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of millimeter wave signal sources, and particularly relates to a high conversion gain millimeter wave frequency quadrupler. BACKGROUND

[0002] With the continuous development of wireless communication systems, the demand for spectrum resources of high-speed wireless communication technology is increasing. Millimeter waves have a wide range of application scenarios in high-speed communication, millimeter wave imaging, radar, sub-terahertz detectors, and biomedicine due to their short wavelength, wide frequency band, high transmission rate, and other characteristics.

[0003] In a millimeter wave communication system, a frequency source, as an indispensable part of a transceiver, plays a crucial role. A low-frequency frequency source is usually obtained directly from an oscillator, but in the millimeter wave frequency band, the frequency stability and phase noise of the frequency source obtained by the traditional method often do not meet the requirements. The commonly used method is to frequency multiply the low-frequency frequency source to the high-frequency band through a frequency multiplier, which can also improve the performance of the frequency source in terms of output power, bandwidth, etc., to meet the requirements of millimeter wave communication.

[0004] Common millimeter wave frequency multiplication structures include single-ended frequency multipliers and push-push frequency multipliers. Single-tube frequency multiplier structures are simple and have advantages in terms of power consumption and circuit size; however, single-tube frequency multipliers often have difficulty in achieving high harmonic suppression and bandwidth, and have low output power, which limits their application. SUMMARY

[0005] In order to overcome the problems in the above-mentioned technologies, the application provides a high conversion gain millimeter wave frequency quadrupler. The conversion gain, output power, operating bandwidth, and harmonic suppression of the single-ended frequency multiplier are improved, and the practicality of the single-ended frequency multiplier is improved. A matching filter structure is proposed, which effectively improves the harmonic suppression and operating bandwidth of the single-ended frequency multiplier; a high-gain drive amplifier is cascaded at the frequency multiplication output end, which greatly improves the conversion gain and output power of the millimeter wave frequency quadrupler.

[0006] The technical solution comprises an input matching network, a first frequency multiplication unit, a first inter-stage matching network, a second frequency multiplication unit, a second inter-stage matching network, a buffer amplification unit, and a matching network connected in sequence, wherein

[0007] The input matching network matches the input impedance of the first frequency multiplication unit to 50 ohms and provides out-of-band suppression to filter out noise signals at the input end;

[0008] The first frequency multiplication unit generates harmonic signals of the input signal and provides gain;

[0009] The first inter-stage matching network filters the fundamental wave and the third harmonic wave output by the first frequency multiplication unit, and matches the output impedance of the first frequency multiplication unit to the input impedance of the second frequency multiplication unit, and a part of the matching elements in the first inter-stage matching network constitutes a drain bias circuit of the first frequency multiplication unit.

[0010] The second frequency multiplication unit generates harmonic signals of the input signal at its gate, and provides gain.

[0011] The second inter-stage matching network filters the second harmonic wave and the sixth harmonic wave output by the second frequency multiplication unit, and matches the output impedance of the second frequency multiplication unit to the input impedance of the buffer amplification unit, and a part of the matching elements in the second inter-stage matching network constitutes a drain bias circuit of the second frequency multiplication unit.

[0012] The buffer amplification unit is used to provide gain for the fourth harmonic wave output by the second frequency multiplication unit, improve the output power of the entire millimeter wave four-frequency multiplier, and improve the gain flatness of the four-frequency multiplier.

[0013] The output matching network matches the output impedance of the buffer amplification unit to 50 ohms, and suppresses the eighth harmonic wave.

[0014] Preferably, the input matching network comprises inductance L1, capacitance C1, C2 and inductance L2, wherein the positive port of the inductance L1 is connected to the input signal line, and the negative port is grounded; the positive port of the capacitance C1 is connected to the positive port of the inductance L1, and the negative port is grounded; the inductance L1 and the capacitance C1 constitute a parallel resonance; the two ports of the capacitance C2 are respectively connected to the positive ports of the inductances L1 and L2; the negative port of the inductance L2 is grounded; the positive port of the DC blocking capacitance Cd1 is connected to the positive port of the inductance L2, and the negative port is connected to the gate of the transistor M1.

[0015] Preferably, the first frequency multiplication unit comprises a transistor M1, the transistor M1 adopts GaAs PHEMT, the gate width is 25 um, the number of interdigital fingers is 2, the drain bias participates in matching as a part of the first inter-stage matching network, and the working state is class C, that is, the conduction angle is less than half a period.

[0016] Preferably, the first inter-stage matching network includes inductors L3, L4, L5, L6, and capacitors C3 and C4, wherein the positive and negative ports of inductor L3 are connected to the drain of transistor M1 and the positive port of inductor L4 respectively, the negative port of inductor L4 is connected to the positive port of capacitor C3, the negative port of capacitor C3 is grounded, inductor L4 and capacitor C3 form a series resonance at the input signal frequency f; the positive port of inductor L5 is connected to the positive port of inductor L4, and the negative port is connected to the positive port of capacitor C4, the negative port of capacitor C4 is grounded, inductor L5 and capacitor C4 form a series resonance at frequency 3f; the series branch formed by inductor L4 and capacitor C3 and the series branch formed by inductor L5 and capacitor C4 form a parallel resonance at 2f; the positive port of inductor L6 is connected to the positive port of inductor L4, and the negative port is connected to the positive port of DC blocking capacitor Cd2, and the negative port of Cd2 is connected to the gate of transistor M2.

[0017] Preferably, the second frequency doubling unit includes transistor M2, which is a GaAs PHEMT with a gate width of 25um and 2 interdigital fingers, the drain is biased as part of the second inter-stage matching network to participate in matching, and the working state is class C, i.e. the conduction angle is less than half a period.

[0018] Preferably, the second inter-stage matching network includes inductors L7, L8, L9, L10, and capacitors C5 and C6, wherein the positive and negative ports of inductor L7 are connected to the drain of transistor M2 and the positive port of inductor L8 respectively, the negative port of inductor L8 is connected to the positive port of capacitor C5, and the negative port of capacitor C5 is grounded; inductor L8 and capacitor C5 form a series resonance at frequency 2f; the positive port of inductor L9 is connected to the positive port of inductor L8, and the negative port is connected to the positive port of capacitor C6, the negative port of capacitor C6 is grounded, inductor L9 and capacitor C6 form a series resonance at frequency 6f; the series branch formed by inductor L8 and capacitor C5 and the series branch formed by inductor L9 and capacitor C6 form a parallel resonance at frequency 4f; the positive port of inductor L10 is connected to the positive port of inductor L8, and the negative port is connected to the positive port of DC blocking capacitor Cd3, and the negative port of Cd3 is connected to the gate of transistor M3.

[0019] Preferably, the buffer amplification unit includes transistor M3, which is a GaAs PHEMT with a gate width of 50um and 2 interdigital fingers, and adopts a common-source amplification structure; the buffer amplification unit further includes a feedback branch composed of inductor L11, DC blocking capacitor Cd4, and resistor R1, which is connected across the gate and drain of transistor M3, to improve the stability and bandwidth of the buffer amplification unit; the drain is biased as part of the second inter-stage matching network to participate in matching, and the working state is class AB, i.e. the conduction angle is greater than half a period and less than one period.

[0020] Preferably, the output matching circuit comprises inductors L12, L13, L14, capacitors C7, C8, wherein the positive port of the inductor L12 is connected to the drain of the transistor M3, the negative port is connected to the positive port of the inductor L13, the negative port of the inductor L13 is connected to the positive port of the capacitor C7, and the negative port of the capacitor C7 is grounded; the inductor L15 and the capacitor C7 constitute a series resonance, and the resonance is at a frequency of 8f; the positive port of the inductor L14 is connected to the positive port of the inductor L13, the negative port is connected to the positive port of the capacitor C8, the negative port of the capacitor C8 is grounded, the positive port of the DC blocking capacitor Cd5 is connected to the positive port of the inductor L13, and the negative port is connected to the output of the frequency quadrupler.

[0021] The beneficial effects of the present application at least include:

[0022] (1) The millimeter wave frequency quadrupler of the present application realizes four times frequency multiplication of the millimeter wave frequency band, reduces the frequency of the local oscillator input signal for the required millimeter wave frequency source, and improves the stability of the frequency source.

[0023] (2) The millimeter wave frequency quadrupler of the present application effectively suppresses each harmonic frequency except the required frequency through a new type of matching filter structure, and at the same time improves the bandwidth of the output signal. Compared with the prior art, the present application uses a single-ended structure to realize higher harmonic suppression and output bandwidth, saves circuit area and power consumption, and is conducive to reducing cost.

[0024] (3) The millimeter wave frequency quadrupler of the present application realizes higher conversion gain, improves the output power and efficiency of the frequency quadrupler, and can meet the demand of some high-power local oscillator source. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to make the purpose, technical scheme and beneficial effects of the present application clearer, the present application provides the following drawings for illustration:

[0026] Figure 1 is the circuit principle diagram of the high conversion gain millimeter wave frequency quadrupler of the embodiment of the present application;

[0027] Figure 2 is the output power and each harmonic power diagram of the high conversion gain millimeter wave frequency quadrupler of the embodiment of the present application. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present application will be described in detail below with reference to the drawings.

[0029] Reference Figure 1The figure is a high conversion gain millimeter wave four frequency multiplier circuit schematic diagram of the embodiment of the present application, the main body structure includes input matching network 10, first frequency multiplication unit 20, first interstage matching network 30, second frequency multiplication unit 40, second interstage matching network 50, buffer amplification unit 60, output matching network 70. The fundamental wave signal enters the first frequency multiplication unit 20 through the input matching network 10 to generate each harmonic, the first interstage matching network 30 suppresses each harmonic except the second harmonic, and the second harmonic is input to the second frequency multiplication unit 40, the second interstage matching network 50 suppresses each harmonic except the fourth harmonic, and the fourth harmonic is input to the buffer amplification unit 60, and the output matching network matches the output impedance to 50 ohms to ensure the maximum gain output.

[0030] The input matching network 10 includes inductance L1, capacitance C1, C2 and inductance L2. The positive port of the inductance L1 is connected with the input signal line, and the negative port is grounded; the positive port of the capacitance C1 is connected with the positive port of the inductance L1, and the negative port is grounded; the inductance L1 and the capacitance C1 constitute parallel resonance, and the resonance is near the input signal frequency f; the positive and negative ports of the capacitance C2 are connected with the positive ports of the inductance L1 and L2 respectively, and the negative port of the inductance L2 is grounded; the positive port of the DC blocking capacitance Cd1 is connected with the positive port of the inductance L2, and the negative port is connected with the gate of the transistor M1.

[0031] The first frequency multiplication unit 20 includes the transistor M1 and its bias circuit, and the gate bias Vg1 of the transistor M1 is connected with the gate through a large resistance Rg1. The drain bias Vd1 of the transistor M1 is added to the negative end of the inductance L4, the positive port of the capacitance C3 is connected with the negative end of the inductance L4, and the negative port is grounded, constituting a bypass capacitor.

[0032] The first interstage matching network 30 includes inductance L3, L4, L5, L6, and capacitance C3 and C4. The positive and negative ports of the inductance L3 are connected with the drain of the transistor M1 and the positive port of the inductance L4 respectively, the negative port of the inductance L4 is connected with the positive port of the capacitance C3, and the negative port of the capacitance C3 is grounded; the inductance L4 and the capacitance C3 constitute series resonance, and the resonance is near the input signal frequency f, realizing the suppression of the fundamental wave; the positive port of the inductance L5 is connected with the positive port of the inductance L4, the negative port is connected with the positive port of the capacitance C4, the negative port of the capacitance C4 is grounded, the inductance L5 and the capacitance C4 constitute series resonance, and the resonance is near the frequency 3f, realizing the suppression of the third harmonic; the series branch of the inductance L4 and the capacitance C3 is inductive at 2f, the series branch of the inductance L5 and the capacitance C4 is capacitive at 2f, and the values are adjusted so that the two branches constitute parallel resonance at the frequency 2f, increasing the matching bandwidth; the positive port of the inductance L6 is connected with the positive port of the inductance L4, and the negative port is connected with the positive port of the DC blocking capacitance Cd2, and the negative port of the Cd2 is connected with the gate of the transistor M2.

[0033] The second frequency doubling unit 40 comprises a transistor M2 and its bias circuit, the gate bias Vg2 of the transistor M2 is connected with the gate through a large resistance Rg2. The drain bias Vd2 of the transistor M2 is added to the negative port of the inductor L8, the positive port of the capacitor C5 is connected with the negative port of the inductor L8, and the negative port is grounded, thereby forming a bypass capacitor.

[0034] The second inter-stage matching network 50 is composed of inductors L7, L8, L9, L10, and capacitors C5, C6. The positive and negative ports of the inductor L7 are connected with the drain of the transistor M2 and the positive port of the inductor L8 respectively, the negative port of the inductor L8 is connected with the positive port of the capacitor C5, and the negative port of the capacitor C5 is grounded; the inductor L8 and the capacitor C5 form a series resonance, and the resonance is near the frequency 2f, thereby achieving the suppression of the second harmonic; the positive port of the inductor L9 is connected with the positive port of the inductor L8, the negative port is connected with the positive port of the capacitor C6, the negative port of the capacitor C6 is grounded, the inductor L9 and the capacitor C6 form a series resonance, and the resonance is near the frequency 6f, thereby achieving the suppression of the sixth harmonic; the series branch composed of the inductor L8 and the capacitor C5 is inductive at the frequency 4f, the series branch composed of the inductor L9 and the capacitor C6 is capacitive at the frequency 4f, the values are adjusted so that the upper and lower branches form a parallel resonance at the frequency 4f, thereby increasing the bandwidth of the matching; the positive port of the inductor L10 is connected with the positive port of the inductor L8, the negative port is connected with the positive port of the direct current blocking capacitor Cd3, and the negative port of the Cd3 is connected with the gate of the transistor M3.

[0035] The buffer amplification unit 60 comprises a transistor M3, a resistance Rg3, and an inductor L11, a direct current blocking capacitor Cd4, and a resistance R1. The positive port of the inductor L11 is connected with the drain of the transistor M3, the negative port is connected with the positive port of the direct current blocking capacitor Cd4, the negative port of the Cd4 is connected with the positive port of the resistance R1, and the negative port of the resistance R1 is connected with the drain of the transistor M3. The inductor L11, the direct current blocking capacitor Cd4, and the resistance R1 form a feedback branch of the buffer amplification stage, the inductor L11 is high resistance at the frequency 4f, and at the same time, the feedback branch loss is reduced. The main purpose of introducing the feedback branch is to improve the stability and bandwidth of the frequency doubling stage.

[0036] The output matching network 70 is composed of inductors L12, L13, L14, capacitors C7, C8, and a direct current blocking capacitor Cd5. The positive port of the inductor L12 is connected with the drain of the transistor M3, the negative port is connected with the positive port of the inductor L13, the negative port of the inductor L13 is connected with the positive port of the capacitor C7, and the negative port of the capacitor C7 is grounded; the inductor L15 and the capacitor C7 form a series resonance, and the resonance is near the frequency 8f, thereby achieving the suppression of the eighth harmonic generated by the frequency doubling stage; the positive port of the inductor L14 is connected with the positive port of the inductor L13, the negative port is connected with the positive port of the capacitor C8, the negative port of the capacitor C8 is grounded, the positive port of the direct current blocking capacitor Cd5 is connected with the negative port of the inductor L14, and the negative port is connected with the final output signal.

[0037] The transistors M1 and M2 of the frequency multiplication unit in the embodiment operate in class C, i.e. the conduction angle is less than half of a period, and the nonlinearity of the transistors is used to generate each harmonic of the input signal; the transistor M3 of the buffer amplification unit 60 operates in class AB, has good linearity and high gain, and the balance of power consumption is also considered.

[0038] The embodiment is based on a 100nm GaAs PHEMT process and is verified by ADS simulation software, Figure 2 The output power and harmonic output power of the millimeter wave frequency quadrupler when the input signal power is 0dBm are given, the maximum output power is 14dBm, the 3dB bandwidth of the output power is 49.2GHz-57.6GHz, the fundamental wave suppression is greater than 31dBc in the input frequency range of 12.3GHz-14.4GHz, the second harmonic suppression is greater than 45dBc, the third harmonic suppression is greater than 25dBc, the fifth, sixth, seventh and eighth harmonic suppressions are all greater than 26dBc, and good harmonic suppression is achieved. In addition, the frequency multiplication gain is greater than 11dB in the frequency range of 12.3GHz-14.4GHz, reaches the maximum frequency multiplication gain of 14dB at 13.75GHz, and a millimeter wave frequency quadrupler with high frequency multiplication gain is achieved.

[0039] Finally, it should be pointed out that the above preferred embodiments are only used to illustrate the technical solutions of the present application but not limit the present application, although the present application has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made in form and details without departing from the scope defined by the claims of the present application.

Claims

1. A high conversion gain millimeter wave frequency quadrupler, characterized by, The input matching network, the first frequency multiplication unit, the first inter-stage matching network, the second frequency multiplication unit, the second inter-stage matching network, the buffer amplification unit and the output matching network are sequentially connected, wherein, The input matching network matches the input impedance of the first frequency multiplication unit to 50 ohms while providing out-of-band rejection to filter out noise signals at the input end; The first frequency multiplication unit generates harmonic signals of the input signal and provides gain; The first inter-stage matching network filters out the fundamental wave and the third harmonic wave output by the first frequency multiplication unit while matching the output impedance of the first frequency multiplication unit to the input impedance of the second frequency multiplication unit, and a part of the matching elements in the first inter-stage matching network form a drain bias circuit of the first frequency multiplication unit; The second frequency multiplication unit generates harmonic signals of the input signal at its gate end and provides gain; The second inter-stage matching network filters out the second harmonic wave and the sixth harmonic wave output by the second frequency multiplication unit while matching the output impedance of the second frequency multiplication unit to the input impedance of the buffer amplification unit, and a part of the matching elements in the second inter-stage matching network form a drain bias circuit of the second frequency multiplication unit; The buffer amplification unit is used to provide gain to the fourth harmonic wave output by the second frequency multiplication unit, improve the output power of the entire millimeter wave four-frequency multiplier, and improve the gain flatness of the four-frequency multiplier; The output matching network matches the output impedance of the buffer amplification unit to 50 ohms while suppressing the eighth harmonic wave; The input matching network comprises inductors L1, capacitors C1 and C2, and an inductor L2, wherein the positive port of the inductor L1 is connected to an input signal line, and the negative port is grounded; the positive port of the capacitor C1 is connected to the positive port of the inductor L1, and the negative port is grounded; the inductor L1 and the capacitor C1 form a parallel resonance; the positive and negative ports of the capacitor C2 are connected to the positive ports of the inductors L1 and L2, respectively; the negative port of the inductor L2 is grounded; the positive port of the DC blocking capacitor Cd1 is connected to the positive port of the inductor L2, and the negative port is connected to the gate of the transistor M1; The first inter-stage matching network comprises inductors L3, L4, L5 and L6, and capacitors C3 and C4, wherein the positive and negative ports of the inductor L3 are connected to the drain of the transistor M1 and the positive port of the inductor L4, respectively; the negative port of the inductor L4 is connected to the capacitor C3, the negative port of the capacitor C3 is grounded, the inductor L4 and the capacitor C3 form a series resonance at the input signal frequency f; the positive port of the inductor L5 is connected to the positive port of the inductor L4, the negative port is connected to the positive port of the capacitor C4, the negative port of the capacitor C4 is grounded, the inductor L5 and the capacitor C4 form a series resonance at the frequency 3f; the series branch formed by the inductor L4 and the capacitor C3 and the series branch formed by the inductor L5 and the capacitor C4 form a parallel resonance at 2f; the positive port of the inductor L6 is connected to the positive port of the inductor L4, and the negative port is connected to the positive port of the DC blocking capacitor Cd2, and the negative port of the capacitor Cd2 is connected to the gate of the transistor M2. The output matching circuit comprises inductors L12, L13, L14 and capacitors C7 and C8, wherein the positive port of the inductor L12 is connected with the drain of the transistor M3, the negative port is connected with the positive port of the inductor L13, the negative port of the inductor L13 is connected with the positive port of the capacitor C7, and the negative port of the capacitor C7 is grounded; the inductor L13 and the capacitor C7 constitute a series resonance at the frequency 8f; the positive port of the inductor L14 is connected with the positive port of the inductor L13, the negative port is connected with the positive port of the capacitor C8, the negative port of the capacitor C8 is grounded, the positive port of the DC blocking capacitor Cd5 is connected with the positive port of the inductor L13, and the negative port is connected with the output terminal of the frequency quadrupler.

2. The high conversion gain millimeter wave frequency quadrupler of claim 1, wherein, The first frequency doubling unit comprises a transistor M1, the transistor M1 adopts GaAs PHEMT, the gate width is 25um, the number of interdigital fingers is 2, the drain bias participates in matching as a part of the first interstage matching network, and the working state is class C, i.e. the conduction angle is less than half a period.

3. The high conversion gain millimeter wave frequency quadrupler of claim 1, wherein, The second frequency doubling unit comprises a transistor M2, the transistor M2 adopts GaAs PHEMT, the gate width is 25um, the number of interdigital fingers is 2, the drain bias participates in matching as a part of the second interstage matching network, and the working state is class C, i.e. the conduction angle is less than half a period.

4. The high conversion gain millimeter wave frequency quadrupler of claim 3, wherein, The second interstage matching network comprises inductors L7, L8, L9, L10 and capacitors C5 and C6, wherein the positive and negative ports of the inductor L7 are connected with the drain of the transistor M2 and the positive port of the inductor L8 respectively, the negative port of the inductor L8 is connected with the positive port of the capacitor C5, and the negative port of the capacitor C5 is grounded; the inductor L8 and the capacitor C5 constitute a series resonance at the frequency 2f; the positive port of the inductor L9 is connected with the positive port of the inductor L8, the negative port is connected with the positive port of the capacitor C6, the negative port of the capacitor C6 is grounded, the inductor L9 and the capacitor C6 constitute a series resonance at the frequency 6f; the series branch of the inductor L8 and the capacitor C5 and the series branch of the inductor L9 and the capacitor C6 constitute a parallel resonance at the frequency 4f; the positive port of the inductor L10 is connected with the positive port of the inductor L8, and the negative port is connected with the positive port of the DC blocking capacitor Cd3, and the negative port of the capacitor Cd3 is connected with the gate of the transistor M3.

5. The high conversion gain millimeter wave frequency quadrupler of claim 1, wherein, The buffer amplification unit comprises a transistor M3, the transistor M3 adopts GaAs PHEMT, the gate width is 50um, the number of interdigital fingers is 2, and a common source amplification structure is adopted; the buffer amplification unit further comprises a feedback branch composed of an inductor L11, a DC blocking capacitor Cd4 and a resistor R1, which is connected across the gate and the drain of the transistor M3, so as to improve the stability and bandwidth of the buffer amplification unit; the drain bias participates in matching as a part of the second interstage matching network, and the working state is class AB, i.e. the conduction angle is greater than half a period and less than one period.

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