A microwave wideband differential variable gain amplifier

Abstract

The application discloses a microwave wideband differential variable gain amplifier and relates to the technical field of electronic circuits.The amplifier comprises a differential structure variable gain amplification circuit, an additional phase shift phase offset numerical control bias circuit and a power consumption control bias circuit.The application is applicable to BiCMOS and other processes, the differential variable gain amplification circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, two control voltages which make the phase change trends opposite when the VGA gain is reduced (increased) are designed, and a phase compensation resistor is designed to realize the low additional phase shift characteristic of the VGA.The two control voltages are generated by the additional phase shift phase offset numerical control bias circuit, and a plurality of digital control bits are set to select a target gain state from the two control voltages to reduce the gain error of the VGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a low additional phase shift low RMS gain error wideband variable gain amplifier suitable for BiCMOS process. BACKGROUND

[0002] The phased array system is a hotspot of current research due to its strong anti-interference ability, high signal-to-noise ratio and anti-interference, and is widely used in satellite communication, radar and high-speed point-to-point communication fields.

[0003] The variable gain amplifier is an indispensable module in the phased array system, and the gain variable range, phase error and gain control precision of the VGA will affect the beam scanning precision and sidelobe suppression level of the phased array system. The gain variation precision of the VGA will affect the sidelobe suppression level of the phased array system, and the additional phase shift of the VGA will affect the beam scanning precision of the phased array system. Therefore, it is necessary to reduce the phase error and amplitude error of the VGA in a wide frequency band. SUMMARY

[0004] The embodiment of the present application provides a microwave wideband differential variable gain amplifier, which can solve the technical problem of high phase error and amplitude error of the VGA in the prior art.

[0005] The embodiment of the present application provides a microwave wideband differential variable gain amplifier, which comprises a differential structure variable gain amplification circuit and an additional phase shift offset digital control bias circuit.

[0006] The differential structure variable gain amplification circuit comprises a common emitter tube T2 and a common emitter tube T4, the collector of the common emitter tube T2 is connected with a common base tube T1 and a common base tube T5, and the collector of the common emitter tube T4 is connected with a common base tube T3 and a common base tube T6; wherein the common base of the common base tube T5 and the common base tube T6 is a first control voltage end VCTRL1, and the common base of the common base tube T1 and the common base tube T3 is a second control voltage end VCTRL2.

[0007] The additional phase shift offset digital control bias circuit comprises a common source common gate current mirror and seven pairs of bipolar junction transistors (BJT) as switches, the emitter of each pair of BJT is connected in series to the same bit of the common source common gate current mirror, and the base of each pair of BJT is connected with a level signal X i and an opposite level signal generated by an inverter, wherein i=0~6; the base is connected with the BJT collector interconnection node of the level signal X i , and the base is connected with the BJT collector interconnection node of the opposite level signal The second control voltage VCTRL2 is output at the BJT collector interconnection node.

[0008] Further, the collector of the common-emitter tube T2 is connected in series with the emitter of the common-base tube T1, the collector of the common-emitter tube T2 is connected in series with the emitter of the common-base tube T5, the collector of the common-emitter tube T4 is connected in series with the emitter of the common-base tube T6, and the collector of the common-emitter tube T4 is connected in series with the emitter of the common-base tube T3.

[0009] Further, the differential input signal of the differential structure variable gain amplification circuit is loaded to the bases of the common-emitter tubes T2 and T4 through an input matching network.

[0010] The input matching network comprises: one end of the inductor L1 and one end of the inductor L3 are connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the input power supply VIN+, one end of the inductor L2 and one end of the inductor L4 are connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the input power supply VIN-, the other end of the inductor L3 and the other end of the inductor L4 are connected to the ground through the capacitor CB1 and the capacitor CB2.

[0011] Further, the output matching network of the differential structure variable gain amplification circuit comprises:

[0012] The inductor LC1, the inductor LC2, the differential inductor LD, the resistor RC1 and the resistor RC2 are connected in parallel, and are connected to the output end through the output DC blocking capacitor C3 and the output DC blocking capacitor C4; the power supply VDD is loaded to the collector of the common-emitter tube T1 through the inductor LC1, the differential inductor LD and the resistor RC1 in parallel, and is loaded to the collector of the common-emitter tube T3 through the inductor LC2, the differential inductor LD and the resistor RC2 in parallel.

[0013] Further, the input return loss improvement circuit of the differential structure variable gain amplification circuit comprises:

[0014] The series connection of the resistor RE5 and the capacitor CE2 and the series connection of the resistor RE6 and the capacitor CE1 are connected in series between the emitters of the common-emitter tubes T2 and T4; the degenerative inductor LE with the center connected to the ground is connected in series between the emitters of the common-emitter tubes T2 and T4.

[0015] Further, the power consumption control bias circuit of the differential structure variable gain amplification circuit comprises:

[0016] The triode T7, the resistor RB1 and the resistor RB2 form the power consumption control bias circuit; the power supply VDD is directly loaded to the collector of the triode T7, the bias voltage VBIAS is loaded to the base of the triode T7, and the emitter of the triode T7 is connected to the bases of the common-emitter tubes T2 and T4 through the resistor RB1 and the resistor RB2.

[0017] Further, the common-source common-gate current mirror is a common-source common-gate current mirror designed by using equal proportion MOS tubes.

[0018] Further, the additional phase shift and cancellation digital control bias circuit sets 7-bit digital control bits to control 34 gain states.

[0019] Further, the additional phase shift and cancellation digital control bias circuit further comprises:

[0020] The base of the transistor T7 and the transistor T8 is connected to the fixed power supply VB, and the emitter of the transistor T7 and the transistor T8 is connected to the common-source common-gate current mirror.

[0021] Further, the additional phase shift and cancellation digital control bias circuit further comprises:

[0022] The base is connected to the level signal X i The collector of the BJT is connected to the collector of the transistor T7, and then connected to the resistor R3, the transistor T9 and the resistor R1 in sequence, and then connected to the power supply VDD, the base of the transistor T9 is connected to the collector, and the resistor R1 is connected, the emitter of the transistor T9 is connected to the resistor R3, and the first control voltage VCTRL1 is output at the collector interconnection node of the BJT;

[0023] The base is connected to the opposite level signal The collector of the BJT is connected to the collector of the transistor T8, and then connected to the resistor R4, the transistor T10 and the resistor R2 in sequence, and then connected to the power supply VDD, the base of the transistor T10 is connected to the collector, and the resistor R2 is connected, the emitter of the transistor T10 is connected to the resistor R4, and the second control voltage VCTRL2 is output at the collector interconnection node of the BJT.

[0024] Compared with the prior art, the microwave wideband differential variable gain amplifier has the following beneficial effects:

[0025] The application provides a variable gain amplifier with low additional phase shift and low RMS gain error, which is suitable for BiCMOS process and the like, and a differential variable gain amplifier circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, and the low additional phase shift characteristic of the VGA is realized by designing two control voltages which make the phase change trends opposite when the gain of the VGA is reduced (increased) and designing a phase compensation resistor; and the two control voltages are generated by a digital control biasing circuit which offsets the additional phase shift, and a multi-bit digital control bit is set to select a target gain state from the two control voltages to reduce the gain error of the VGA. That is, the phase error of the variable gain amplifier is reduced by designing two control voltages which make the phase change trends opposite when the gain of the VGA is reduced (increased) and designing a phase compensation resistor; and the RMS amplitude error of the variable gain amplifier is reduced by designing a multi-bit control bit in the digital control biasing circuit which offsets the additional phase shift to select a target gain state. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram of a variable gain amplifier with low additional phase shift and low RMS gain error provided by the embodiment of the application;

[0027] Figure 2 A schematic diagram of a digital control biasing circuit module which offsets the additional phase shift provided by the embodiment of the application;

[0028] Figure 3 A schematic diagram of the phase change when the gain is controlled by the first control voltage and the second control voltage (a) and a schematic diagram of the phase compensation result (b) provided by the embodiment of the application;

[0029] Figure 4 Simulation results of 32 kinds of gain states of the variable gain amplifier with low additional phase shift and low RMS gain error provided by the embodiment of the application;

[0030] Figure 5 RMS phase error of the variable gain amplifier with low additional phase shift and low RMS gain error provided by the embodiment of the application;

[0031] Figure 6 Relative phase result of the variable gain amplifier with low additional phase shift and low RMS gain error provided by the embodiment of the application;

[0032] Figure 7 RMS gain error of the variable gain amplifier with low additional phase shift and low RMS gain error provided by the embodiment of the application. DETAILED DESCRIPTION

[0033] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in many different manners without the specific details, and it is to be understood that the present application is not limited to the specific embodiments described below and that the specific embodiments are given for the purposes of exemplification only.

[0034] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0035] In addition, the terms "first", "second", "third" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0036] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0037] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0038] It is to be understood that when an element such as a layer, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] The low additional phase shift low RMS gain error microwave broadband differential variable gain amplifier provided by the embodiment of the application comprises a differential structure variable gain amplifier circuit, an additional phase shift and offset digital control bias circuit and a power consumption control bias circuit. The variable gain amplifier circuit is a differential current steering type Cascode structure, comprising a pair of common emitter tubes and two pairs of common base tubes. The additional phase shift and offset digital control bias circuit directly controls the VGA gain without the need of an additional DAC circuit. In the differential structure variable gain amplifier circuit, two control voltages are designed to make the phase change trends opposite when the VGA gain is reduced (increased), and a phase compensation resistor is designed to reduce the phase error of the variable gain amplifier. A multi-bit control bit is designed in the additional phase shift and offset digital control bias circuit to screen the target gain state, thereby reducing the RMS amplitude error of the variable gain amplifier.

[0040] The additional phase shift and offset digital control bias circuit sets 7-bit digital control bits, from which 34 gain state bits are selected to minimize the gain error of the variable gain amplifier. The additional phase shift and offset digital control bias circuit is realized by using a MOS tube equal proportion array series switch circuit, and no additional DAC circuit is needed for digital control. That is, the 7-bit digital control bias circuit (which can control 128 gain states) is used to control 34 gain states.

[0041] The differential input signal of the differential structure variable gain amplifier circuit is loaded to the base of the common emitter tubes T2 and T4 through an input matching network. The input matching network comprises inductors L1-L4 and capacitors C1 and C2. The inductor L3 and the inductor L4 are grounded through capacitors CB1 and CB2. The inductor LC1, the inductor LC2, the differential inductor LD, the parallel resistor RC and the output DC blocking capacitors C3 and C4 constitute an amplifier output matching network. The series resistor RE5 and CE2 series structure and the series resistor RE6 and CE1 series structure between the emitters of the common emitter tubes T2 and T4 improve the input return loss of the amplifier. The center ground degeneration inductor LE in series between the emitters of the common emitter tubes T2 and T4 improves the stability of the amplifier.

[0042] Further, the series connection of resistors RE1-RE4 between the collectors of common-emitter tubes T2, T4 and the emitters of common-base tubes T1, T6, T5, T3 reduces the phase error of the variable gain amplifier. The bases of common-base tubes T5, T6 are connected to a first control voltage VCTRL1, and the bases of common-base tubes T1, T3 are connected to a second control voltage VCTRL2. When the gain is controlled to decrease (increase), the first control voltage VCTRL1 and the second control voltage VCTRL2 cause opposite phase change trends, which finally reduce the phase error of the amplifier.

[0043] Further, the first control voltage VCTRL1 and the second control voltage VCTRL2 are generated by a 7-bit digitally controlled biasing circuit for offsetting the additional phase shift, in which a common-source common-gate current mirror is implemented using equal proportion MOS tubes, which are closer to ideal current mirrors than BJTs used as current mirrors, and 7 pairs of BJTs are used as switches, with the emitters of each pair of BJTs connected in series to the same bit of the common-source common-gate current mirror, and the bases of each pair of BJTs connected to level signals X i and opposite level signals are generated by inverters, in which i=0-6; the bases are connected to level signals X i The collectors of the BJTs connected to level signals X and opposite level signals are connected in series with the collector of transistor T8, and then connected in series with resistor R4, transistor T10, and resistor R2, and then connected to power supply VDD; the base and the collector of transistor T10 are connected in series and connected to resistor R2, and the emitter of transistor T10 is connected to resistor R4, and the second control voltage VCTRL2 is output at the node where the collectors of the BJTs are connected.

[0044] In which the bases of transistors T7 and T8 are connected to a fixed power supply VB, and the emitters are connected to a common-source common-gate current mirror, which provides a fixed current for the digitally controlled biasing circuit for offsetting the additional phase shift; transistors T9 and T10 are diode-connected devices, which reduce the collector level of the common-source common-gate current mirror to ensure normal operation of the MOS tubes.

[0045] Furthermore, the collectors of common-emitter transistors T1 and T3 are connected to the power supply VDD through a parallel structure of an inductor and a resistor RC; the power supply VDD is directly applied to the collectors of transistors T5, T6, and T7, and the bias voltage VBIAS is applied to the base of transistor T7. The emitter of transistor T7 is connected to the base of common-emitter transistors T2 and T4 through resistors RB1 and RB2. Transistor T7 and resistors RB1 and RB2 constitute a power consumption control bias circuit, which can achieve power consumption control of the variable gain amplifier circuit by changing the magnitude of the bias voltage VBIAS.

[0046] The variable gain amplifier circuit structure provided in this embodiment of the invention is as follows:

[0047] from Figure 1 As can be seen, the core component is a current-controlled Cascode structure, including a pair of common-emitter transistors T2 and T4, and two pairs of common-base transistors T1, T3, T5, and T6. The differential input signal V... IN (+) V IN (-) The input is applied to the bases of common-emitter transistors T2 and T4 through a T-type input matching network, which includes inductors L1 to L4 and capacitors C1 and C2. Inductors L3 and L4 are connected to capacitors C1 and C2. B1 C B2 Grounded; common base transistors T1 and T3 collector series inductor L C1 L C2 Connect inductor L D Then connect the parallel resistor R C1 R C2 Inductor L C1 L C2 With inductor L D Connect capacitors C3 and C4 between the nodes to the differential output port. Connect resistor R in series between the emitters of common-emitter transistors T2 and T4. E5 C E2 Series structure, resistor R E6 C E1 The series structure improves the amplifier input return loss, and the center-grounded degraded inductor L is connected in series between the emitters of common-emitter transistors T2 and T4. E This is used to improve amplifier stability.

[0048] Power supply V DD Through inductor L C1 Differential inductor L D With resistance R C1 R C2 A parallel structure is applied to the collectors of common-emitter transistors T1 and T3; power supply V DD The bias voltage V is directly applied to the collectors of transistors T5, T6, and T7. BIASThe load is applied to the base of transistor T7, and the emitter of transistor T7 is connected to resistor R. B1 R B2 Connect the bases of common-emitter transistors T2 and T4, and transistor T7 and resistor R. B1 R B2 This constitutes a power consumption control bias circuit, which can control the bias voltage V by changing the bias voltage V. BIAS The size enables power consumption control of the variable gain amplifier circuit. The first control voltage V... CTRL1 Connect common base transistors T5 and T6, and the second control voltage V CTRL2 Connect common base tubes T1 and T3.

[0049] First control voltage V CTRL1 Second control voltage V CTRL2 Generated by a 7-digit digitally controlled bias circuit with additional phase shift cancellation, such as Figure 2 As shown, the common-source cascode current mirror is implemented using proportionally scaled MOSFETs, with 7 pairs of BJTs used as switches. The emitter of each pair of BJTs is connected in series with the same common-source cascode current mirror, and the base of each pair of BJTs is connected to the level signal X. i opposite level signal Generated by an inverter, where i = 0 to 6; the base is connected to the level signal X. i The collectors of the BJT and transistor T7 are interconnected, followed by a series connection of resistor R3, transistor T9, and resistor R1, and then connected to power supply VDD. The base and collector of transistor T9 are interconnected and connected to resistor R1, while the emitter of transistor T9 is connected to resistor R3. A first control voltage VCTRL1 is output at the BJT collector interconnection node; the base is connected to an opposite level signal. After the collector of the BJT is connected to the collector of the transistor T8, the resistor R4, the transistor T10, and the resistor R2 are connected in series and then connected to the power supply VDD. The base and collector of the transistor T10 are interconnected and connected to the resistor R2. The emitter of the transistor T10 is connected to the resistor R4. The first control voltage VCTRL2 is output at the BJT collector interconnection node.

[0050] Figure 3 (a) is the first control voltage V CTRL1 Second control voltage V CTRL2 A schematic diagram of the gain-phase characteristics of a variable gain amplifier circuit under varying conditions: When the control gain decreases (increases), the first control voltage V... CTRL1 With the second control voltage V CTRL2 The resulting phase change trends are opposite. By simultaneously applying two control voltages to control the gain, the phase error of the variable gain amplifier can be reduced to a certain extent. The compensation result is illustrated in the diagram below. Figure 3 As shown in (b).

[0051] In order to offset the phase problem caused by the parasitic capacitance of the transistor, a small resistance R is connected in series between the collector of the common-emitter tube T2, T4 and the emitter of the common-base tube T1, T5, T6, T3 E1 ~R E4 , and the optimal resistance value of the small resistance is selected by compromising between the phase change of the VGA, the maximum gain, the gain dynamic range and the like; meanwhile, two control voltages V CRTL1 , V CTRL2 are used to control the gain of the VGA, and the current ratio of the current mirror, the reference current and the resistance R1~R4 are adjusted according to the maximum gain, the gain dynamic range and the gain step length of the VGA, so that the change of the two control voltages is within the dynamic range for optimizing the performance of the gain of the VGA. Figure 2

[0052] The beneficial effects of the present application will be described below in combination with simulation results:

[0053] Figure 4 The simulation results of 34 gain states selected for the variable gain amplifier with low additional phase shift and low RMS gain error. The maximum gain of the VGA can reach 15.8dB in the working frequency band of 8GHz-16GHz, the gain accuracy is 0.5dB, and the gain dynamic range reaches 16.5dB. As shown in Figure 7 , the VGA selects the target gain state by designing multiple control bits in the digitally controlled bias circuit for offsetting the additional phase shift, and the RMS gain error in the frequency band does not exceed 0.2dB under the condition of the gain accuracy of 0.5dB; the RMS phase error result is shown in Figure 5 , the RMS phase error of the VGA does not exceed 0.9° in the frequency band of 8GHz-16GHz, and the additional phase shift result of the VGA is shown in Figure 6 , the VGA has the maximum additional phase shift of less than 2.5° at 16GHz in the working frequency band.

[0054] In summary, the variable gain amplifier with low additional phase shift and low RMS gain error provided by the present application uses the current steering type Cascode structure for the variable gain circuit, improves the isolation of the front and rear stages, and stabilizes the input matching; the additional phase shift of the amplifier is effectively reduced by increasing a control voltage port (the second control voltage) to control the gain change of the amplifier together with the first control voltage and introducing the phase compensation resistance, and the compensation method is relatively simple; the first control voltage and the second control voltage are generated by the 7-bit digitally controlled bias circuit for offsetting the additional phase shift, and the digital control method is more simple than the analog voltage control, and does not need higher external conditions.

[0055] ​Any technical features in the above-described embodiments can be combined in any manner, and, for the sake of brevity, the foregoing description has not described all possible combinations of the technical features. However, it is contemplated that the scope of the disclosure encompasses all possible combinations of the technical features.

Claims

1. A microwave wideband differential variable gain amplifier, characterized by, The differential structure variable gain amplification circuit and the additional phase shift cancellation digital control bias circuit are included. The differential structure variable gain amplification circuit includes: common emitter tube T2 and common emitter tube T4, the collector of common emitter tube T2 is connected with common base tube T1 and common base tube T5, and the collector of common emitter tube T4 is connected with common base tube T3 and common base tube T6; wherein the common base of common base tube T5 and common base tube T6 is the first control voltage terminal VCTRL1, and the common base of common base tube T1 and common base tube T3 is the second control voltage terminal VCTRL2. The collector of common emitter tube T2 is connected with the emitter of common base tube T1, the collector of common emitter tube T2 is connected with the emitter of common base tube T5, the collector of common emitter tube T4 is connected with the emitter of common base tube T6, and the collector of common emitter tube T4 is connected with the emitter of common base tube T3, and the resistors RE1, RE2, RE3 and RE4 are connected in series between the collectors and the emitters respectively. The additional phase shift numerical control bias circuit, including: a common source common gate current mirror, 7 pairs of bipolar junction transistors (BJT) as switches, the emitter of each pair of BJT is connected in series to the same bit of the common source common gate current mirror, and the base of each pair of BJT is connected with a level signal X i and an opposite level signal generated by an inverter, wherein i=0~6; the base is connected with a level signal X i , and the collector interconnection node outputs a first control voltage VCTRL1; the base is connected with an opposite level signal , and the collector interconnection node outputs a second control voltage VCTRL2.

2. The microwave wideband differential variable gain amplifier of claim 1, wherein, The differential input signal of the differential structure variable gain amplification circuit is loaded to the base of common emitter tube T2 and the base of common emitter tube T4 through the input matching network.

3. The microwave wideband differential variable gain amplifier of claim 1, wherein, The input matching network includes: one end of inductor L1 and one end of inductor L3 are connected with one end of capacitor C1, the other end of capacitor C1 is connected with input power supply VIN+, one end of inductor L2 and one end of inductor L4 are connected with one end of capacitor C2, the other end of capacitor C2 is connected with input power supply VIN-, the other end of inductor L3 and the other end of inductor L4 are connected with ground through capacitor CB1 and capacitor CB2. The output matching network of the differential structure variable gain amplification circuit includes:

4. The microwave wideband differential variable gain amplifier of claim 1, wherein, Inductor LC1, inductor LC2, differential inductor LD, parallel resistor RC1 and resistor RC2, and the output end is connected through output DC blocking capacitor C3 and output DC blocking capacitor C4; the power supply VDD is loaded to the collector of common emitter tube T1 through the parallel structure of inductor LC1, differential inductor LD and resistor RC1, and is loaded to the collector of common emitter tube T3 through the parallel structure of inductor LC2, differential inductor LD and resistor RC2. The input return loss improvement circuit of the differential structure variable gain amplification circuit includes:

5. The microwave wideband differential variable gain amplifier of claim 1, wherein, The emitter of common emitter tube T2 and the emitter of common emitter tube T4 are connected in series with the series connection of resistor RE5 and capacitor CE2, and the series connection of resistor RE6 and capacitor CE1; the emitter of common emitter tube T2 and the emitter of common emitter tube T4 are connected in series with a center-grounded degeneration inductor LE. The power consumption control bias circuit of the differential structure variable gain amplification circuit includes:

6. The microwave wideband differential variable gain amplifier of claim 1, wherein, The power consumption control bias circuit is composed of triode T7 and resistors RB1 and RB2; the power supply VDD is directly loaded to the collector of triode T7, the bias voltage VBIAS is loaded to the base of triode T7, and the emitter of triode T7 is connected with the base of common emitter tube T2 and common emitter tube T4 through resistors RB1 and RB2. The common source current mirror is a common source current mirror designed by using equal proportion MOS tubes.

7. The microwave wideband differential variable gain amplifier of claim 1, wherein, The additional phase shift cancellation digital control bias circuit is provided with 7-bit digital control bits to control 34 kinds of gain states.

8. The microwave wideband differential variable gain amplifier of claim 1, wherein, The additional phase shift cancellation digital control bias circuit further includes:

9. The microwave wideband differential variable gain amplifier of claim 1, wherein, ​ The transistor T7 and the transistor T8 base connection fixed power supply VB, the transistor T7 and the transistor T8 emitter connection common source common gate current mirror.

10. The microwave wideband differential variable gain amplifier of claim 9, wherein, The additional phase shift cancellation digital control bias circuit further comprises: Base connection level signal X i The BJT collector and the transistor T7 collector are interconnected, and then the resistor R3, the transistor T9, and the resistor R1 are connected in series, and then the power supply VDD is connected. The base and the collector of the transistor T9 are interconnected and connected with the resistor R1. The emitter of the transistor T9 is connected with the resistor R3. The first control voltage VCTRL1 is output at the BJT collector interconnection node. Base connects opposite level signal BJT collector and transistor T8 collector are interconnected, and then connected in series with resistor R4, transistor T10, resistor R2, and then connected to power supply VDD. The base and collector of transistor T10 are interconnected and connected to resistor R2. The emitter of transistor T10 is connected to resistor R4. The second control voltage VCTRL2 is output at the BJT collector interconnection node.

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