Silicon nanowire array accelerometer with adjustable optimal operating point and its fabrication method

Abstract

This invention relates to a silicon nanowire array accelerometer with an adjustable optimal operating point and its fabrication method. The silicon nanowire array accelerometer includes silicon nanowire sensing elements, a mass block, a silicon nitride thin film, a gold electrode, a gate, and a silicon substrate. When the accelerometer is subjected to external acceleration, the up-and-down movement of the mass block causes deformation of the silicon nanowires, resulting in changes in the conductivity of the silicon nanowires and thus outputting a changing signal. Simultaneously, the gate of this invention can modulate the silicon nanowire channel, thereby finding the optimal operating point of the device. Furthermore, the gate structure effectively protects the silicon nanowires from breakage due to various reasons, greatly improving the long-term stability of the silicon nanowire device. The fabrication method of this invention is simple, low-cost, and can be mass-produced.

Description

Technical Field

[0001] This invention belongs to the field of accelerometer technology, specifically relating to a silicon nanowire array accelerometer with an adjustable optimal operating point and its fabrication method. Background Technology

[0002] Silicon nanowires are a novel type of one-dimensional nanomaterial. Subtle changes in the external environment can cause drastic changes in the material's properties, giving silicon nanowire devices high sensitivity. Currently, commercially available silicon nanowire devices cannot be adaptively adjusted for specific application scenarios, thus failing to reach their optimal operating point. Summary of the Invention

[0003] The purpose of this invention is to address the above-mentioned problems by providing a silicon nanowire array accelerometer with an adjustable optimal operating point and its fabrication method.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] The fabrication method of a silicon nanowire array accelerometer with adjustable optimal operating point includes the following steps:

[0006] S1. Select a (111) type SOI silicon wafer and prepare a silicon nitride thin film on its top silicon surface to form a dense dielectric mask layer;

[0007] S2. Transfer a small triangular array pattern on the dielectric mask layer and etch silicon nitride at the triangles to form a small triangular array window; then perform dry etching on the top silicon at the small triangular array window to obtain vertical small triangular trenches of the same depth to form a small triangular array trench, and then remove the photoresist.

[0008] S3. Oxidation of small triangular array trenches based on self-limiting thermal oxidation process;

[0009] S4. Transfer the large triangular array pattern on the dielectric mask layer and etch the silicon nitride at the triangles to form a large triangular array window; then perform dry etching on the top silicon at the large triangular array window to obtain vertical large triangular trenches of the same depth to form a large triangular array trench, and then remove the photoresist.

[0010] Among them, the small triangular array slots and the large triangular array slots form an array structure with a small vertical triangular slot in the middle of the area enclosed by three vertical large triangular slots as the array unit;

[0011] S5. Perform anisotropic wet etching on each vertical large triangular groove of the large triangular array to form a hexagonal etching array; among them, a single-crystal silicon thin-wall structure is formed between two adjacent hexagonal etching grooves, and a relative cone-like structure appears between the three hexagonal etching grooves of the same array unit.

[0012] S6. After the silicon wafer is oxidized based on the self-limiting thermal oxidation process, single-crystal silicon nanowires are formed at the top center of all single-crystal silicon thin-walled structures, forming a silicon nanowire array.

[0013] S7. Erase silicon nitride at appropriate locations on the silicon wafer to form square windows, implant boron ions into the square windows and then anneal them, and then fabricate the positive and negative electrodes.

[0014] S8. A gate is fabricated on a suspended silicon nitride thin film; the gate is used to adjust the channel of the silicon nanowire array;

[0015] S9. Create isolation channels at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes;

[0016] S10: Remove the oxidized single-crystal silicon thin-wall structure and release the entire structure.

[0017] As a preferred embodiment, the gate is located directly above the silicon nanowire, and the width of the gate is 1-100 μm.

[0018] As a preferred embodiment, the three vertical large triangular slots in the array unit are distributed such that two are located in the same row and the remaining one is located in another row.

[0019] As a preferred option, adjacent array elements share two vertical large triangular slots, and the four vertical large triangular slots are distributed with two in the same row and the other two in another row.

[0020] As a preferred embodiment, the number of array units is 2-1000.

[0021] As a preferred embodiment, the small triangular window is replaced with a circle or a square.

[0022] As a preferred embodiment, the preset width of the single-crystal silicon thin-walled structure is less than 1 μm.

[0023] As a preferred embodiment, the width of the single-crystal silicon nanowire is 10-800 nm.

[0024] The present invention also provides a silicon nanowire array accelerometer prepared by the processing method described in any of the preceding embodiments.

[0025] As a preferred solution, the silicon nanowire array accelerometer finds the optimal operating point of the accelerometer by adjusting the concentration of charge carriers in the silicon nanowire channel through the gate.

[0026] Compared with the prior art, the beneficial effects of the present invention are:

[0027] This invention utilizes a silicon nitride thin film and multiple silicon nanowires to support multiple mass blocks as the core structure of an accelerometer. This not only represents an innovation in device structure but also creatively fabricates a gate on the accelerometer. By modulating the gate to change the carrier concentration in the silicon nanowire channel, the optimal operating point of the accelerometer can be found. Furthermore, the gate structure effectively protects the silicon nanowires from breakage due to various reasons, significantly improving the long-term stability of the silicon nanowire device.

[0028] The silicon nanowire accelerometer of the present invention, due to the special design of silicon nanowires and mass block structure, can still work normally when the acceleration value is large, and can realize the fabrication of an accelerometer with an ultra-large range. Attached Figure Description

[0029] Figure 1A This is a schematic diagram of fabricating a silicon nitride thin film on the top silicon layer.

[0030] Figure 1B This is a partial schematic diagram of large and small triangular etching grooves being created on a silicon wafer.

[0031] Figure 1C This is a partial schematic diagram of the inclined hexagonal corrosion grooves formed by the large triangular array of wet corrosion.

[0032] Figure 1D This is a schematic diagram of silicon nanowires formed by thermal oxidation of thin-walled silicon nanowires.

[0033] Figure 1E This is a schematic diagram of the silicon nanowire-supported mass block after the entire structure has been released.

[0034] Figure 1F This is a schematic diagram of the accelerometer in Embodiment 1;

[0035] Figure 2 This is a schematic diagram of the accelerometer in Embodiment 2;

[0036] Figure 3 This is a schematic diagram of the accelerometer in Embodiment 3;

[0037] Figure 4A , Figure 4B and Figure 4C This is a photo of the large triangular groove after wet etching. Detailed Implementation

[0038] To more clearly illustrate the embodiments of the present invention, specific implementation methods will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0039] The silicon nanowire array accelerometer with adjustable optimal operating point of this invention mainly comprises silicon nanowires, a silicon nitride thin film, a mass block, a gold electrode, a gate, and a silicon substrate, with the gold electrode and gate on bulk silicon. The core structure of the accelerometer consists of multiple mass blocks supported by a silicon nitride thin film and multiple silicon nanowires, and the gate can modulate the silicon nanowire channel.

[0040] Specifically, the fabrication method of a silicon nanowire array accelerometer with an adjustable optimal operating point includes the following steps:

[0041] S1. Select a (111) type SOI silicon wafer, prepare a silicon nitride thin film on its top silicon surface to form a dense dielectric mask layer, transfer multiple triangular patterns through photolithography, and simultaneously perform RIE process to etch the silicon nitride at the triangular patterns to form a small triangular array window.

[0042] S2. Dry etching is performed on the silicon at the small triangular array window described in step S1 to prepare multiple vertical triangular trenches of the same depth, forming a small triangular array trench, and then the photoresist is removed.

[0043] S3. The small triangular array groove described in step S2 is oxidized based on a self-limiting thermal oxidation process.

[0044] S4. A large triangular array window is formed in the dielectric mask layer generated in step S1 by photolithography.

[0045] S5. Dry etching is performed on the silicon at the large triangular array window described in step S4, until the oxide layer of the SOI silicon wafer is etched, to prepare a vertical large triangular array trench.

[0046] S6. Remove the photoresist, and then perform anisotropic wet etching on the large triangular groove in step S5 to form a hexagonal array etching groove in which each sidewall belongs to the {111} crystal plane family. A single-crystal silicon thin-wall structure is formed between two adjacent hexagonal etching grooves, and a relative cone-like structure appears between every three adjacent hexagonal etching grooves.

[0047] S7. After oxidizing the silicon wafer using a self-limiting thermal oxidation process, single-crystal silicon nanowires are formed at the top center of all single-crystal silicon nanowalls.

[0048] S8. A square window is formed by etching silicon nitride at an appropriate location on the chip. Boron ions are implanted into the square window, followed by annealing. Then, a gold electrode is fabricated in this area. Finally, the gate is fabricated on the suspended silicon nitride film.

[0049] S9. Create isolation channels at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes of the device.

[0050] S10. Remove the silicon oxide thin-walled array using BOE (buffer oxide etching solution) to release the entire structure.

[0051] In a preferred embodiment, the silicon nitride thin film in step S1 is prepared using low-stress CVD thin film growth technology and the thickness of the silicon nitride thin film is 50nm-5μm.

[0052] In a preferred embodiment, the side length of the small triangular window formed in step S1 is 1-50 μm, and the window can also be a pattern such as a circle or a square.

[0053] In a preferred embodiment, the depth of the vertical small triangular grooves in step S2 is 1-100 μm.

[0054] In a preferred embodiment, the oxidation depth in step S3 is 100nm-20μm.

[0055] In a preferred embodiment, the large triangle array in step S4 consists of two basic units. The first basic unit has one triangle on top and two triangles below; the second basic unit has two triangles on top and one triangle below. The two basic units are arranged sequentially, and a triangle array is formed by 1 to 1000 such arrangements. It should also be noted that the large triangle array can also be composed of either of the basic units alone.

[0056] In a preferred embodiment, the depth of the vertical large triangular array slots in step S5 is 1-100 μm.

[0057] In a preferred embodiment, the solution in step S6 is a 10-80 wt% KOH solution at 10-100°C, and the wet etching time is 5 minutes to 10 hours.

[0058] In a preferred embodiment, the preset width of the single-crystal silicon thin-walled structure formed in step S6 is less than 1 μm.

[0059] In a preferred embodiment, the width of the single-crystal silicon nanowires formed in step S7 is 10-800 nm.

[0060] In a preferred embodiment, the ion implantation process in step S8 uses an ion implantation energy of 5-100 keV and an ion implantation metering of 0.1E15 cm⁻¹. -2 -10E15cm -2 The annealing temperature is 200-4000℃, and the annealing time is 5 minutes to 10 hours.

[0061] In a preferred embodiment, the gate in step S8 is located directly above the silicon nanowires and each silicon nanowire is covered by the gate, with a gate width of 1-100 μm.

[0062] In a preferred embodiment, the optimal operating point of the accelerometer can be found by adjusting the concentration of charge carriers in the silicon nanowire channel in step S8.

[0063] In a preferred embodiment, the isolation channel in step S9 is made by etching the silicon wafer down to or below the oxide layer.

[0064] In a preferred embodiment, the single-crystal silicon nanowires released in step S10 are protected by a gate fabricated in step S8.

[0065] The following detailed description is provided through specific embodiments:

[0066] Example 1:

[0067] The silicon nanowire array accelerometer with adjustable optimal operating point in this embodiment mainly includes silicon nanowires 8, a silicon nitride thin film 1, a mass block 9, a gold electrode 12, and a gate 13. When the accelerometer is subjected to external acceleration, the mass block 9 moves up and down, causing displacement. The movement of the mass block 9 causes deformation of the silicon nanowires 8, thereby affecting the conductivity of the silicon nanowires 8 and causing a change in the signal. The signal is output through the gold electrode 12. At the same time, the gate 13 of the accelerometer can modulate the carrier concentration in the silicon nanowire channel, thereby finding the optimal operating point of the accelerometer.

[0068] The fabrication method of the silicon nanowire array accelerometer with adjustable optimal operating point in this embodiment includes at least the following steps:

[0069] 1. First, select a (111) type SOI silicon wafer. On the surface of the top silicon layer 2 of the silicon wafer, a silicon nitride thin film 1 with a thickness of 50nm-5μm is prepared using low-stress CVD thin film growth technology to form a dense dielectric mask layer. Figure 1A As shown. The pattern of the small triangular array 14 is transferred using photolithography. RIE (Reverse Etching) is then performed on the small triangular array 14 to etch silicon nitride at the patterned areas, forming small triangular array windows. The side length of each small triangular window is 1-50 μm. Dry etching is then performed on the silicon at the small triangular array windows to fabricate vertical small triangular array trenches with uniform depths of 1-100 μm. The photoresist is removed, and the vertical small triangular array trenches are oxidized to a depth of 100 nm-20 μm using a self-confined thermal oxidation process. Figure 1B As shown.

[0070] 2. A large triangular array window 5 is formed on the silicon nitride layer 1 using photolithography. This large triangular array consists of two basic units: the first basic unit has one triangle on top and two triangles below; the second basic unit has two triangles below and one triangle on top. These two basic units are placed alternately to form the large triangular array in this embodiment. Dry etching is performed on the silicon at the window of the large triangular array 5, etching down to the silicon oxide layer 3 of the silicon wafer to prepare vertical large triangular trenches with depths of 1-100 μm, and then the photoresist is removed. Figure 1B and Figure 1E As shown.

[0071] 3. In a 10-80 wt% KOH solution at 10-100℃, anisotropic wet etching is performed on the silicon wafer for 5 minutes to 10 hours. The large triangular array 5 trenches in step 2 will be etched into hexagonal etching trenches 6, where each sidewall belongs to the {111} crystal plane family. Figure 1C , 4A As shown in 4B and 4C, a single-crystal silicon thin-walled structure 7 with a preset width of less than 1 μm is formed between two adjacent hexagonal etching grooves 6. Two opposing cone-like structures appear between every three adjacent etching grooves. The upper cone-like structure is the mass block 9 of the silicon nanowire array accelerometer (the suspension of the mass block requires two processes: one is breaking the small triangles, and the other is the subsequent BOE removal of the oxidized single-crystal silicon thin-walled structure to completely break it, thus achieving the suspension of the mass block). Figure 1C and Figure 1E As shown.

[0072] 4. After oxidizing the silicon wafer using a self-confined thermal oxidation process, a single-crystal silicon nanowire 8 will form at the very center of the top of all the single-crystal silicon nanowalls 7. For example... Figure 1D As shown.

[0073] 5. Silicon nitride is etched at the upper left and lower right corners of the chip to form square windows. Boron ions are implanted into the square windows, followed by annealing. The ion implantation energy is 5-100 keV, and the ion implantation metering is 0.1E15cm. -2 -10E15cm -2 The annealing temperature is 200-4000℃, and the annealing time is 5 minutes to 10 hours. Afterwards, a gold electrode 12 is fabricated in this area. Then, a gate electrode with a width of 1-100 μm is fabricated on the suspended silicon nitride. The fabricated gate electrode is directly above the silicon nanowires, and each silicon nanowire is covered with a gate electrode. At appropriate locations on the silicon wafer, the silicon wafer is etched down to the oxide layer 3 to fabricate the isolation channel 11 of the device, achieving physical isolation between the positive and negative electrodes. Figure 1F As shown.

[0074] 6. Remove the oxidized single-crystal silicon nanowalls from step 3 using BOE (buffer oxide etching solution) to release the entire structure.

[0075] Example 2:

[0076] This embodiment is basically the same as Embodiment 1 in terms of processing flow, but differs in device structure, such as... Figure 1F and Figure 2 As shown: The triangle arrays formed in steps 1 and 2 of this embodiment are different from those in embodiment 1. In this embodiment, the triangle array in step 2 is composed of one triangle on top and two triangles below as a basic unit, and several such basic units are used to form the triangle array of this embodiment.

[0077] The construction of isolation channels also differs. In this embodiment, isolation channels are constructed both between and within basic units. Isolation channels are constructed between the lower right and lower left triangles of every two adjacent basic units, and between the upper and lower right triangles within each basic unit.

[0078] In addition, the gate fabrication is also different. In this embodiment, since an isolation channel is fabricated inside the basic unit, the fabricated gate only needs to cover two silicon nanowires.

[0079] Other examples can be found in Example 1.

[0080] Example 3:

[0081] This embodiment is basically the same as Embodiment 1 in terms of processing flow, but differs in device structure, such as... Figure 1F and Figure 3 As shown, the triangular arrays formed in steps 1 and 2 of this embodiment are different from those in embodiment 1. In this embodiment, the triangular array in step 2 is composed of two triangles on top and one triangle on the bottom as a basic unit, and several such basic units are combined to form the triangular array of this embodiment.

[0082] The method of creating isolation channels also differs. In this embodiment, isolation channels are created both between basic units and within basic units. Isolation channels are created between the upper right and upper left triangles of every two adjacent basic units, and between the lower and upper right triangles within each basic unit.

[0083] In addition, the gate fabrication is also different. In this embodiment, since an isolation channel is fabricated inside the basic unit, the fabricated gate only needs to cover two silicon nanowires.

[0084] Other examples can be found in Example 1.

[0085] The above description is merely a detailed explanation of preferred embodiments and principles of the present invention. For those skilled in the art, there may be changes in specific implementation methods based on the ideas provided by the present invention, and these changes should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a silicon nanowire array accelerometer with an adjustable optimal operating point, characterized in that, Includes the following steps: S1. Select a (111) type SOI silicon wafer and prepare a silicon nitride thin film on its top silicon surface to form a dense dielectric mask layer; S2. Transfer a small triangular array pattern on the dielectric mask layer and etch silicon nitride at the triangles to form a small triangular array window; then perform dry etching on the top silicon at the small triangular array window to obtain vertical small triangular trenches of the same depth to form a small triangular array trench, and then remove the photoresist. S3. Oxidation of small triangular array trenches based on self-limiting thermal oxidation process; S4. Transfer the large triangular array pattern on the dielectric mask layer and etch the silicon nitride at the triangles to form a large triangular array window; then perform dry etching on the top silicon at the large triangular array window to obtain vertical large triangular trenches of the same depth to form a large triangular array trench, and then remove the photoresist. Among them, the small triangular array slots and the large triangular array slots form an array structure with a small vertical triangular slot in the middle of the area enclosed by three vertical large triangular slots as the array unit; S5. Perform anisotropic wet etching on each vertical large triangular groove of the large triangular array to form a hexagonal etching array; wherein, a single-crystal silicon thin-wall structure is formed between two adjacent hexagonal etching grooves, and a relative cone-like structure appears between the three hexagonal etching grooves in the same array unit. S6. After the silicon wafer is oxidized based on the self-limiting thermal oxidation process, single-crystal silicon nanowires are formed at the top center of all single-crystal silicon thin-walled structures, forming a silicon nanowire array. S7. Erase silicon nitride at appropriate locations on the silicon wafer to form square windows, implant boron ions into the square windows and then anneal them, and then fabricate the positive and negative electrodes. S8. A gate is fabricated on a suspended silicon nitride thin film; the gate is used to adjust the channel of the silicon nanowire array; S9. Create isolation channels at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes; S10: Remove the oxidized thin-walled structure of the single-crystal silicon and release the entire structure; When the accelerometer is subjected to external acceleration, the mass block will move up and down, causing displacement. The movement of the mass block will cause the silicon nanowire to deform, thereby affecting the conductivity of the silicon nanowire and thus causing changes in the signal. Silicon nanowire array accelerometers find the optimal operating point by adjusting the concentration of charge carriers in the silicon nanowire channel through the gate.

2. The processing method as described in claim 1, characterized in that, The gate is located directly above the silicon nanowire, and the gate width is 1-100 μm.

3. The processing method as described in claim 1, characterized in that, The three vertical large triangular slots in the array unit are distributed such that two are located in the same row and the remaining one is located in another row.

4. The processing method as described in claim 1, characterized in that, Adjacent array cells share two vertical large triangular slots, and the four vertical large triangular slots are distributed with two in the same row and the other two in another row.

5. The processing method as described in claim 3 or 4, characterized in that, The number of array units is 2-1000.

6. The processing method as described in claim 1, characterized in that, The small triangular array window is replaced with a circle or a square.

7. The processing method as described in claim 1, characterized in that, The preset width of the single-crystal silicon thin-walled structure is less than 1 μm.

8. The processing method as described in claim 1, characterized in that, The width of the single-crystal silicon nanowires is 10-800 nm.

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