A dynamic testing method and apparatus for a semiconductor device

Abstract

The application belongs to the technical field of semiconductor testing. Specifically provided are a dynamic testing method and device for a semiconductor device, which comprises compiling a configuration file according to the testing requirements of a testing task; the configuration file comprises a set of pulse control signals and constraint rules between each pulse control signal in the set; wherein the set comprises at least one pulse control signal; the correspondence between each pulse control signal and each trigger device is determined, and the corresponding pulse control signal is bound for each trigger device; based on the pulse control signal bound for each trigger device, the corresponding action device is controlled to act; wherein the configuration file and the pulse control signal bound for each trigger device support software modification. Based on the technical scheme provided in the application, only the configuration file needs to be updated when the testing timing is updated, which greatly improves the development efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device testing, and in particular to a dynamic testing method and device for semiconductor devices. BACKGROUND

[0002] With the development of semiconductor technology, the requirements for semiconductor device testing are becoming more and more stringent, and semiconductor device testing has gradually developed from static testing to dynamic testing.

[0003] Since dynamic testing has strict requirements on the action timing and action time of switches, digital-to-analog converters, analog-to-digital converters and other components, the prior art usually uses an FPGA as a controller, designs the control timing in advance through the FPGA, and burns the program into the FPGA. When the FPGA receives a trigger signal, it immediately performs sequential actions according to the designed timing, thereby achieving testing with timing requirements.

[0004] However, the above-mentioned testing method provided by the prior art has a major drawback. That is, every time the testing timing is modified, the FPGA needs to be reprogrammed and the program needs to be re-burned. Re-burning the logic file is equivalent to re-laying out and routing the internal circuit of the controller. Due to the complexity and high density of the internal circuit of the FPGA, for high-speed timing control, re-laying out and routing may introduce new internal line crosstalk (the internal line spacing will change after re-laying out and routing) or timing errors (the internal line length will change after re-laying out and routing). For testing equipment that requires high reliability, modifying the FPGA program usually requires a long verification period, which is very disadvantageous for the development of new testing requirements. SUMMARY

[0005] Therefore, the present application provides a dynamic testing method and device for semiconductor devices, which can effectively improve the dynamic parameter testing efficiency of components in the semiconductor testing process without the need to reprogram the FPGA or re-burn the program when the testing timing needs to be updated in the future.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application provides a dynamic testing method for semiconductor devices, comprising: writing a configuration file according to the testing requirements of a testing task; the configuration file comprises a set of pulse control signals and constraint rules between each pulse control signal in the set; wherein the set comprises at least one pulse control signal; determining the correspondence between each pulse control signal and each trigger device, and binding the corresponding pulse control signal to each trigger device; based on the pulse control signal bound to each trigger device, controlling the corresponding action device to act; wherein the configuration file and the pulse control signal bound to each trigger device support software modification.

[0007] From the above, the present application can directly configure and modify the new timing through software in the development process of the subsequent new timing by designing the configuration file supporting software modification in the logic module; the present application can also directly configure and modify through software when the pulse control signal needs to be bound to different trigger devices as the action trigger signal by designing the binding relationship supporting software modification in the logic module. The scheme can realize the dynamic test based on the new timing without modifying the logic code, without recompiling, and without rewiring, thereby improving the test efficiency of the dynamic parameter test of the semiconductor packaging link and improving the development efficiency.

[0008] As a possible implementation manner of the first aspect, the trigger device includes a switch control register, a digital-to-analog conversion trigger, and / or an analog-to-digital conversion trigger.

[0009] As a possible implementation manner of the first aspect, the action device includes a switch device, a digital-to-analog converter, and / or an analog-to-digital converter; the switch control register is configured to control the opening and closing of the switch device based on the pulse control signal; the digital-to-analog conversion trigger is configured to control the working state of the digital-to-analog converter based on the pulse control signal; and the analog-to-digital conversion trigger is configured to control the working state of the analog-to-digital converter based on the pulse control signal.

[0010] From the above, the opening and closing of the switch device are controlled through the switch control register, the working state of the digital-to-analog converter is controlled through the digital-to-analog conversion trigger, and the working state of the analog-to-digital converter is controlled through the analog-to-digital conversion trigger, thereby realizing the control of the corresponding action device through the pulse control signal bound to the corresponding trigger device to perform the action, and realizing the dynamic test of the device to be tested.

[0011] As a possible implementation manner of the first aspect, the method further includes generating a start signal to control the simultaneous start of the pulse control signals in the set.

[0012] As a possible implementation manner of the first aspect, the start signal is further configured to synchronously start other external related resources when the pulse control signals in the set are simultaneously started.

[0013] From the above, the start signal provided by the present application can also realize the synchronous start of other external related resources when the pulse control signals are started. In addition, if there is no synchronization requirement, the start signal can be used as a global start signal to control the simultaneous start of the pulse control signals.

[0014] The second aspect of the present application provides a dynamic testing device of a semiconductor device, comprising: a pulse generation module, configured to compile a pulse control signal set and constraint rules between each pulse control signal in the set according to testing requirements of a testing task; wherein the set comprises at least one pulse control signal; a binding matrix module, configured to determine a correspondence between the each pulse control signal and each trigger device, and bind the corresponding pulse control signal for the each trigger device; and an action control module, configured to control a corresponding action device to perform an action based on the pulse control signal bound for the each trigger device; wherein the pulse control signal set, the constraint rules between each pulse control signal in the set, and the pulse control signal bound for the each trigger device support software modification.

[0015] Based on the device provided in the present aspect, in the development process of subsequent new timing, the new timing and the constraint rules in the pulse generation module can be directly configured and modified by software, and in the subsequent new binding relationship, the binding relationship in the binding matrix module can be directly configured and modified by software, so that the dynamic testing based on the new timing is realized without modifying the logic code, without recompilation, and without rewiring, which not only improves the testing efficiency of the dynamic parameter testing of the semiconductor device in the semiconductor testing link, but also improves the development efficiency.

[0016] As a possible implementation manner of the second aspect, the device further comprises a global start module, configured to generate a start signal, wherein the start signal is used to control the simultaneous start of each pulse control signal in the set.

[0017] As a possible implementation manner of the second aspect, the global start module is further configured to synchronously start external other related resources when each pulse control signal in the set is simultaneously started.

[0018] The third aspect of the present application provides a computing device, comprising: a processor, and a memory; the memory has program instructions stored thereon, and the program instructions, when executed by the processor, cause the processor to execute the dynamic testing method of the semiconductor device according to any one of the first aspect.

[0019] The fourth aspect of the present application provides a computer readable storage medium, having program instructions stored thereon, and the program instructions, when executed by a computer, cause the computer to execute the dynamic testing method of the semiconductor device according to the first aspect.

[0020] These and other aspects of the present application will become more fully understood from the following description of (one or more) embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0021] The various technical features of the present application and the relationship between them will be further illustrated below with reference to the accompanying drawings. The drawings are exemplary, and some technical features are not shown in actual proportion, and some technical features in the drawings can be omitted, which are conventional in the technical field to which the present application belongs and are not essential to understanding and implementing the present application, or additional technical features are shown, which are not essential to understanding and implementing the present application, that is, the combination of various technical features shown in the drawings is not used to limit the present application. In addition, throughout the present application, the same reference signs refer to the same contents. The specific drawings are as follows:

[0022] Figure 1 A flow chart of a dynamic testing method of a semiconductor device provided for an embodiment of the present application;

[0023] Figure 2 A structural schematic diagram of a dynamic testing device of a semiconductor device provided for an embodiment of the present application;

[0024] Figure 3 An exemplary circuit structural diagram when DRon testing is performed on a GaN MOSFET provided for an embodiment of the present application;

[0025] Figure 4 A structural schematic diagram of a dynamic testing device of a semiconductor device when DRon testing is performed on GaN provided for an embodiment of the present application;

[0026] Figure 5 A structural schematic diagram of a computing device provided for an embodiment of the present application;

[0027] Figure 6 A structural schematic diagram of another computing device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0028] The words "first, second, third, etc." or module A, module B, module C, etc. in the specification and claims, or similar terms, are only used to distinguish similar objects, and can be understood that the specific order or sequence can be interchanged as allowed, so that the present application described herein can be implemented in an order other than that illustrated or described herein.

[0029] In the following description, the labels indicating steps such as S110, S120, etc. do not necessarily mean that the steps are executed in this order, and the order of the steps can be interchanged or executed simultaneously as allowed.

[0030] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0031] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0033] Referring to the figures below, a dynamic testing method for a semiconductor device provided in this application will be described in detail.

[0034] like Figure 1 The diagram shown is a flowchart of a dynamic testing method for a conductor device provided in an embodiment of this application. The implementation process of this method mainly includes steps S110-S130, which are described in detail below:

[0035] S110: Write a configuration file according to the test requirements of the test task; the configuration file includes a set of pulse control signals and constraint rules between each pulse control signal in the set.

[0036] It should be understood that the pulse control signal set can include one or more pulse control signals. That is, if only one pulse control signal is required in the corresponding test task, then the pulse control signal set can contain only one pulse control signal; if multiple pulse control signals are required in the corresponding test task, then the pulse control signal set can contain multiple pulse control signals.

[0037] The pulse control signals in the pulse control signal set are all supportable to be modified by software. Specifically, the time relationship between high and low levels in each pulse control signal is supportable to be modified by software, the meaning represented by high and low levels in each pulse control signal is supportable to be modified by software, and the number of pulse control signals contained in the pulse control signal set is supportable to be modified by software. The meaning represented by high and low levels in each pulse control signal includes, but is not limited to, that high level can represent opening or relationship, and low level can also represent opening or closing.

[0038] In the embodiment, the constraint rules between the pulse control signals can be determined according to test task requirements. For example, the constraint rule can be that high level or low level of a pulse control signal and high level or low level of another pulse control signal are not allowed to exist at the same time, and thus the constraint rule that high level or low level of the above two pulse control signals cannot exist at the same time is present to prevent damage to hardware. It should be understood that the constraint rule is only an example, and in other test tasks or other test stages of other embodiments, the constraint rule can also be other rules.

[0039] The constraint rules between the pulse control signals in the pulse control signal set are also supportable to be modified by software. It should be understood that the constraint rules can be modified by software to meet the needs of the current test task.

[0040] S120: Determine the correspondence between the pulse control signals and the trigger devices, and bind the corresponding pulse control signals to the trigger devices.

[0041] In the embodiment, the trigger devices include, but are not limited to, switch control registers, digital-to-analog conversion triggers, and / or analog-to-digital conversion triggers.

[0042] By binding the corresponding pulse control signals to the corresponding trigger devices, the trigger devices have an enabling signal for control action, thereby achieving the purpose of controlling the action of the action devices according to the specified timing.

[0043] The pulse control signals bound to the trigger devices are supportable to be modified by software. In a semiconductor device to be tested, there can be multiple trigger devices, and in a certain test task, most of them do not have to be used. Therefore, only the trigger devices needed in the test task are bound to the corresponding pulse control signals. The binding relationship between the two can be modified by software in different test requirements.

[0044] S130: Control the corresponding action devices to act based on the pulse control signals bound to the trigger devices.

[0045] In the embodiment, the action device includes: a switch device, a digital-to-analog converter, and / or an analog-to-digital converter; it is understood that the switch control register in step S120 is used to control the switch device to open and close at different timings based on the pulse control signal to which it is bound. The digital-to-analog conversion trigger in step S120 is used to control the digital-to-analog converter to switch between working states at different timings based on the pulse control signal to which it is bound, for example: the digital-to-analog converter acquires or outputs a voltage. The analog-to-digital conversion trigger in step S130 is used to control the analog-to-digital converter to switch between working states at different timings based on the pulse control signal to which it is bound.

[0046] In the embodiment, before steps S110-S130 are performed, a start signal can also be generated, by which the pulse control signals in the set can be controlled to start simultaneously. In the embodiment, in a working condition that needs to be synchronized with other resources, the start signal can also be used as a synchronization signal to achieve the simultaneous start of the pulse control signals in the set and the simultaneous start of external other related resources. The external related resources can include an external power supply, an external signal generator, an external oscilloscope, an external acquisition card, and other external instruments or other hardware resources.

[0047] Another embodiment of the application further provides a dynamic testing device of a semiconductor device. The dynamic testing device of the semiconductor device will be described in detail below with reference to the drawings.

[0048] As shown in Figure 2 Fig. 1 is a structural schematic diagram of a dynamic testing device of a semiconductor device provided by an embodiment of the application. The dynamic testing device 20 of the semiconductor device includes a global start module 210, a pulse generation module 220, a binding matrix module 230, and an action control module 240.

[0049] The global start module 210 is used to generate a start signal, by which the pulse control signals in the set can be controlled to start simultaneously; by which the external other related resources can also be started simultaneously when the pulse control signals in the set start simultaneously.

[0050] The pulse generation module 220 is used to write the pulse control signal set and the constraint rules between the pulse control signals in the set according to the test requirements of a test task. Referring to Figure 2The pulse generation module 220 is configured to generate a pulse control signal set, and the constraint rule is a constraint rule between pulse control signals in the pulse control signal set. The pulse generation module 220 can output an enable signal with the constraint rule to the binding matrix module 230. The number of pulse control signals in the pulse generation module 220 can be increased or decreased according to the actual test task.

[0051] The binding matrix module 230 is configured to receive the pulse control signal set with the constraint rule, determine the correspondence between the pulse control signals in the set and the trigger devices, and bind the corresponding pulse control signals to the trigger devices according to the determined correspondence. In this way, the pulse control signals can be bound to the trigger devices, so that the action devices controlled by the trigger devices can keep consistent with the high and low pads of the pulse.

[0052] The action control module 240 is configured to control the corresponding action devices to perform actions based on the pulse control signals bound to the trigger devices. The trigger devices and the action devices have a correspondence, the pulse control signals transmit corresponding pulse control information to the trigger devices, and the corresponding action devices of the trigger devices will follow the pulse control signals to perform corresponding actions. For example, when the trigger device is a switch control register, the switch corresponding to the switch control register will follow the pulse control signal to perform an action. For example, when the trigger device is an analog-to-digital conversion (ADC) trigger, the ADC corresponding to the ADC trigger will perform a related action. For example, when the trigger device is a digital-to-analog conversion (DAC) trigger, the DAC corresponding to the DAC trigger will perform a related action. In this embodiment, the ADC or the DAC is edge triggered, including but not limited to rising edge triggered, falling edge triggered, rising edge and falling edge triggered, rising edge or falling edge triggered. When the ADC or the DAC receives the corresponding trigger signal, the state machine of the ADC or the DAC will be triggered, and the task of starting to collect or output the voltage of the corresponding ADC or DAC will be controlled.

[0053] The following will take the dynamic resistance (Dynamic Ron, DRon) test of a gallium nitride power device (GaN) as an example to illustrate the dynamic test method and device of the semiconductor device provided in the embodiments of the present application.

[0054] As Figure 3An exemplary circuit diagram for DRon test of GaN MOSFET is shown. It includes a drive branch Q, a first analog-to-digital converter ADC1, a second analog-to-digital converter ADC2, a digital-to-analog converter DAC, a high voltage source HV, a low voltage source LV, a first switch K1, a second switch K2, a third switch K3, a first diode D1, a second diode D2, a resistor Shunt and a current source I. In this test task, the first switch K1, the second switch K2, the third switch K3, the drive branch Q, the analog-to-digital converter and the digital-to-analog converter DAC need to meet specific timing.

[0055] As shown in Figure 4 An exemplary structure diagram of a dynamic test device of a semiconductor device for DRon test of GaN MOSFET is shown.

[0056] First, the specific timing of the above device and the constraint rules between the timings are written into a configuration file. In this step, the pulse control signals of the first switch K1, the second switch K2, the third switch K3, the drive branch Q, the analog-to-digital converter ADC and the digital-to-analog converter DAC need to be written, i.e. Figure 4 Pulse 1-Pulse 6. In this test task, Pulse 3 cannot exist high level at the same time as Pulse 1, and Pulse 3 cannot exist high level at the same time as Pulse 2. Through the above written pulse control signals and constraint rules, the configuration file is stored in the pulse generation module 220.

[0057] Then, the corresponding pulse control signals are bound to the corresponding trigger devices through the binding matrix module 230. That is, Pulse 1 is bound to the first pin 1 of the switch control register, Pulse 2 is bound to the third pin 3 of the switch control register, Pulse 3 is bound to the second pin 2 of the switch control register, Pulse 4 is bound to the first pin 1 of the ADC trigger, Pulse 5 is bound to the fourth pin 4 of the switch control register, and Pulse 6 is bound to the first pin 1 of the DAC trigger.

[0058] In addition, the first pin 1 of the switch control register is also used to control the opening and closing of the first switch K1; the second pin 2 of the switch control register is also used to control the opening and closing of the second switch K2; the third pin 3 of the switch control register is also used to control the on-off of the drive branch Q; the fourth pin 4 of the switch control register is also used to control the opening and closing of the third switch K3; the first pin 1 of the ADC trigger is also used to control the working state of the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2, and the first pin 1 of the DAC trigger is also used to control the working state of the digital-to-analog converter DAC.

[0059] Through the binding relationship, the association of the pulse control signal and the action device is realized, and the action control module 240 controls the corresponding action device to act based on the pulse control signal bound by each trigger device.

[0060] In the embodiment, if the corresponding timing needs to be adjusted, only the content in the configuration file needs to be modified, the logic code does not need to be modified, and the new code does not need to be recompiled, thereby realizing high-speed dynamic configuration of the timing, and greatly improving the test efficiency and development efficiency.

[0061] The embodiment of the application further provides a computing device, including a processor and a memory. Figure 1 The method of the corresponding embodiment, or each optional embodiment therein.

[0062] Figure 5 is a structural schematic diagram of a computing device 900 provided by the embodiment of the application. The computing device 900 includes a processor 910 and a memory 920.

[0063] It should be understood that Figure 5 The computing device 900 shown in the embodiment can further include a communication interface 930, which can be used for communication with other devices.

[0064] The processor 910 can be connected with the memory 920. The memory 920 can be used for storing program codes and data. Therefore, the memory 920 can be an internal storage unit of the processor 910, can be an external storage unit independent of the processor 910, or can be a component including the internal storage unit of the processor 910 and the external storage unit independent of the processor 910.

[0065] Optionally, the computing device 900 can further include a bus. The memory 920 and the communication interface 930 can be connected with the processor 910 through the bus. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0066] It should be understood that the processor 910 can be a central processing unit (CPU) in the embodiments of the present application. The processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. Alternatively, the processor 910 can be one or more integrated circuits for performing related programs to implement the technical solutions provided by the embodiments of the present application.

[0067] The memory 920 can include read-only memory and random access memory, and provide instructions and data to the processor 910. Part of the processor 910 can also include non-volatile random access memory. For example, the processor 910 can also store device type information.

[0068] When the computing device 900 is running, the processor 910 executes computer execution instructions in the memory 920 to perform the operation steps of the above method.

[0069] It should be understood that the computing device 900 according to the embodiments of the present application can correspond to the execution of the corresponding subject in the method according to the embodiments of the present application, and the above and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding flow of each method of the embodiments, and for the sake of brevity, will not be repeated here.

[0070] The embodiments of the present application also provide another kind of computing device, as Figure 6 The structural schematic diagram of another computing device 1000 provided by the embodiment is shown, which includes a processor 1010 and an interface circuit 1020, wherein the processor 1010 accesses the memory through the interface circuit 1020, the memory stores program instructions, and the program instructions make the processor execute Figure 4 the method of the corresponding embodiment when the processor executes. In addition, the computing device can also include a communication interface, a bus, etc., which can be referred to the introduction in the embodiments shown in Figure 5 , and will not be repeated here. Exemplarily, the interface circuit 1020 can be a CAN bus or a LIN bus.

[0071] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0072] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0073] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0074] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0075] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0076] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0077] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The program is executed by a processor to perform a dynamic testing method of a semiconductor device. The method includes at least one of the schemes described in the various embodiments.

[0078] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0079] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is borne. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and can send, propagate or transmit a program for use by or in connection with an instruction execution system, device or apparatus.

[0080] The computer readable media on which the program code can be carried can be any appropriate media including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0081] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0082] It should be noted that the above-mentioned are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and all belong to the protection scope of the present application.

Claims

1. A method of dynamic testing of a semiconductor device, characterized by, The method is applied to a test circuit of a dynamic resistance of a gallium nitride power device, and the test circuit comprises a driving branch, a first analog-digital converter, a second analog-digital converter, a digital-analog converter, a high-voltage source, a low-voltage source, a first switch, a second switch, a third switch, a first diode, a second diode, a resistor and a current source, and the method comprises the following steps of: a configuration file is written according to a test requirement of a test task; the configuration file comprises a pulse control signal set of the first switch, the second switch, the third switch, the driving branch, the first analog-digital converter, the second analog-digital converter, the digital-analog converter and a constraint rule between each pulse control signal in the set; wherein the set comprises at least one pulse control signal; a corresponding relationship between each pulse control signal and each trigger device is determined, and a corresponding pulse control signal is bound for each trigger device, wherein the trigger device comprises a switch control register, a digital-analog conversion trigger and an analog-digital conversion trigger; the switch control register is used for controlling opening and closing of the first switch and the second switch, on-off of the driving branch and opening and closing of the third switch; the analog-digital conversion trigger is used for controlling working states of the first analog-digital converter and the second analog-digital converter, and the digital-analog conversion trigger is used for controlling a working state of the digital-analog converter; based on the pulse control signal bound for each trigger device, a corresponding action device is controlled to act; wherein the configuration file and the pulse control signal bound for each trigger device support software modification; meanings represented by high and low levels in each pulse control signal in the configuration file are supportable for software modification; and the constraint rule between each pulse control signal in the configuration file is supportable for software modification.

2. The method of claim 1, wherein, time relationships of high and low levels in each pulse control signal in the configuration file are supportable for software modification.

3. The method of claim 1, wherein, the constraint rule comprises: the first pulse control signal and the second pulse control signal are not allowed to simultaneously have high levels or low levels, wherein the pulse control signal set comprises the first pulse control signal and the second pulse control signal.

4. The method according to any one of claims 1 to 3, characterized in that, further comprising: a start signal is generated, and the start signal is used for controlling simultaneous starting of each pulse control signal in the set.

5. The method of claim 4, wherein, the start signal is further used for synchronously starting external other related resources when each pulse control signal in the set is simultaneously started.

6. A dynamic testing apparatus for a semiconductor device, characterized by comprising: The device is applied to a test circuit of a dynamic resistance of a gallium nitride power device, and the test circuit comprises a driving branch, a first analog-digital converter, a second analog-digital converter, a digital-analog converter, a high-voltage source, a low-voltage source, a first switch, a second switch, a third switch, a first diode, a second diode, a resistor and a current source, and the device comprises the following steps of: The pulse generation module is configured to write a configuration file according to test requirements of a test task, the configuration file including a pulse control signal set of the first switch, the second switch, the third switch, the driving branch, the first analog-digital converter, the second analog-digital converter, the digital-analog converter, and constraint rules between each pulse control signal in the set; the set includes at least one pulse control signal, wherein the trigger device includes a switch control register, a digital-analog conversion trigger, and an analog-digital conversion trigger; the switch control register is configured to control opening and closing of the first switch and the second switch, on-off of the driving branch, and opening and closing of the third switch; the analog-digital conversion trigger is configured to control working states of the first analog-digital converter and the second analog-digital converter; and the digital-analog conversion trigger is configured to control a working state of the digital-analog converter. The binding matrix module is configured to determine a correspondence between each pulse control signal and each trigger device, and bind a corresponding pulse control signal to each trigger device. The action control module is configured to control a corresponding action device to perform an action based on the pulse control signal bound to each trigger device. The pulse control signal set, the constraint rules between each pulse control signal in the set, and the pulse control signal bound to each trigger device support software modification; meanings of high and low levels in each pulse control signal in the configuration file are supportable for software modification; and the constraint rules between each pulse control signal in the configuration file are supportable for software modification.

7. The apparatus of claim 6, wherein, Further comprising: The global start module is configured to generate a start signal, the start signal being configured to control simultaneous starting of each pulse control signal in the set.

8. The apparatus of claim 7, wherein, The global start module is further configured to synchronously start external other related resources when each pulse control signal in the set is simultaneously started.

9. A computing device, comprising: The semiconductor device includes: A processor and a memory; The memory has program instructions stored thereon, the program instructions being configured to cause the processor to execute the dynamic test method of the semiconductor device according to any one of claims 1-5 when executed by the processor.

10. A computer-readable storage medium having stored thereon program instructions, wherein, The program instructions are configured to cause a computer to execute the dynamic test method of the semiconductor device according to any one of claims 1-5 when executed by the computer.

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